3
* Local APIC virtualization
5
* Copyright (C) 2006 Qumranet, Inc.
6
* Copyright (C) 2007 Novell
7
* Copyright (C) 2007 Intel
8
* Copyright 2009 Red Hat, Inc. and/or its affiliates.
11
* Dor Laor <dor.laor@qumranet.com>
12
* Gregory Haskins <ghaskins@novell.com>
13
* Yaozu (Eddie) Dong <eddie.dong@intel.com>
15
* Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17
* This work is licensed under the terms of the GNU GPL, version 2. See
18
* the COPYING file in the top-level directory.
21
#include <linux/kvm_host.h>
22
#include <linux/kvm.h>
24
#include <linux/highmem.h>
25
#include <linux/smp.h>
26
#include <linux/hrtimer.h>
28
#include <linux/module.h>
29
#include <linux/math64.h>
30
#include <linux/slab.h>
31
#include <asm/processor.h>
34
#include <asm/current.h>
35
#include <asm/apicdef.h>
36
#include <linux/atomic.h>
37
#include "kvm_cache_regs.h"
43
#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
45
#define mod_64(x, y) ((x) % (y))
53
#define APIC_BUS_CYCLE_NS 1
55
/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
56
#define apic_debug(fmt, arg...)
58
#define APIC_LVT_NUM 6
59
/* 14 is the version for Xeon and Pentium 8.4.8*/
60
#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
61
#define LAPIC_MMIO_LENGTH (1 << 12)
62
/* followed define is not in apicdef.h */
63
#define APIC_SHORT_MASK 0xc0000
64
#define APIC_DEST_NOSHORT 0x0
65
#define APIC_DEST_MASK 0x800
66
#define MAX_APIC_VECTOR 256
68
#define VEC_POS(v) ((v) & (32 - 1))
69
#define REG_POS(v) (((v) >> 5) << 4)
71
static unsigned int min_timer_period_us = 500;
72
module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
74
static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
76
return *((u32 *) (apic->regs + reg_off));
79
static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
81
*((u32 *) (apic->regs + reg_off)) = val;
84
static inline int apic_test_and_set_vector(int vec, void *bitmap)
86
return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89
static inline int apic_test_and_clear_vector(int vec, void *bitmap)
91
return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94
static inline void apic_set_vector(int vec, void *bitmap)
96
set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99
static inline void apic_clear_vector(int vec, void *bitmap)
101
clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104
static inline int apic_hw_enabled(struct kvm_lapic *apic)
106
return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
109
static inline int apic_sw_enabled(struct kvm_lapic *apic)
111
return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
114
static inline int apic_enabled(struct kvm_lapic *apic)
116
return apic_sw_enabled(apic) && apic_hw_enabled(apic);
120
(APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
123
(LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
124
APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
126
static inline int kvm_apic_id(struct kvm_lapic *apic)
128
return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
131
static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
133
return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
136
static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
138
return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
141
static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
143
return ((apic_get_reg(apic, APIC_LVTT) &
144
apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
147
static inline int apic_lvtt_period(struct kvm_lapic *apic)
149
return ((apic_get_reg(apic, APIC_LVTT) &
150
apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
153
static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
155
return ((apic_get_reg(apic, APIC_LVTT) &
156
apic->lapic_timer.timer_mode_mask) ==
157
APIC_LVT_TIMER_TSCDEADLINE);
160
static inline int apic_lvt_nmi_mode(u32 lvt_val)
162
return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
165
void kvm_apic_set_version(struct kvm_vcpu *vcpu)
167
struct kvm_lapic *apic = vcpu->arch.apic;
168
struct kvm_cpuid_entry2 *feat;
169
u32 v = APIC_VERSION;
171
if (!irqchip_in_kernel(vcpu->kvm))
174
feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
175
if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
176
v |= APIC_LVR_DIRECTED_EOI;
177
apic_set_reg(apic, APIC_LVR, v);
180
static inline int apic_x2apic_mode(struct kvm_lapic *apic)
182
return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
185
static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
186
LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
187
LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
188
LVT_MASK | APIC_MODE_MASK, /* LVTPC */
189
LINT_MASK, LINT_MASK, /* LVT0-1 */
190
LVT_MASK /* LVTERR */
193
static int find_highest_vector(void *bitmap)
196
int word_offset = MAX_APIC_VECTOR >> 5;
198
while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
201
if (likely(!word_offset && !word[0]))
204
return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
207
static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
209
apic->irr_pending = true;
210
return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
213
static inline int apic_search_irr(struct kvm_lapic *apic)
215
return find_highest_vector(apic->regs + APIC_IRR);
218
static inline int apic_find_highest_irr(struct kvm_lapic *apic)
222
if (!apic->irr_pending)
225
result = apic_search_irr(apic);
226
ASSERT(result == -1 || result >= 16);
231
static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
233
apic->irr_pending = false;
234
apic_clear_vector(vec, apic->regs + APIC_IRR);
235
if (apic_search_irr(apic) != -1)
236
apic->irr_pending = true;
239
int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
241
struct kvm_lapic *apic = vcpu->arch.apic;
244
/* This may race with setting of irr in __apic_accept_irq() and
245
* value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
246
* will cause vmexit immediately and the value will be recalculated
247
* on the next vmentry.
251
highest_irr = apic_find_highest_irr(apic);
256
static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
257
int vector, int level, int trig_mode);
259
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
261
struct kvm_lapic *apic = vcpu->arch.apic;
263
return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
264
irq->level, irq->trig_mode);
267
static inline int apic_find_highest_isr(struct kvm_lapic *apic)
271
result = find_highest_vector(apic->regs + APIC_ISR);
272
ASSERT(result == -1 || result >= 16);
277
static void apic_update_ppr(struct kvm_lapic *apic)
279
u32 tpr, isrv, ppr, old_ppr;
282
old_ppr = apic_get_reg(apic, APIC_PROCPRI);
283
tpr = apic_get_reg(apic, APIC_TASKPRI);
284
isr = apic_find_highest_isr(apic);
285
isrv = (isr != -1) ? isr : 0;
287
if ((tpr & 0xf0) >= (isrv & 0xf0))
292
apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
293
apic, ppr, isr, isrv);
295
if (old_ppr != ppr) {
296
apic_set_reg(apic, APIC_PROCPRI, ppr);
298
kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
302
static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
304
apic_set_reg(apic, APIC_TASKPRI, tpr);
305
apic_update_ppr(apic);
308
int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
310
return dest == 0xff || kvm_apic_id(apic) == dest;
313
int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
318
if (apic_x2apic_mode(apic)) {
319
logical_id = apic_get_reg(apic, APIC_LDR);
320
return logical_id & mda;
323
logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
325
switch (apic_get_reg(apic, APIC_DFR)) {
327
if (logical_id & mda)
330
case APIC_DFR_CLUSTER:
331
if (((logical_id >> 4) == (mda >> 0x4))
332
&& (logical_id & mda & 0xf))
336
apic_debug("Bad DFR vcpu %d: %08x\n",
337
apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
344
int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
345
int short_hand, int dest, int dest_mode)
348
struct kvm_lapic *target = vcpu->arch.apic;
350
apic_debug("target %p, source %p, dest 0x%x, "
351
"dest_mode 0x%x, short_hand 0x%x\n",
352
target, source, dest, dest_mode, short_hand);
355
switch (short_hand) {
356
case APIC_DEST_NOSHORT:
359
result = kvm_apic_match_physical_addr(target, dest);
362
result = kvm_apic_match_logical_addr(target, dest);
365
result = (target == source);
367
case APIC_DEST_ALLINC:
370
case APIC_DEST_ALLBUT:
371
result = (target != source);
374
apic_debug("kvm: apic: Bad dest shorthand value %x\n",
383
* Add a pending IRQ into lapic.
384
* Return 1 if successfully added and 0 if discarded.
386
static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
387
int vector, int level, int trig_mode)
390
struct kvm_vcpu *vcpu = apic->vcpu;
392
switch (delivery_mode) {
394
vcpu->arch.apic_arb_prio++;
396
/* FIXME add logic for vcpu on reset */
397
if (unlikely(!apic_enabled(apic)))
401
apic_debug("level trig mode for vector %d", vector);
402
apic_set_vector(vector, apic->regs + APIC_TMR);
404
apic_clear_vector(vector, apic->regs + APIC_TMR);
406
result = !apic_test_and_set_irr(vector, apic);
407
trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
408
trig_mode, vector, !result);
411
apic_debug("level trig mode repeatedly for "
412
"vector %d", vector);
416
kvm_make_request(KVM_REQ_EVENT, vcpu);
421
apic_debug("Ignoring delivery mode 3\n");
425
apic_debug("Ignoring guest SMI\n");
430
kvm_inject_nmi(vcpu);
437
vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
438
kvm_make_request(KVM_REQ_EVENT, vcpu);
441
apic_debug("Ignoring de-assert INIT to vcpu %d\n",
446
case APIC_DM_STARTUP:
447
apic_debug("SIPI to vcpu %d vector 0x%02x\n",
448
vcpu->vcpu_id, vector);
449
if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
451
vcpu->arch.sipi_vector = vector;
452
vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
453
kvm_make_request(KVM_REQ_EVENT, vcpu);
460
* Should only be called by kvm_apic_local_deliver() with LVT0,
461
* before NMI watchdog was enabled. Already handled by
462
* kvm_apic_accept_pic_intr().
467
printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
474
int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
476
return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
479
static void apic_set_eoi(struct kvm_lapic *apic)
481
int vector = apic_find_highest_isr(apic);
484
* Not every write EOI will has corresponding ISR,
485
* one example is when Kernel check timer on setup_IO_APIC
490
apic_clear_vector(vector, apic->regs + APIC_ISR);
491
apic_update_ppr(apic);
493
if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
494
trigger_mode = IOAPIC_LEVEL_TRIG;
496
trigger_mode = IOAPIC_EDGE_TRIG;
497
if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
498
kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
499
kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
502
static void apic_send_ipi(struct kvm_lapic *apic)
504
u32 icr_low = apic_get_reg(apic, APIC_ICR);
505
u32 icr_high = apic_get_reg(apic, APIC_ICR2);
506
struct kvm_lapic_irq irq;
508
irq.vector = icr_low & APIC_VECTOR_MASK;
509
irq.delivery_mode = icr_low & APIC_MODE_MASK;
510
irq.dest_mode = icr_low & APIC_DEST_MASK;
511
irq.level = icr_low & APIC_INT_ASSERT;
512
irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
513
irq.shorthand = icr_low & APIC_SHORT_MASK;
514
if (apic_x2apic_mode(apic))
515
irq.dest_id = icr_high;
517
irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
519
trace_kvm_apic_ipi(icr_low, irq.dest_id);
521
apic_debug("icr_high 0x%x, icr_low 0x%x, "
522
"short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
523
"dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
524
icr_high, icr_low, irq.shorthand, irq.dest_id,
525
irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
528
kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
531
static u32 apic_get_tmcct(struct kvm_lapic *apic)
537
ASSERT(apic != NULL);
539
/* if initial count is 0, current count should also be 0 */
540
if (apic_get_reg(apic, APIC_TMICT) == 0)
543
remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
544
if (ktime_to_ns(remaining) < 0)
545
remaining = ktime_set(0, 0);
547
ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
548
tmcct = div64_u64(ns,
549
(APIC_BUS_CYCLE_NS * apic->divide_count));
554
static void __report_tpr_access(struct kvm_lapic *apic, bool write)
556
struct kvm_vcpu *vcpu = apic->vcpu;
557
struct kvm_run *run = vcpu->run;
559
kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
560
run->tpr_access.rip = kvm_rip_read(vcpu);
561
run->tpr_access.is_write = write;
564
static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
566
if (apic->vcpu->arch.tpr_access_reporting)
567
__report_tpr_access(apic, write);
570
static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
574
if (offset >= LAPIC_MMIO_LENGTH)
579
if (apic_x2apic_mode(apic))
580
val = kvm_apic_id(apic);
582
val = kvm_apic_id(apic) << 24;
585
apic_debug("Access APIC ARBPRI register which is for P6\n");
588
case APIC_TMCCT: /* Timer CCR */
589
if (apic_lvtt_tscdeadline(apic))
592
val = apic_get_tmcct(apic);
596
report_tpr_access(apic, false);
599
apic_update_ppr(apic);
600
val = apic_get_reg(apic, offset);
607
static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
609
return container_of(dev, struct kvm_lapic, dev);
612
static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
615
unsigned char alignment = offset & 0xf;
617
/* this bitmask has a bit cleared for each reserver register */
618
static const u64 rmask = 0x43ff01ffffffe70cULL;
620
if ((alignment + len) > 4) {
621
apic_debug("KVM_APIC_READ: alignment error %x %d\n",
626
if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
627
apic_debug("KVM_APIC_READ: read reserved register %x\n",
632
result = __apic_read(apic, offset & ~0xf);
634
trace_kvm_apic_read(offset, result);
640
memcpy(data, (char *)&result + alignment, len);
643
printk(KERN_ERR "Local APIC read with len = %x, "
644
"should be 1,2, or 4 instead\n", len);
650
static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
652
return apic_hw_enabled(apic) &&
653
addr >= apic->base_address &&
654
addr < apic->base_address + LAPIC_MMIO_LENGTH;
657
static int apic_mmio_read(struct kvm_io_device *this,
658
gpa_t address, int len, void *data)
660
struct kvm_lapic *apic = to_lapic(this);
661
u32 offset = address - apic->base_address;
663
if (!apic_mmio_in_range(apic, address))
666
apic_reg_read(apic, offset, len, data);
671
static void update_divide_count(struct kvm_lapic *apic)
673
u32 tmp1, tmp2, tdcr;
675
tdcr = apic_get_reg(apic, APIC_TDCR);
677
tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
678
apic->divide_count = 0x1 << (tmp2 & 0x7);
680
apic_debug("timer divide count is 0x%x\n",
684
static void start_apic_timer(struct kvm_lapic *apic)
687
atomic_set(&apic->lapic_timer.pending, 0);
689
if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
690
/* lapic timer in oneshot or peroidic mode */
691
now = apic->lapic_timer.timer.base->get_time();
692
apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
693
* APIC_BUS_CYCLE_NS * apic->divide_count;
695
if (!apic->lapic_timer.period)
698
* Do not allow the guest to program periodic timers with small
699
* interval, since the hrtimers are not throttled by the host
702
if (apic_lvtt_period(apic)) {
703
s64 min_period = min_timer_period_us * 1000LL;
705
if (apic->lapic_timer.period < min_period) {
707
"kvm: vcpu %i: requested %lld ns "
708
"lapic timer period limited to %lld ns\n",
710
apic->lapic_timer.period, min_period);
711
apic->lapic_timer.period = min_period;
715
hrtimer_start(&apic->lapic_timer.timer,
716
ktime_add_ns(now, apic->lapic_timer.period),
719
apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
721
"timer initial count 0x%x, period %lldns, "
722
"expire @ 0x%016" PRIx64 ".\n", __func__,
723
APIC_BUS_CYCLE_NS, ktime_to_ns(now),
724
apic_get_reg(apic, APIC_TMICT),
725
apic->lapic_timer.period,
726
ktime_to_ns(ktime_add_ns(now,
727
apic->lapic_timer.period)));
728
} else if (apic_lvtt_tscdeadline(apic)) {
729
/* lapic timer in tsc deadline mode */
730
u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
732
struct kvm_vcpu *vcpu = apic->vcpu;
733
unsigned long this_tsc_khz = vcpu_tsc_khz(vcpu);
736
if (unlikely(!tscdeadline || !this_tsc_khz))
739
local_irq_save(flags);
741
now = apic->lapic_timer.timer.base->get_time();
742
guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
743
if (likely(tscdeadline > guest_tsc)) {
744
ns = (tscdeadline - guest_tsc) * 1000000ULL;
745
do_div(ns, this_tsc_khz);
747
hrtimer_start(&apic->lapic_timer.timer,
748
ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
750
local_irq_restore(flags);
754
static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
756
int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
758
if (apic_lvt_nmi_mode(lvt0_val)) {
759
if (!nmi_wd_enabled) {
760
apic_debug("Receive NMI setting on APIC_LVT0 "
761
"for cpu %d\n", apic->vcpu->vcpu_id);
762
apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
764
} else if (nmi_wd_enabled)
765
apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
768
static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
772
trace_kvm_apic_write(reg, val);
775
case APIC_ID: /* Local APIC ID */
776
if (!apic_x2apic_mode(apic))
777
apic_set_reg(apic, APIC_ID, val);
783
report_tpr_access(apic, true);
784
apic_set_tpr(apic, val & 0xff);
792
if (!apic_x2apic_mode(apic))
793
apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
799
if (!apic_x2apic_mode(apic))
800
apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
807
if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
808
mask |= APIC_SPIV_DIRECTED_EOI;
809
apic_set_reg(apic, APIC_SPIV, val & mask);
810
if (!(val & APIC_SPIV_APIC_ENABLED)) {
814
for (i = 0; i < APIC_LVT_NUM; i++) {
815
lvt_val = apic_get_reg(apic,
816
APIC_LVTT + 0x10 * i);
817
apic_set_reg(apic, APIC_LVTT + 0x10 * i,
818
lvt_val | APIC_LVT_MASKED);
820
atomic_set(&apic->lapic_timer.pending, 0);
826
/* No delay here, so we always clear the pending bit */
827
apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
832
if (!apic_x2apic_mode(apic))
834
apic_set_reg(apic, APIC_ICR2, val);
838
apic_manage_nmi_watchdog(apic, val);
843
/* TODO: Check vector */
844
if (!apic_sw_enabled(apic))
845
val |= APIC_LVT_MASKED;
847
val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
848
apic_set_reg(apic, reg, val);
853
if ((apic_get_reg(apic, APIC_LVTT) &
854
apic->lapic_timer.timer_mode_mask) !=
855
(val & apic->lapic_timer.timer_mode_mask))
856
hrtimer_cancel(&apic->lapic_timer.timer);
858
if (!apic_sw_enabled(apic))
859
val |= APIC_LVT_MASKED;
860
val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
861
apic_set_reg(apic, APIC_LVTT, val);
865
if (apic_lvtt_tscdeadline(apic))
868
hrtimer_cancel(&apic->lapic_timer.timer);
869
apic_set_reg(apic, APIC_TMICT, val);
870
start_apic_timer(apic);
875
apic_debug("KVM_WRITE:TDCR %x\n", val);
876
apic_set_reg(apic, APIC_TDCR, val);
877
update_divide_count(apic);
881
if (apic_x2apic_mode(apic) && val != 0) {
882
apic_debug("KVM_WRITE:ESR not zero %x\n", val);
888
if (apic_x2apic_mode(apic)) {
889
apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
898
apic_debug("Local APIC Write to read-only register %x\n", reg);
902
static int apic_mmio_write(struct kvm_io_device *this,
903
gpa_t address, int len, const void *data)
905
struct kvm_lapic *apic = to_lapic(this);
906
unsigned int offset = address - apic->base_address;
909
if (!apic_mmio_in_range(apic, address))
913
* APIC register must be aligned on 128-bits boundary.
914
* 32/64/128 bits registers must be accessed thru 32 bits.
917
if (len != 4 || (offset & 0xf)) {
918
/* Don't shout loud, $infamous_os would cause only noise. */
919
apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
925
/* too common printing */
926
if (offset != APIC_EOI)
927
apic_debug("%s: offset 0x%x with length 0x%x, and value is "
928
"0x%x\n", __func__, offset, len, val);
930
apic_reg_write(apic, offset & 0xff0, val);
935
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
937
struct kvm_lapic *apic = vcpu->arch.apic;
940
apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
942
EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
944
void kvm_free_lapic(struct kvm_vcpu *vcpu)
946
if (!vcpu->arch.apic)
949
hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
951
if (vcpu->arch.apic->regs)
952
free_page((unsigned long)vcpu->arch.apic->regs);
954
kfree(vcpu->arch.apic);
958
*----------------------------------------------------------------------
960
*----------------------------------------------------------------------
963
u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
965
struct kvm_lapic *apic = vcpu->arch.apic;
969
if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
972
return apic->lapic_timer.tscdeadline;
975
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
977
struct kvm_lapic *apic = vcpu->arch.apic;
981
if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
984
hrtimer_cancel(&apic->lapic_timer.timer);
985
apic->lapic_timer.tscdeadline = data;
986
start_apic_timer(apic);
989
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
991
struct kvm_lapic *apic = vcpu->arch.apic;
995
apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
996
| (apic_get_reg(apic, APIC_TASKPRI) & 4));
999
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1001
struct kvm_lapic *apic = vcpu->arch.apic;
1006
tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1008
return (tpr & 0xf0) >> 4;
1011
void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1013
struct kvm_lapic *apic = vcpu->arch.apic;
1016
value |= MSR_IA32_APICBASE_BSP;
1017
vcpu->arch.apic_base = value;
1021
if (!kvm_vcpu_is_bsp(apic->vcpu))
1022
value &= ~MSR_IA32_APICBASE_BSP;
1024
vcpu->arch.apic_base = value;
1025
if (apic_x2apic_mode(apic)) {
1026
u32 id = kvm_apic_id(apic);
1027
u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1028
apic_set_reg(apic, APIC_LDR, ldr);
1030
apic->base_address = apic->vcpu->arch.apic_base &
1031
MSR_IA32_APICBASE_BASE;
1033
/* with FSB delivery interrupt, we can restart APIC functionality */
1034
apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1035
"0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1039
void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1041
struct kvm_lapic *apic;
1044
apic_debug("%s\n", __func__);
1047
apic = vcpu->arch.apic;
1048
ASSERT(apic != NULL);
1050
/* Stop the timer in case it's a reset to an active apic */
1051
hrtimer_cancel(&apic->lapic_timer.timer);
1053
apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1054
kvm_apic_set_version(apic->vcpu);
1056
for (i = 0; i < APIC_LVT_NUM; i++)
1057
apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1058
apic_set_reg(apic, APIC_LVT0,
1059
SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1061
apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1062
apic_set_reg(apic, APIC_SPIV, 0xff);
1063
apic_set_reg(apic, APIC_TASKPRI, 0);
1064
apic_set_reg(apic, APIC_LDR, 0);
1065
apic_set_reg(apic, APIC_ESR, 0);
1066
apic_set_reg(apic, APIC_ICR, 0);
1067
apic_set_reg(apic, APIC_ICR2, 0);
1068
apic_set_reg(apic, APIC_TDCR, 0);
1069
apic_set_reg(apic, APIC_TMICT, 0);
1070
for (i = 0; i < 8; i++) {
1071
apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1072
apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1073
apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1075
apic->irr_pending = false;
1076
update_divide_count(apic);
1077
atomic_set(&apic->lapic_timer.pending, 0);
1078
if (kvm_vcpu_is_bsp(vcpu))
1079
vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1080
apic_update_ppr(apic);
1082
vcpu->arch.apic_arb_prio = 0;
1084
apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1085
"0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1086
vcpu, kvm_apic_id(apic),
1087
vcpu->arch.apic_base, apic->base_address);
1090
bool kvm_apic_present(struct kvm_vcpu *vcpu)
1092
return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1095
int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1097
return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1101
*----------------------------------------------------------------------
1103
*----------------------------------------------------------------------
1106
static bool lapic_is_periodic(struct kvm_timer *ktimer)
1108
struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1110
return apic_lvtt_period(apic);
1113
int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1115
struct kvm_lapic *lapic = vcpu->arch.apic;
1117
if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1118
return atomic_read(&lapic->lapic_timer.pending);
1123
static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1125
u32 reg = apic_get_reg(apic, lvt_type);
1126
int vector, mode, trig_mode;
1128
if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1129
vector = reg & APIC_VECTOR_MASK;
1130
mode = reg & APIC_MODE_MASK;
1131
trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1132
return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1137
void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1139
struct kvm_lapic *apic = vcpu->arch.apic;
1142
kvm_apic_local_deliver(apic, APIC_LVT0);
1145
static struct kvm_timer_ops lapic_timer_ops = {
1146
.is_periodic = lapic_is_periodic,
1149
static const struct kvm_io_device_ops apic_mmio_ops = {
1150
.read = apic_mmio_read,
1151
.write = apic_mmio_write,
1154
int kvm_create_lapic(struct kvm_vcpu *vcpu)
1156
struct kvm_lapic *apic;
1158
ASSERT(vcpu != NULL);
1159
apic_debug("apic_init %d\n", vcpu->vcpu_id);
1161
apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1165
vcpu->arch.apic = apic;
1167
apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1169
printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1171
goto nomem_free_apic;
1175
hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1177
apic->lapic_timer.timer.function = kvm_timer_fn;
1178
apic->lapic_timer.t_ops = &lapic_timer_ops;
1179
apic->lapic_timer.kvm = vcpu->kvm;
1180
apic->lapic_timer.vcpu = vcpu;
1182
apic->base_address = APIC_DEFAULT_PHYS_BASE;
1183
vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1185
kvm_lapic_reset(vcpu);
1186
kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1195
int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1197
struct kvm_lapic *apic = vcpu->arch.apic;
1200
if (!apic || !apic_enabled(apic))
1203
apic_update_ppr(apic);
1204
highest_irr = apic_find_highest_irr(apic);
1205
if ((highest_irr == -1) ||
1206
((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1211
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1213
u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1216
if (!apic_hw_enabled(vcpu->arch.apic))
1218
if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1219
GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1224
void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1226
struct kvm_lapic *apic = vcpu->arch.apic;
1228
if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1229
if (kvm_apic_local_deliver(apic, APIC_LVTT))
1230
atomic_dec(&apic->lapic_timer.pending);
1234
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1236
int vector = kvm_apic_has_interrupt(vcpu);
1237
struct kvm_lapic *apic = vcpu->arch.apic;
1242
apic_set_vector(vector, apic->regs + APIC_ISR);
1243
apic_update_ppr(apic);
1244
apic_clear_irr(vector, apic);
1248
void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1250
struct kvm_lapic *apic = vcpu->arch.apic;
1252
apic->base_address = vcpu->arch.apic_base &
1253
MSR_IA32_APICBASE_BASE;
1254
kvm_apic_set_version(vcpu);
1256
apic_update_ppr(apic);
1257
hrtimer_cancel(&apic->lapic_timer.timer);
1258
update_divide_count(apic);
1259
start_apic_timer(apic);
1260
apic->irr_pending = true;
1261
kvm_make_request(KVM_REQ_EVENT, vcpu);
1264
void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1266
struct kvm_lapic *apic = vcpu->arch.apic;
1267
struct hrtimer *timer;
1272
timer = &apic->lapic_timer.timer;
1273
if (hrtimer_cancel(timer))
1274
hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1277
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1282
if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1285
vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1286
data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1287
kunmap_atomic(vapic, KM_USER0);
1289
apic_set_tpr(vcpu->arch.apic, data & 0xff);
1292
void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1295
int max_irr, max_isr;
1296
struct kvm_lapic *apic;
1299
if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1302
apic = vcpu->arch.apic;
1303
tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1304
max_irr = apic_find_highest_irr(apic);
1307
max_isr = apic_find_highest_isr(apic);
1310
data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1312
vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1313
*(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1314
kunmap_atomic(vapic, KM_USER0);
1317
void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1319
if (!irqchip_in_kernel(vcpu->kvm))
1322
vcpu->arch.apic->vapic_addr = vapic_addr;
1325
int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1327
struct kvm_lapic *apic = vcpu->arch.apic;
1328
u32 reg = (msr - APIC_BASE_MSR) << 4;
1330
if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1333
/* if this is ICR write vector before command */
1335
apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1336
return apic_reg_write(apic, reg, (u32)data);
1339
int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1341
struct kvm_lapic *apic = vcpu->arch.apic;
1342
u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1344
if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1347
if (apic_reg_read(apic, reg, 4, &low))
1350
apic_reg_read(apic, APIC_ICR2, 4, &high);
1352
*data = (((u64)high) << 32) | low;
1357
int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1359
struct kvm_lapic *apic = vcpu->arch.apic;
1361
if (!irqchip_in_kernel(vcpu->kvm))
1364
/* if this is ICR write vector before command */
1365
if (reg == APIC_ICR)
1366
apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1367
return apic_reg_write(apic, reg, (u32)data);
1370
int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1372
struct kvm_lapic *apic = vcpu->arch.apic;
1375
if (!irqchip_in_kernel(vcpu->kvm))
1378
if (apic_reg_read(apic, reg, 4, &low))
1380
if (reg == APIC_ICR)
1381
apic_reg_read(apic, APIC_ICR2, 4, &high);
1383
*data = (((u64)high) << 32) | low;