2
* m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
4
* (C) 1999-2000 Magnus Damm <damm@opensource.se>
5
* (C) 2001-2002 Montavista Software, Inc.
8
* Support for two slots by Cyclades Corporation
9
* <oliver.kurth@cyclades.de>
10
* Further fixes, v2.6 kernel port
11
* <marcelo.tosatti@cyclades.com>
13
* Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
14
* <vbordug@ru.mvista.com>
16
* "The ExCA standard specifies that socket controllers should provide
17
* two IO and five memory windows per socket, which can be independently
18
* configured and positioned in the host address space and mapped to
19
* arbitrary segments of card address space. " - David A Hinds. 1999
21
* This controller does _not_ meet the ExCA standard.
23
* m8xx pcmcia controller brief info:
24
* + 8 windows (attrib, mem, i/o)
25
* + up to two slots (SLOT_A and SLOT_B)
26
* + inputpins, outputpins, event and mask registers.
27
* - no offset register. sigh.
29
* Because of the lacking offset register we must map the whole card.
30
* We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31
* Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32
* * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33
* The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34
* They are maximum 64KByte each...
37
#include <linux/module.h>
38
#include <linux/init.h>
39
#include <linux/types.h>
40
#include <linux/fcntl.h>
41
#include <linux/string.h>
43
#include <linux/kernel.h>
44
#include <linux/errno.h>
45
#include <linux/timer.h>
46
#include <linux/ioport.h>
47
#include <linux/delay.h>
48
#include <linux/interrupt.h>
49
#include <linux/fsl_devices.h>
50
#include <linux/bitops.h>
51
#include <linux/of_device.h>
52
#include <linux/of_platform.h>
55
#include <asm/system.h>
57
#include <asm/mpc8xx.h>
58
#include <asm/8xx_immap.h>
60
#include <asm/fs_pd.h>
62
#include <pcmcia/ss.h>
64
#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
65
#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
67
static const char *version = "Version 0.06, Aug 2005";
68
MODULE_LICENSE("Dual MPL/GPL");
70
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
72
/* The RPX series use SLOT_B */
73
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
74
#define CONFIG_PCMCIA_SLOT_B
75
#define CONFIG_BD_IS_MHZ
78
/* The ADS board use SLOT_A */
80
#define CONFIG_PCMCIA_SLOT_A
81
#define CONFIG_BD_IS_MHZ
84
/* The FADS series are a mess */
86
#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
87
#define CONFIG_PCMCIA_SLOT_A
89
#define CONFIG_PCMCIA_SLOT_B
93
#if defined(CONFIG_MPC885ADS)
94
#define CONFIG_PCMCIA_SLOT_A
95
#define PCMCIA_GLITCHY_CD
98
/* Cyclades ACS uses both slots */
100
#define CONFIG_PCMCIA_SLOT_A
101
#define CONFIG_PCMCIA_SLOT_B
104
#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
106
#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
108
#define PCMCIA_SOCKETS_NO 2
109
/* We have only 8 windows, dualsocket support will be limited. */
110
#define PCMCIA_MEM_WIN_NO 2
111
#define PCMCIA_IO_WIN_NO 2
112
#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
114
#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
116
#define PCMCIA_SOCKETS_NO 1
117
/* full support for one slot */
118
#define PCMCIA_MEM_WIN_NO 5
119
#define PCMCIA_IO_WIN_NO 2
121
/* define _slot_ to be able to optimize macros */
123
#ifdef CONFIG_PCMCIA_SLOT_A
125
#define PCMCIA_SLOT_MSG "SLOT_A"
128
#define PCMCIA_SLOT_MSG "SLOT_B"
132
#error m8xx_pcmcia: Bad configuration!
135
/* ------------------------------------------------------------------------- */
137
#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
138
#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
139
#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
140
/* ------------------------------------------------------------------------- */
142
static int pcmcia_schlvl;
144
static DEFINE_SPINLOCK(events_lock);
146
#define PCMCIA_SOCKET_KEY_5V 1
147
#define PCMCIA_SOCKET_KEY_LV 2
149
/* look up table for pgcrx registers */
150
static u32 *m8xx_pgcrx[2];
153
* This structure is used to address each window in the PCMCIA controller.
155
* Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
156
* after pcmcia_win[n]...
165
* For some reason the hardware guys decided to make both slots share
168
* Could someone invent object oriented hardware ?
170
* The macros are used to get the right bit from the registers.
175
#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
176
#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
177
#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
178
#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
180
#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
181
#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
182
#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
183
#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
184
#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
185
#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
186
#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
187
#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
188
#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
189
#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
190
#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
192
#define M8XX_PCMCIA_POR_VALID 0x00000001
193
#define M8XX_PCMCIA_POR_WRPROT 0x00000002
194
#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
195
#define M8XX_PCMCIA_POR_IO 0x00000018
196
#define M8XX_PCMCIA_POR_16BIT 0x00000040
198
#define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
200
#define M8XX_PGCRX_CXOE 0x00000080
201
#define M8XX_PGCRX_CXRESET 0x00000040
203
/* we keep one lookup table per socket to check flags */
205
#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
212
static const char driver_name[] = "m8xx-pcmcia";
215
void (*handler) (void *info, u32 events);
219
pcmconf8xx_t *pcmcia;
223
socket_state_t state;
224
struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
225
struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
226
struct event_table events[PCMCIA_EVENTS_MAX];
227
struct pcmcia_socket socket;
230
static struct socket_info socket[PCMCIA_SOCKETS_NO];
233
* Search this table to see if the windowsize is
237
#define M8XX_SIZES_NO 32
239
static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
240
0x00000001, 0x00000002, 0x00000008, 0x00000004,
241
0x00000080, 0x00000040, 0x00000010, 0x00000020,
242
0x00008000, 0x00004000, 0x00001000, 0x00002000,
243
0x00000100, 0x00000200, 0x00000800, 0x00000400,
245
0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
246
0x01000000, 0x02000000, 0xffffffff, 0x04000000,
247
0x00010000, 0x00020000, 0x00080000, 0x00040000,
248
0x00800000, 0x00400000, 0x00100000, 0x00200000
251
/* ------------------------------------------------------------------------- */
253
static irqreturn_t m8xx_interrupt(int irq, void *dev);
255
#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
257
/* ------------------------------------------------------------------------- */
258
/* board specific stuff: */
259
/* voltage_set(), hardware_enable() and hardware_disable() */
260
/* ------------------------------------------------------------------------- */
261
/* RPX Boards from Embedded Planet */
263
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
265
/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
266
* SYPCR is write once only, therefore must the slowest memory be faster
267
* than the bus monitor or we will get a machine check due to the bus timeout.
270
#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
272
#undef PCMCIA_BMT_LIMIT
273
#define PCMCIA_BMT_LIMIT (6*8)
275
static int voltage_set(int slot, int vcc, int vpp)
283
reg |= BCSR1_PCVCTL4;
286
reg |= BCSR1_PCVCTL5;
298
reg |= BCSR1_PCVCTL6;
303
reg |= BCSR1_PCVCTL7;
308
if (!((vcc == 50) || (vcc == 0)))
311
/* first, turn off all power */
313
out_be32(((u32 *) RPX_CSR_ADDR),
314
in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
319
/* enable new powersettings */
321
out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
326
#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
327
#define hardware_enable(_slot_) /* No hardware to enable */
328
#define hardware_disable(_slot_) /* No hardware to disable */
330
#endif /* CONFIG_RPXCLASSIC */
332
/* FADS Boards from Motorola */
334
#if defined(CONFIG_FADS)
336
#define PCMCIA_BOARD_MSG "FADS"
338
static int voltage_set(int slot, int vcc, int vpp)
346
reg |= BCSR1_PCCVCC0;
349
reg |= BCSR1_PCCVCC1;
361
reg |= BCSR1_PCCVPP1;
366
if ((vcc == 33) || (vcc == 50))
367
reg |= BCSR1_PCCVPP0;
374
/* first, turn off all power */
375
out_be32((u32 *) BCSR1,
376
in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
379
/* enable new powersettings */
380
out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
385
#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
387
static void hardware_enable(int slot)
389
out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
392
static void hardware_disable(int slot)
394
out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
399
/* MPC885ADS Boards */
401
#if defined(CONFIG_MPC885ADS)
403
#define PCMCIA_BOARD_MSG "MPC885ADS"
404
#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
406
static inline void hardware_enable(int slot)
408
m8xx_pcmcia_ops.hw_ctrl(slot, 1);
411
static inline void hardware_disable(int slot)
413
m8xx_pcmcia_ops.hw_ctrl(slot, 0);
416
static inline int voltage_set(int slot, int vcc, int vpp)
418
return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
423
/* ------------------------------------------------------------------------- */
424
/* Motorola MBX860 */
426
#if defined(CONFIG_MBX)
428
#define PCMCIA_BOARD_MSG "MBX"
430
static int voltage_set(int slot, int vcc, int vpp)
458
if ((vcc == 33) || (vcc == 50))
466
/* first, turn off all power */
467
out_8((u8 *) MBX_CSR2_ADDR,
468
in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
470
/* enable new powersettings */
471
out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg);
476
#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
477
#define hardware_enable(_slot_) /* No hardware to enable */
478
#define hardware_disable(_slot_) /* No hardware to disable */
480
#endif /* CONFIG_MBX */
482
#if defined(CONFIG_PRxK)
483
#include <asm/cpld.h>
484
extern volatile fpga_pc_regs *fpga_pc;
486
#define PCMCIA_BOARD_MSG "MPC855T"
488
static int voltage_set(int slot, int vcc, int vpp)
492
cpld_regs *ccpld = get_cpld();
498
reg |= PCMCIA_VCC_33;
501
reg |= PCMCIA_VCC_50;
513
reg |= PCMCIA_VPP_VCC;
518
if ((vcc == 33) || (vcc == 50))
519
reg |= PCMCIA_VPP_12;
526
reg = reg >> (slot << 2);
527
regread = in_8(&ccpld->fpga_pc_ctl);
529
(regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
530
/* enable new powersettings */
532
regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
534
out_8(&ccpld->fpga_pc_ctl, reg | regread);
541
#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
542
#define hardware_enable(_slot_) /* No hardware to enable */
543
#define hardware_disable(_slot_) /* No hardware to disable */
545
#endif /* CONFIG_PRxK */
547
static u32 pending_events[PCMCIA_SOCKETS_NO];
548
static DEFINE_SPINLOCK(pending_event_lock);
550
static irqreturn_t m8xx_interrupt(int irq, void *dev)
552
struct socket_info *s;
553
struct event_table *e;
554
unsigned int i, events, pscr, pipr, per;
555
pcmconf8xx_t *pcmcia = socket[0].pcmcia;
557
pr_debug("m8xx_pcmcia: Interrupt!\n");
558
/* get interrupt sources */
560
pscr = in_be32(&pcmcia->pcmc_pscr);
561
pipr = in_be32(&pcmcia->pcmc_pipr);
562
per = in_be32(&pcmcia->pcmc_per);
564
for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
570
if (pscr & e->regbit)
571
events |= e->eventbit;
577
* report only if both card detect signals are the same
579
* we depend on that CD2 is the bit to the left of CD1...
581
if (events & SS_DETECT)
582
if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
583
(pipr & M8XX_PCMCIA_CD1(i))) {
584
events &= ~SS_DETECT;
586
#ifdef PCMCIA_GLITCHY_CD
588
* I've experienced CD problems with my ADS board.
589
* We make an extra check to see if there was a
590
* real change of Card detection.
593
if ((events & SS_DETECT) &&
595
(M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
596
(s->state.Vcc | s->state.Vpp)) {
597
events &= ~SS_DETECT;
598
/*printk( "CD glitch workaround - CD = 0x%08x!\n",
599
(pipr & (M8XX_PCMCIA_CD2(i)
600
| M8XX_PCMCIA_CD1(i)))); */
604
/* call the handler */
606
pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, "
607
"pipr = 0x%08x\n", i, events, pscr, pipr);
610
spin_lock(&pending_event_lock);
611
pending_events[i] |= events;
612
spin_unlock(&pending_event_lock);
614
* Turn off RDY_L bits in the PER mask on
615
* CD interrupt receival.
617
* They can generate bad interrupts on the
618
* ACS4,8,16,32. - marcelo
620
per &= ~M8XX_PCMCIA_RDY_L(0);
621
per &= ~M8XX_PCMCIA_RDY_L(1);
623
out_be32(&pcmcia->pcmc_per, per);
626
pcmcia_parse_events(&socket[i].socket, events);
630
/* clear the interrupt sources */
631
out_be32(&pcmcia->pcmc_pscr, pscr);
633
pr_debug("m8xx_pcmcia: Interrupt done.\n");
638
static u32 m8xx_get_graycode(u32 size)
642
for (k = 0; k < M8XX_SIZES_NO; k++)
643
if (m8xx_size_to_gray[k] == size)
646
if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
652
static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
654
u32 reg, clocks, psst, psl, psht;
659
* We get called with IO maps setup to 0ns
660
* if not specified by the user.
661
* They should be 255ns.
667
ns = 100; /* fast memory if 0 */
671
* In PSST, PSL, PSHT fields we tell the controller
672
* timing parameters in CLKOUT clock cycles.
673
* CLKOUT is the same as GCLK2_50.
676
/* how we want to adjust the timing - in percent */
678
#define ADJ 180 /* 80 % longer accesstime - to be sure */
680
clocks = ((bus_freq / 1000) * ns) / 1000;
681
clocks = (clocks * ADJ) / (100 * 1000);
682
if (clocks >= PCMCIA_BMT_LIMIT) {
683
printk("Max access time limit reached\n");
684
clocks = PCMCIA_BMT_LIMIT - 1;
687
psst = clocks / 7; /* setup time */
688
psht = clocks / 7; /* hold time */
689
psl = (clocks * 5) / 7; /* strobe length */
691
psst += clocks - (psst + psht + psl);
700
static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
702
int lsock = container_of(sock, struct socket_info, socket)->slot;
703
struct socket_info *s = &socket[lsock];
704
unsigned int pipr, reg;
705
pcmconf8xx_t *pcmcia = s->pcmcia;
707
pipr = in_be32(&pcmcia->pcmc_pipr);
709
*value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
710
| M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
711
*value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
713
if (s->state.flags & SS_IOCARD)
714
*value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
716
*value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
717
*value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
718
*value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
721
if (s->state.Vcc | s->state.Vpp)
722
*value |= SS_POWERON;
726
* This driver only supports 16-Bit pc-cards.
727
* Cardbus is not handled here.
729
* To determine what voltage to use we must read the VS1 and VS2 pin.
730
* Depending on what socket type is present,
731
* different combinations mean different things.
733
* Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
735
* 5V 5V, LV* NC NC 5V only 5V (if available)
737
* 5V 5V, LV* GND NC 5 or 3.3V as low as possible
739
* 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
741
* LV* 5V - - shall not fit into socket
743
* LV* LV* GND NC 3.3V only 3.3V
745
* LV* LV* NC GND x.xV x.xV (if avail.)
747
* LV* LV* GND GND 3.3 or x.xV as low as possible
749
* *LV means Low Voltage
752
* That gives us the following table:
754
* Socket VS1 VS2 Voltage
757
* 5V NC GND none (should not be possible)
761
* LV NC NC 5V (if available)
762
* LV NC GND x.xV (if available)
766
* So, how do I determine if I have a 5V or a LV
767
* socket on my board? Look at the socket!
770
* Socket with 5V key:
771
* ++--------------------------------------------+
776
* +---------------------------------------------+
778
* Socket with LV key:
779
* ++--------------------------------------------+
784
* +---------------------------------------------+
787
* With other words - LV only cards does not fit
788
* into the 5V socket!
791
/* read out VS1 and VS2 */
793
reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
794
>> M8XX_PCMCIA_VS_SHIFT(lsock);
796
if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
800
break; /* GND, NC - 3.3V only */
803
break; /* NC. GND - x.xV only */
807
pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value);
811
static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
813
int lsock = container_of(sock, struct socket_info, socket)->slot;
814
struct socket_info *s = &socket[lsock];
815
struct event_table *e;
818
pcmconf8xx_t *pcmcia = socket[0].pcmcia;
820
pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
821
"io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
822
state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
824
/* First, set voltage - bail out if invalid */
825
if (voltage_set(lsock, state->Vcc, state->Vpp))
828
/* Take care of reset... */
829
if (state->flags & SS_RESET)
830
out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
832
out_be32(M8XX_PGCRX(lsock),
833
in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
835
/* ... and output enable. */
837
/* The CxOE signal is connected to a 74541 on the ADS.
838
I guess most other boards used the ADS as a reference.
839
I tried to control the CxOE signal with SS_OUTPUT_ENA,
840
but the reset signal seems connected via the 541.
841
If the CxOE is left high are some signals tristated and
842
no pullups are present -> the cards act weird.
843
So right now the buffers are enabled if the power is on. */
845
if (state->Vcc || state->Vpp)
846
out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
848
out_be32(M8XX_PGCRX(lsock),
849
in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
852
* We'd better turn off interrupts before
853
* we mess with the events-table..
856
spin_lock_irqsave(&events_lock, flags);
859
* Play around with the interrupt mask to be able to
860
* give the events the generic pcmcia driver wants us to.
866
if (state->csc_mask & SS_DETECT) {
867
e->eventbit = SS_DETECT;
868
reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
869
| M8XX_PCMCIA_CD1(lsock));
872
if (state->flags & SS_IOCARD) {
876
if (state->csc_mask & SS_STSCHG) {
877
e->eventbit = SS_STSCHG;
878
reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
882
* If io_irq is non-zero we should enable irq.
885
out_be32(M8XX_PGCRX(lsock),
886
in_be32(M8XX_PGCRX(lsock)) |
887
mk_int_int_mask(s->hwirq) << 24);
889
* Strange thing here:
890
* The manual does not tell us which interrupt
891
* the sources generate.
892
* Anyhow, I found out that RDY_L generates IREQLVL.
894
* We use level triggerd interrupts, and they don't
895
* have to be cleared in PSCR in the interrupt handler.
897
reg |= M8XX_PCMCIA_RDY_L(lsock);
899
out_be32(M8XX_PGCRX(lsock),
900
in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
905
if (state->csc_mask & SS_BATDEAD) {
906
e->eventbit = SS_BATDEAD;
907
reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
910
if (state->csc_mask & SS_BATWARN) {
911
e->eventbit = SS_BATWARN;
912
reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
915
/* What should I trigger on - low/high,raise,fall? */
916
if (state->csc_mask & SS_READY) {
917
e->eventbit = SS_READY;
918
reg |= e->regbit = 0; //??
923
e->regbit = 0; /* terminate list */
926
* Clear the status changed .
927
* Port A and Port B share the same port.
928
* Writing ones will clear the bits.
931
out_be32(&pcmcia->pcmc_pscr, reg);
935
* Port A and Port B share the same port.
936
* Need for read-modify-write.
937
* Ones will enable the interrupt.
942
pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
943
out_be32(&pcmcia->pcmc_per, reg);
945
spin_unlock_irqrestore(&events_lock, flags);
947
/* copy the struct and modify the copy */
954
static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
956
int lsock = container_of(sock, struct socket_info, socket)->slot;
958
struct socket_info *s = &socket[lsock];
959
struct pcmcia_win *w;
960
unsigned int reg, winnr;
961
pcmconf8xx_t *pcmcia = s->pcmcia;
963
#define M8XX_SIZE (io->stop - io->start + 1)
964
#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
966
pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, "
967
"%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags,
968
io->speed, (unsigned long long)io->start,
969
(unsigned long long)io->stop);
971
if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
972
|| (io->stop > 0xffff) || (io->stop < io->start))
975
if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
978
if (io->flags & MAP_ACTIVE) {
980
pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n");
982
winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
983
+ (lsock * PCMCIA_IO_WIN_NO) + io->map;
985
/* setup registers */
987
w = (void *)&pcmcia->pcmc_pbr0;
990
out_be32(&w->or, 0); /* turn off window first */
991
out_be32(&w->br, M8XX_BASE);
994
reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
996
reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
998
if (io->flags & MAP_WRPROT)
999
reg |= M8XX_PCMCIA_POR_WRPROT;
1001
/*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
1002
if (io->flags & MAP_16BIT)
1003
reg |= M8XX_PCMCIA_POR_16BIT;
1005
if (io->flags & MAP_ACTIVE)
1006
reg |= M8XX_PCMCIA_POR_VALID;
1008
out_be32(&w->or, reg);
1010
pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at "
1011
"%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1013
/* shutdown IO window */
1014
winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1015
+ (lsock * PCMCIA_IO_WIN_NO) + io->map;
1017
/* setup registers */
1019
w = (void *)&pcmcia->pcmc_pbr0;
1022
out_be32(&w->or, 0); /* turn off window */
1023
out_be32(&w->br, 0); /* turn off base address */
1025
pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at "
1026
"%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1029
/* copy the struct and modify the copy */
1030
s->io_win[io->map] = *io;
1031
s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1032
pr_debug("m8xx_pcmcia: SetIOMap exit\n");
1037
static int m8xx_set_mem_map(struct pcmcia_socket *sock,
1038
struct pccard_mem_map *mem)
1040
int lsock = container_of(sock, struct socket_info, socket)->slot;
1041
struct socket_info *s = &socket[lsock];
1042
struct pcmcia_win *w;
1043
struct pccard_mem_map *old;
1044
unsigned int reg, winnr;
1045
pcmconf8xx_t *pcmcia = s->pcmcia;
1047
pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1048
"%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1049
mem->speed, (unsigned long long)mem->static_start,
1052
if ((mem->map >= PCMCIA_MEM_WIN_NO)
1053
// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1054
|| (mem->card_start >= 0x04000000)
1055
|| (mem->static_start & 0xfff) /* 4KByte resolution */
1056
||(mem->card_start & 0xfff))
1059
if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1060
printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1065
winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1067
/* Setup the window in the pcmcia controller */
1069
w = (void *)&pcmcia->pcmc_pbr0;
1074
reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1076
if (mem->flags & MAP_ATTRIB)
1077
reg |= M8XX_PCMCIA_POR_ATTRMEM;
1079
if (mem->flags & MAP_WRPROT)
1080
reg |= M8XX_PCMCIA_POR_WRPROT;
1082
if (mem->flags & MAP_16BIT)
1083
reg |= M8XX_PCMCIA_POR_16BIT;
1085
if (mem->flags & MAP_ACTIVE)
1086
reg |= M8XX_PCMCIA_POR_VALID;
1088
out_be32(&w->or, reg);
1090
pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, "
1091
"OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1093
if (mem->flags & MAP_ACTIVE) {
1094
/* get the new base address */
1095
mem->static_start = PCMCIA_MEM_WIN_BASE +
1096
(PCMCIA_MEM_WIN_SIZE * winnr)
1100
pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1101
"%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1102
mem->speed, (unsigned long long)mem->static_start,
1105
/* copy the struct and modify the copy */
1107
old = &s->mem_win[mem->map];
1110
old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1115
static int m8xx_sock_init(struct pcmcia_socket *sock)
1118
pccard_io_map io = { 0, 0, 0, 0, 1 };
1119
pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1121
pr_debug("m8xx_pcmcia: sock_init(%d)\n", s);
1123
m8xx_set_socket(sock, &dead_socket);
1124
for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1126
m8xx_set_io_map(sock, &io);
1128
for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1130
m8xx_set_mem_map(sock, &mem);
1137
static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1139
return m8xx_set_socket(sock, &dead_socket);
1142
static struct pccard_operations m8xx_services = {
1143
.init = m8xx_sock_init,
1144
.suspend = m8xx_sock_suspend,
1145
.get_status = m8xx_get_status,
1146
.set_socket = m8xx_set_socket,
1147
.set_io_map = m8xx_set_io_map,
1148
.set_mem_map = m8xx_set_mem_map,
1151
static int __init m8xx_probe(struct platform_device *ofdev)
1153
struct pcmcia_win *w;
1154
unsigned int i, m, hwirq;
1155
pcmconf8xx_t *pcmcia;
1157
struct device_node *np = ofdev->dev.of_node;
1159
pcmcia_info("%s\n", version);
1161
pcmcia = of_iomap(np, 0);
1165
pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1166
hwirq = irq_map[pcmcia_schlvl].hwirq;
1167
if (pcmcia_schlvl < 0) {
1172
m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1173
m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1175
pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1176
" with IRQ %u (%d). \n", pcmcia_schlvl, hwirq);
1178
/* Configure Status change interrupt */
1180
if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1181
driver_name, socket)) {
1182
pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1188
w = (void *)&pcmcia->pcmc_pbr0;
1190
out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1191
clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1193
/* connect interrupt and disable CxOE */
1195
out_be32(M8XX_PGCRX(0),
1196
M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1197
out_be32(M8XX_PGCRX(1),
1198
M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1200
/* initialize the fixed memory windows */
1202
for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1203
for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1204
out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1205
(PCMCIA_MEM_WIN_SIZE
1206
* (m + i * PCMCIA_MEM_WIN_NO)));
1208
out_be32(&w->or, 0); /* set to not valid */
1214
/* turn off voltage */
1215
voltage_set(0, 0, 0);
1216
voltage_set(1, 0, 0);
1218
/* Enable external hardware */
1222
for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1224
socket[i].socket.owner = THIS_MODULE;
1225
socket[i].socket.features =
1226
SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1227
socket[i].socket.irq_mask = 0x000;
1228
socket[i].socket.map_size = 0x1000;
1229
socket[i].socket.io_offset = 0;
1230
socket[i].socket.pci_irq = pcmcia_schlvl;
1231
socket[i].socket.ops = &m8xx_services;
1232
socket[i].socket.resource_ops = &pccard_iodyn_ops;
1233
socket[i].socket.cb_dev = NULL;
1234
socket[i].socket.dev.parent = &ofdev->dev;
1235
socket[i].pcmcia = pcmcia;
1236
socket[i].bus_freq = ppc_proc_freq;
1237
socket[i].hwirq = hwirq;
1241
for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1242
status = pcmcia_register_socket(&socket[i].socket);
1244
pcmcia_error("Socket register failed\n");
1250
static int m8xx_remove(struct platform_device *ofdev)
1253
struct pcmcia_win *w;
1254
pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1256
for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1257
w = (void *)&pcmcia->pcmc_pbr0;
1259
out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1260
out_be32(&pcmcia->pcmc_per,
1261
in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1263
/* turn off interrupt and disable CxOE */
1264
out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1266
/* turn off memory windows */
1267
for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1268
out_be32(&w->or, 0); /* set to not valid */
1272
/* turn off voltage */
1273
voltage_set(i, 0, 0);
1275
/* disable external hardware */
1276
hardware_disable(i);
1278
for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1279
pcmcia_unregister_socket(&socket[i].socket);
1282
free_irq(pcmcia_schlvl, NULL);
1287
static const struct of_device_id m8xx_pcmcia_match[] = {
1290
.compatible = "fsl,pq-pcmcia",
1295
MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1297
static struct platform_driver m8xx_pcmcia_driver = {
1299
.name = driver_name,
1300
.owner = THIS_MODULE,
1301
.of_match_table = m8xx_pcmcia_match,
1303
.probe = m8xx_probe,
1304
.remove = m8xx_remove,
1307
static int __init m8xx_init(void)
1309
return platform_driver_register(&m8xx_pcmcia_driver);
1312
static void __exit m8xx_exit(void)
1314
platform_driver_unregister(&m8xx_pcmcia_driver);
1317
module_init(m8xx_init);
1318
module_exit(m8xx_exit);