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* linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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* Thanks to the following companies for their support:
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* - JMicron (hardware and technical support)
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/scatterlist.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/leds.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/host.h>
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#define DRIVER_NAME "sdhci"
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#define DBG(f, x...) \
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pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
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#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
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defined(CONFIG_MMC_SDHCI_MODULE))
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#define SDHCI_USE_LEDS_CLASS
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#define MAX_TUNING_LOOP 40
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static unsigned int debug_quirks = 0;
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static unsigned int debug_quirks2;
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static void sdhci_finish_data(struct sdhci_host *);
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static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
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static void sdhci_finish_command(struct sdhci_host *);
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static int sdhci_execute_tuning(struct mmc_host *mmc);
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static void sdhci_tuning_timer(unsigned long data);
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#ifdef CONFIG_PM_RUNTIME
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static int sdhci_runtime_pm_get(struct sdhci_host *host);
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static int sdhci_runtime_pm_put(struct sdhci_host *host);
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static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
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static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
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static void sdhci_dumpregs(struct sdhci_host *host)
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pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
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mmc_hostname(host->mmc));
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pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
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sdhci_readl(host, SDHCI_DMA_ADDRESS),
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sdhci_readw(host, SDHCI_HOST_VERSION));
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pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
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sdhci_readw(host, SDHCI_BLOCK_SIZE),
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sdhci_readw(host, SDHCI_BLOCK_COUNT));
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pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
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sdhci_readl(host, SDHCI_ARGUMENT),
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sdhci_readw(host, SDHCI_TRANSFER_MODE));
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pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
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sdhci_readl(host, SDHCI_PRESENT_STATE),
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sdhci_readb(host, SDHCI_HOST_CONTROL));
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pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
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sdhci_readb(host, SDHCI_POWER_CONTROL),
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sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
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pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
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sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
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sdhci_readw(host, SDHCI_CLOCK_CONTROL));
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pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
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sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
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sdhci_readl(host, SDHCI_INT_STATUS));
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pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
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sdhci_readl(host, SDHCI_INT_ENABLE),
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sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
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pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
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sdhci_readw(host, SDHCI_ACMD12_ERR),
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sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
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pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
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sdhci_readl(host, SDHCI_CAPABILITIES),
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sdhci_readl(host, SDHCI_CAPABILITIES_1));
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pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
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sdhci_readw(host, SDHCI_COMMAND),
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sdhci_readl(host, SDHCI_MAX_CURRENT));
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pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
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sdhci_readw(host, SDHCI_HOST_CONTROL2));
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if (host->flags & SDHCI_USE_ADMA)
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pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
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readl(host->ioaddr + SDHCI_ADMA_ERROR),
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readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
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pr_debug(DRIVER_NAME ": ===========================================\n");
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/*****************************************************************************\
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* Low level functions *
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\*****************************************************************************/
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static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
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ier = sdhci_readl(host, SDHCI_INT_ENABLE);
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sdhci_writel(host, ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
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static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
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sdhci_clear_set_irqs(host, 0, irqs);
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static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
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sdhci_clear_set_irqs(host, irqs, 0);
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static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
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if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
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if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
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present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
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irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
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sdhci_unmask_irqs(host, irqs);
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sdhci_mask_irqs(host, irqs);
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static void sdhci_enable_card_detection(struct sdhci_host *host)
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sdhci_set_card_detection(host, true);
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static void sdhci_disable_card_detection(struct sdhci_host *host)
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sdhci_set_card_detection(host, false);
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static void sdhci_reset(struct sdhci_host *host, u8 mask)
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unsigned long timeout;
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u32 uninitialized_var(ier);
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if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
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if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
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if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
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ier = sdhci_readl(host, SDHCI_INT_ENABLE);
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if (host->ops->platform_reset_enter)
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host->ops->platform_reset_enter(host, mask);
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sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
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if (mask & SDHCI_RESET_ALL)
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/* Wait max 100 ms */
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/* hw clears the bit when it's done */
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while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
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pr_err("%s: Reset 0x%x never completed.\n",
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mmc_hostname(host->mmc), (int)mask);
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sdhci_dumpregs(host);
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if (host->ops->platform_reset_exit)
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host->ops->platform_reset_exit(host, mask);
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if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
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sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
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static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
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static void sdhci_init(struct sdhci_host *host, int soft)
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sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
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sdhci_reset(host, SDHCI_RESET_ALL);
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sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
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SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
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SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
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SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
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SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
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/* force clock reconfiguration */
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sdhci_set_ios(host->mmc, &host->mmc->ios);
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static void sdhci_reinit(struct sdhci_host *host)
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sdhci_enable_card_detection(host);
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static void sdhci_activate_led(struct sdhci_host *host)
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl |= SDHCI_CTRL_LED;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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static void sdhci_deactivate_led(struct sdhci_host *host)
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl &= ~SDHCI_CTRL_LED;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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#ifdef SDHCI_USE_LEDS_CLASS
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static void sdhci_led_control(struct led_classdev *led,
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enum led_brightness brightness)
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struct sdhci_host *host = container_of(led, struct sdhci_host, led);
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spin_lock_irqsave(&host->lock, flags);
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if (host->runtime_suspended)
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if (brightness == LED_OFF)
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sdhci_deactivate_led(host);
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sdhci_activate_led(host);
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spin_unlock_irqrestore(&host->lock, flags);
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/*****************************************************************************\
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\*****************************************************************************/
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static void sdhci_read_block_pio(struct sdhci_host *host)
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size_t blksize, len, chunk;
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u32 uninitialized_var(scratch);
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DBG("PIO reading\n");
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blksize = host->data->blksz;
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local_irq_save(flags);
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if (!sg_miter_next(&host->sg_miter))
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len = min(host->sg_miter.length, blksize);
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host->sg_miter.consumed = len;
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buf = host->sg_miter.addr;
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scratch = sdhci_readl(host, SDHCI_BUFFER);
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*buf = scratch & 0xFF;
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sg_miter_stop(&host->sg_miter);
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local_irq_restore(flags);
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static void sdhci_write_block_pio(struct sdhci_host *host)
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size_t blksize, len, chunk;
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DBG("PIO writing\n");
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blksize = host->data->blksz;
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local_irq_save(flags);
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if (!sg_miter_next(&host->sg_miter))
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len = min(host->sg_miter.length, blksize);
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host->sg_miter.consumed = len;
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buf = host->sg_miter.addr;
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scratch |= (u32)*buf << (chunk * 8);
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if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
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sdhci_writel(host, scratch, SDHCI_BUFFER);
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sg_miter_stop(&host->sg_miter);
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local_irq_restore(flags);
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static void sdhci_transfer_pio(struct sdhci_host *host)
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if (host->blocks == 0)
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if (host->data->flags & MMC_DATA_READ)
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mask = SDHCI_DATA_AVAILABLE;
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mask = SDHCI_SPACE_AVAILABLE;
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* Some controllers (JMicron JMB38x) mess up the buffer bits
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* for transfers < 4 bytes. As long as it is just one block,
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* we can ignore the bits.
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if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
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(host->data->blocks == 1))
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while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
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if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
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if (host->data->flags & MMC_DATA_READ)
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sdhci_read_block_pio(host);
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sdhci_write_block_pio(host);
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if (host->blocks == 0)
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DBG("PIO transfer complete.\n");
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static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
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local_irq_save(*flags);
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return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
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static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
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kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
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local_irq_restore(*flags);
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static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
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__le32 *dataddr = (__le32 __force *)(desc + 4);
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__le16 *cmdlen = (__le16 __force *)desc;
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/* SDHCI specification says ADMA descriptors should be 4 byte
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* aligned, so using 16 or 32bit operations should be safe. */
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cmdlen[0] = cpu_to_le16(cmd);
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cmdlen[1] = cpu_to_le16(len);
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dataddr[0] = cpu_to_le32(addr);
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static int sdhci_adma_table_pre(struct sdhci_host *host,
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struct mmc_data *data)
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dma_addr_t align_addr;
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struct scatterlist *sg;
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* The spec does not specify endianness of descriptor table.
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* We currently guess that it is LE.
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if (data->flags & MMC_DATA_READ)
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direction = DMA_FROM_DEVICE;
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direction = DMA_TO_DEVICE;
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* The ADMA descriptor table is mapped further down as we
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* need to fill it with data first.
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host->align_addr = dma_map_single(mmc_dev(host->mmc),
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host->align_buffer, 128 * 4, direction);
482
if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
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BUG_ON(host->align_addr & 0x3);
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host->sg_count = dma_map_sg(mmc_dev(host->mmc),
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data->sg, data->sg_len, direction);
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if (host->sg_count == 0)
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desc = host->adma_desc;
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align = host->align_buffer;
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align_addr = host->align_addr;
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for_each_sg(data->sg, sg, host->sg_count, i) {
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addr = sg_dma_address(sg);
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len = sg_dma_len(sg);
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* The SDHCI specification states that ADMA
502
* addresses must be 32-bit aligned. If they
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* aren't, then we use a bounce buffer for
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* the (up to three) bytes that screw up the
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offset = (4 - (addr & 0x3)) & 0x3;
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if (data->flags & MMC_DATA_WRITE) {
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buffer = sdhci_kmap_atomic(sg, &flags);
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WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
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memcpy(align, buffer, offset);
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sdhci_kunmap_atomic(buffer, &flags);
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sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
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BUG_ON(offset > 65536);
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sdhci_set_adma_desc(desc, addr, len, 0x21);
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* If this triggers then we have a calculation bug
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WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
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if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
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* Mark the last descriptor as the terminating descriptor
547
if (desc != host->adma_desc) {
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desc[0] |= 0x2; /* end */
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* Add a terminating entry.
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/* nop, end, valid */
557
sdhci_set_adma_desc(desc, 0, 0, 0x3);
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* Resync align buffer as we might have changed it.
563
if (data->flags & MMC_DATA_WRITE) {
564
dma_sync_single_for_device(mmc_dev(host->mmc),
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host->align_addr, 128 * 4, direction);
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host->adma_addr = dma_map_single(mmc_dev(host->mmc),
569
host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
570
if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
572
BUG_ON(host->adma_addr & 0x3);
577
dma_unmap_sg(mmc_dev(host->mmc), data->sg,
578
data->sg_len, direction);
580
dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
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static void sdhci_adma_table_post(struct sdhci_host *host,
587
struct mmc_data *data)
591
struct scatterlist *sg;
597
if (data->flags & MMC_DATA_READ)
598
direction = DMA_FROM_DEVICE;
600
direction = DMA_TO_DEVICE;
602
dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
603
(128 * 2 + 1) * 4, DMA_TO_DEVICE);
605
dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
608
if (data->flags & MMC_DATA_READ) {
609
dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
610
data->sg_len, direction);
612
align = host->align_buffer;
614
for_each_sg(data->sg, sg, host->sg_count, i) {
615
if (sg_dma_address(sg) & 0x3) {
616
size = 4 - (sg_dma_address(sg) & 0x3);
618
buffer = sdhci_kmap_atomic(sg, &flags);
619
WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
620
memcpy(buffer, align, size);
621
sdhci_kunmap_atomic(buffer, &flags);
628
dma_unmap_sg(mmc_dev(host->mmc), data->sg,
629
data->sg_len, direction);
632
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
635
struct mmc_data *data = cmd->data;
636
unsigned target_timeout, current_timeout;
639
* If the host controller provides us with an incorrect timeout
640
* value, just skip the check and use 0xE. The hardware may take
641
* longer to time out, but that's much better than having a too-short
644
if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
647
/* Unspecified timeout, assume max */
648
if (!data && !cmd->cmd_timeout_ms)
653
target_timeout = cmd->cmd_timeout_ms * 1000;
655
target_timeout = data->timeout_ns / 1000;
657
target_timeout += data->timeout_clks / host->clock;
661
* Figure out needed cycles.
662
* We do this in steps in order to fit inside a 32 bit int.
663
* The first step is the minimum timeout, which will have a
664
* minimum resolution of 6 bits:
665
* (1) 2^13*1000 > 2^22,
666
* (2) host->timeout_clk < 2^16
671
current_timeout = (1 << 13) * 1000 / host->timeout_clk;
672
while (current_timeout < target_timeout) {
674
current_timeout <<= 1;
680
pr_warning("%s: Too large timeout requested for CMD%d!\n",
681
mmc_hostname(host->mmc), cmd->opcode);
688
static void sdhci_set_transfer_irqs(struct sdhci_host *host)
690
u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
691
u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
693
if (host->flags & SDHCI_REQ_USE_DMA)
694
sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
696
sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
699
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
703
struct mmc_data *data = cmd->data;
708
if (data || (cmd->flags & MMC_RSP_BUSY)) {
709
count = sdhci_calc_timeout(host, cmd);
710
sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
717
BUG_ON(data->blksz * data->blocks > 524288);
718
BUG_ON(data->blksz > host->mmc->max_blk_size);
719
BUG_ON(data->blocks > 65535);
722
host->data_early = 0;
723
host->data->bytes_xfered = 0;
725
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
726
host->flags |= SDHCI_REQ_USE_DMA;
729
* FIXME: This doesn't account for merging when mapping the
732
if (host->flags & SDHCI_REQ_USE_DMA) {
734
struct scatterlist *sg;
737
if (host->flags & SDHCI_USE_ADMA) {
738
if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
741
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
745
if (unlikely(broken)) {
746
for_each_sg(data->sg, sg, data->sg_len, i) {
747
if (sg->length & 0x3) {
748
DBG("Reverting to PIO because of "
749
"transfer size (%d)\n",
751
host->flags &= ~SDHCI_REQ_USE_DMA;
759
* The assumption here being that alignment is the same after
760
* translation to device address space.
762
if (host->flags & SDHCI_REQ_USE_DMA) {
764
struct scatterlist *sg;
767
if (host->flags & SDHCI_USE_ADMA) {
769
* As we use 3 byte chunks to work around
770
* alignment problems, we need to check this
773
if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
776
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
780
if (unlikely(broken)) {
781
for_each_sg(data->sg, sg, data->sg_len, i) {
782
if (sg->offset & 0x3) {
783
DBG("Reverting to PIO because of "
785
host->flags &= ~SDHCI_REQ_USE_DMA;
792
if (host->flags & SDHCI_REQ_USE_DMA) {
793
if (host->flags & SDHCI_USE_ADMA) {
794
ret = sdhci_adma_table_pre(host, data);
797
* This only happens when someone fed
798
* us an invalid request.
801
host->flags &= ~SDHCI_REQ_USE_DMA;
803
sdhci_writel(host, host->adma_addr,
809
sg_cnt = dma_map_sg(mmc_dev(host->mmc),
810
data->sg, data->sg_len,
811
(data->flags & MMC_DATA_READ) ?
816
* This only happens when someone fed
817
* us an invalid request.
820
host->flags &= ~SDHCI_REQ_USE_DMA;
822
WARN_ON(sg_cnt != 1);
823
sdhci_writel(host, sg_dma_address(data->sg),
830
* Always adjust the DMA selection as some controllers
831
* (e.g. JMicron) can't do PIO properly when the selection
834
if (host->version >= SDHCI_SPEC_200) {
835
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
836
ctrl &= ~SDHCI_CTRL_DMA_MASK;
837
if ((host->flags & SDHCI_REQ_USE_DMA) &&
838
(host->flags & SDHCI_USE_ADMA))
839
ctrl |= SDHCI_CTRL_ADMA32;
841
ctrl |= SDHCI_CTRL_SDMA;
842
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
845
if (!(host->flags & SDHCI_REQ_USE_DMA)) {
848
flags = SG_MITER_ATOMIC;
849
if (host->data->flags & MMC_DATA_READ)
850
flags |= SG_MITER_TO_SG;
852
flags |= SG_MITER_FROM_SG;
853
sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
854
host->blocks = data->blocks;
857
sdhci_set_transfer_irqs(host);
859
/* Set the DMA boundary value and block size */
860
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
861
data->blksz), SDHCI_BLOCK_SIZE);
862
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
865
static void sdhci_set_transfer_mode(struct sdhci_host *host,
866
struct mmc_command *cmd)
869
struct mmc_data *data = cmd->data;
874
WARN_ON(!host->data);
876
mode = SDHCI_TRNS_BLK_CNT_EN;
877
if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
878
mode |= SDHCI_TRNS_MULTI;
880
* If we are sending CMD23, CMD12 never gets sent
881
* on successful completion (so no Auto-CMD12).
883
if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
884
mode |= SDHCI_TRNS_AUTO_CMD12;
885
else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
886
mode |= SDHCI_TRNS_AUTO_CMD23;
887
sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
891
if (data->flags & MMC_DATA_READ)
892
mode |= SDHCI_TRNS_READ;
893
if (host->flags & SDHCI_REQ_USE_DMA)
894
mode |= SDHCI_TRNS_DMA;
896
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
899
static void sdhci_finish_data(struct sdhci_host *host)
901
struct mmc_data *data;
908
if (host->flags & SDHCI_REQ_USE_DMA) {
909
if (host->flags & SDHCI_USE_ADMA)
910
sdhci_adma_table_post(host, data);
912
dma_unmap_sg(mmc_dev(host->mmc), data->sg,
913
data->sg_len, (data->flags & MMC_DATA_READ) ?
914
DMA_FROM_DEVICE : DMA_TO_DEVICE);
919
* The specification states that the block count register must
920
* be updated, but it does not specify at what point in the
921
* data flow. That makes the register entirely useless to read
922
* back so we have to assume that nothing made it to the card
923
* in the event of an error.
926
data->bytes_xfered = 0;
928
data->bytes_xfered = data->blksz * data->blocks;
931
* Need to send CMD12 if -
932
* a) open-ended multiblock transfer (no CMD23)
933
* b) error in multiblock transfer
940
* The controller needs a reset of internal state machines
941
* upon error conditions.
944
sdhci_reset(host, SDHCI_RESET_CMD);
945
sdhci_reset(host, SDHCI_RESET_DATA);
948
sdhci_send_command(host, data->stop);
950
tasklet_schedule(&host->finish_tasklet);
953
static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
957
unsigned long timeout;
964
mask = SDHCI_CMD_INHIBIT;
965
if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
966
mask |= SDHCI_DATA_INHIBIT;
968
/* We shouldn't wait for data inihibit for stop commands, even
969
though they might use busy signaling */
970
if (host->mrq->data && (cmd == host->mrq->data->stop))
971
mask &= ~SDHCI_DATA_INHIBIT;
973
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
975
pr_err("%s: Controller never released "
976
"inhibit bit(s).\n", mmc_hostname(host->mmc));
977
sdhci_dumpregs(host);
979
tasklet_schedule(&host->finish_tasklet);
986
mod_timer(&host->timer, jiffies + 10 * HZ);
990
sdhci_prepare_data(host, cmd);
992
sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
994
sdhci_set_transfer_mode(host, cmd);
996
if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
997
pr_err("%s: Unsupported response type!\n",
998
mmc_hostname(host->mmc));
999
cmd->error = -EINVAL;
1000
tasklet_schedule(&host->finish_tasklet);
1004
if (!(cmd->flags & MMC_RSP_PRESENT))
1005
flags = SDHCI_CMD_RESP_NONE;
1006
else if (cmd->flags & MMC_RSP_136)
1007
flags = SDHCI_CMD_RESP_LONG;
1008
else if (cmd->flags & MMC_RSP_BUSY)
1009
flags = SDHCI_CMD_RESP_SHORT_BUSY;
1011
flags = SDHCI_CMD_RESP_SHORT;
1013
if (cmd->flags & MMC_RSP_CRC)
1014
flags |= SDHCI_CMD_CRC;
1015
if (cmd->flags & MMC_RSP_OPCODE)
1016
flags |= SDHCI_CMD_INDEX;
1018
/* CMD19 is special in that the Data Present Select should be set */
1019
if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
1020
flags |= SDHCI_CMD_DATA;
1022
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1025
static void sdhci_finish_command(struct sdhci_host *host)
1029
BUG_ON(host->cmd == NULL);
1031
if (host->cmd->flags & MMC_RSP_PRESENT) {
1032
if (host->cmd->flags & MMC_RSP_136) {
1033
/* CRC is stripped so we need to do some shifting. */
1034
for (i = 0;i < 4;i++) {
1035
host->cmd->resp[i] = sdhci_readl(host,
1036
SDHCI_RESPONSE + (3-i)*4) << 8;
1038
host->cmd->resp[i] |=
1040
SDHCI_RESPONSE + (3-i)*4-1);
1043
host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1047
host->cmd->error = 0;
1049
/* Finished CMD23, now send actual command. */
1050
if (host->cmd == host->mrq->sbc) {
1052
sdhci_send_command(host, host->mrq->cmd);
1055
/* Processed actual command. */
1056
if (host->data && host->data_early)
1057
sdhci_finish_data(host);
1059
if (!host->cmd->data)
1060
tasklet_schedule(&host->finish_tasklet);
1066
static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1068
int div = 0; /* Initialized for compiler warning */
1070
unsigned long timeout;
1072
if (clock == host->clock)
1075
if (host->ops->set_clock) {
1076
host->ops->set_clock(host, clock);
1077
if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1081
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1086
if (host->version >= SDHCI_SPEC_300) {
1088
* Check if the Host Controller supports Programmable Clock
1091
if (host->clk_mul) {
1095
* We need to figure out whether the Host Driver needs
1096
* to select Programmable Clock Mode, or the value can
1097
* be set automatically by the Host Controller based on
1098
* the Preset Value registers.
1100
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1101
if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1102
for (div = 1; div <= 1024; div++) {
1103
if (((host->max_clk * host->clk_mul) /
1108
* Set Programmable Clock Mode in the Clock
1111
clk = SDHCI_PROG_CLOCK_MODE;
1115
/* Version 3.00 divisors must be a multiple of 2. */
1116
if (host->max_clk <= clock)
1119
for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1121
if ((host->max_clk / div) <= clock)
1128
/* Version 2.00 divisors must be a power of 2. */
1129
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1130
if ((host->max_clk / div) <= clock)
1136
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1137
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1138
<< SDHCI_DIVIDER_HI_SHIFT;
1139
clk |= SDHCI_CLOCK_INT_EN;
1140
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1142
/* Wait max 20 ms */
1144
while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1145
& SDHCI_CLOCK_INT_STABLE)) {
1147
pr_err("%s: Internal clock never "
1148
"stabilised.\n", mmc_hostname(host->mmc));
1149
sdhci_dumpregs(host);
1156
clk |= SDHCI_CLOCK_CARD_EN;
1157
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1160
host->clock = clock;
1163
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1167
if (power != (unsigned short)-1) {
1168
switch (1 << power) {
1169
case MMC_VDD_165_195:
1170
pwr = SDHCI_POWER_180;
1174
pwr = SDHCI_POWER_300;
1178
pwr = SDHCI_POWER_330;
1185
if (host->pwr == pwr)
1191
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1196
* Spec says that we should clear the power reg before setting
1197
* a new value. Some controllers don't seem to like this though.
1199
if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1200
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1203
* At least the Marvell CaFe chip gets confused if we set the voltage
1204
* and set turn on power at the same time, so set the voltage first.
1206
if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1207
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1209
pwr |= SDHCI_POWER_ON;
1211
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1214
* Some controllers need an extra 10ms delay of 10ms before they
1215
* can apply clock after applying power
1217
if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1221
/*****************************************************************************\
1225
\*****************************************************************************/
1227
static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1229
struct sdhci_host *host;
1231
unsigned long flags;
1233
host = mmc_priv(mmc);
1235
sdhci_runtime_pm_get(host);
1237
spin_lock_irqsave(&host->lock, flags);
1239
WARN_ON(host->mrq != NULL);
1241
#ifndef SDHCI_USE_LEDS_CLASS
1242
sdhci_activate_led(host);
1246
* Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1247
* requests if Auto-CMD12 is enabled.
1249
if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1251
mrq->data->stop = NULL;
1258
/* If polling, assume that the card is always present. */
1259
if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1262
present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1265
if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1266
host->mrq->cmd->error = -ENOMEDIUM;
1267
tasklet_schedule(&host->finish_tasklet);
1271
present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1273
* Check if the re-tuning timer has already expired and there
1274
* is no on-going data transfer. If so, we need to execute
1275
* tuning procedure before sending command.
1277
if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1278
!(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1279
spin_unlock_irqrestore(&host->lock, flags);
1280
sdhci_execute_tuning(mmc);
1281
spin_lock_irqsave(&host->lock, flags);
1283
/* Restore original mmc_request structure */
1287
if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1288
sdhci_send_command(host, mrq->sbc);
1290
sdhci_send_command(host, mrq->cmd);
1294
spin_unlock_irqrestore(&host->lock, flags);
1297
static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1299
unsigned long flags;
1302
spin_lock_irqsave(&host->lock, flags);
1304
if (host->flags & SDHCI_DEVICE_DEAD)
1308
* Reset the chip on each power off.
1309
* Should clear out any weird states.
1311
if (ios->power_mode == MMC_POWER_OFF) {
1312
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1316
sdhci_set_clock(host, ios->clock);
1318
if (ios->power_mode == MMC_POWER_OFF)
1319
sdhci_set_power(host, -1);
1321
sdhci_set_power(host, ios->vdd);
1323
if (host->ops->platform_send_init_74_clocks)
1324
host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1327
* If your platform has 8-bit width support but is not a v3 controller,
1328
* or if it requires special setup code, you should implement that in
1329
* platform_8bit_width().
1331
if (host->ops->platform_8bit_width)
1332
host->ops->platform_8bit_width(host, ios->bus_width);
1334
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1335
if (ios->bus_width == MMC_BUS_WIDTH_8) {
1336
ctrl &= ~SDHCI_CTRL_4BITBUS;
1337
if (host->version >= SDHCI_SPEC_300)
1338
ctrl |= SDHCI_CTRL_8BITBUS;
1340
if (host->version >= SDHCI_SPEC_300)
1341
ctrl &= ~SDHCI_CTRL_8BITBUS;
1342
if (ios->bus_width == MMC_BUS_WIDTH_4)
1343
ctrl |= SDHCI_CTRL_4BITBUS;
1345
ctrl &= ~SDHCI_CTRL_4BITBUS;
1347
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1350
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1352
if ((ios->timing == MMC_TIMING_SD_HS ||
1353
ios->timing == MMC_TIMING_MMC_HS)
1354
&& !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1355
ctrl |= SDHCI_CTRL_HISPD;
1357
ctrl &= ~SDHCI_CTRL_HISPD;
1359
if (host->version >= SDHCI_SPEC_300) {
1363
/* In case of UHS-I modes, set High Speed Enable */
1364
if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1365
(ios->timing == MMC_TIMING_UHS_SDR104) ||
1366
(ios->timing == MMC_TIMING_UHS_DDR50) ||
1367
(ios->timing == MMC_TIMING_UHS_SDR25) ||
1368
(ios->timing == MMC_TIMING_UHS_SDR12))
1369
ctrl |= SDHCI_CTRL_HISPD;
1371
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1372
if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1373
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1375
* We only need to set Driver Strength if the
1376
* preset value enable is not set.
1378
ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1379
if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1380
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1381
else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1382
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1384
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1387
* According to SDHC Spec v3.00, if the Preset Value
1388
* Enable in the Host Control 2 register is set, we
1389
* need to reset SD Clock Enable before changing High
1390
* Speed Enable to avoid generating clock gliches.
1393
/* Reset SD Clock Enable */
1394
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1395
clk &= ~SDHCI_CLOCK_CARD_EN;
1396
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1398
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1400
/* Re-enable SD Clock */
1401
clock = host->clock;
1403
sdhci_set_clock(host, clock);
1407
/* Reset SD Clock Enable */
1408
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1409
clk &= ~SDHCI_CLOCK_CARD_EN;
1410
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1412
if (host->ops->set_uhs_signaling)
1413
host->ops->set_uhs_signaling(host, ios->timing);
1415
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1416
/* Select Bus Speed Mode for host */
1417
ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1418
if (ios->timing == MMC_TIMING_UHS_SDR12)
1419
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1420
else if (ios->timing == MMC_TIMING_UHS_SDR25)
1421
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1422
else if (ios->timing == MMC_TIMING_UHS_SDR50)
1423
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1424
else if (ios->timing == MMC_TIMING_UHS_SDR104)
1425
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1426
else if (ios->timing == MMC_TIMING_UHS_DDR50)
1427
ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1428
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1431
/* Re-enable SD Clock */
1432
clock = host->clock;
1434
sdhci_set_clock(host, clock);
1436
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1439
* Some (ENE) controllers go apeshit on some ios operation,
1440
* signalling timeout and CRC errors even on CMD0. Resetting
1441
* it on each ios seems to solve the problem.
1443
if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1444
sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1448
spin_unlock_irqrestore(&host->lock, flags);
1451
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1453
struct sdhci_host *host = mmc_priv(mmc);
1455
sdhci_runtime_pm_get(host);
1456
sdhci_do_set_ios(host, ios);
1457
sdhci_runtime_pm_put(host);
1460
static int sdhci_check_ro(struct sdhci_host *host)
1462
unsigned long flags;
1465
spin_lock_irqsave(&host->lock, flags);
1467
if (host->flags & SDHCI_DEVICE_DEAD)
1469
else if (host->ops->get_ro)
1470
is_readonly = host->ops->get_ro(host);
1472
is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1473
& SDHCI_WRITE_PROTECT);
1475
spin_unlock_irqrestore(&host->lock, flags);
1477
/* This quirk needs to be replaced by a callback-function later */
1478
return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1479
!is_readonly : is_readonly;
1482
#define SAMPLE_COUNT 5
1484
static int sdhci_do_get_ro(struct sdhci_host *host)
1488
if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1489
return sdhci_check_ro(host);
1492
for (i = 0; i < SAMPLE_COUNT; i++) {
1493
if (sdhci_check_ro(host)) {
1494
if (++ro_count > SAMPLE_COUNT / 2)
1502
static void sdhci_hw_reset(struct mmc_host *mmc)
1504
struct sdhci_host *host = mmc_priv(mmc);
1506
if (host->ops && host->ops->hw_reset)
1507
host->ops->hw_reset(host);
1510
static int sdhci_get_ro(struct mmc_host *mmc)
1512
struct sdhci_host *host = mmc_priv(mmc);
1515
sdhci_runtime_pm_get(host);
1516
ret = sdhci_do_get_ro(host);
1517
sdhci_runtime_pm_put(host);
1521
static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1523
if (host->flags & SDHCI_DEVICE_DEAD)
1527
host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1529
host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1531
/* SDIO IRQ will be enabled as appropriate in runtime resume */
1532
if (host->runtime_suspended)
1536
sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1538
sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1543
static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1545
struct sdhci_host *host = mmc_priv(mmc);
1546
unsigned long flags;
1548
spin_lock_irqsave(&host->lock, flags);
1549
sdhci_enable_sdio_irq_nolock(host, enable);
1550
spin_unlock_irqrestore(&host->lock, flags);
1553
static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1554
struct mmc_ios *ios)
1561
* Signal Voltage Switching is only applicable for Host Controllers
1564
if (host->version < SDHCI_SPEC_300)
1568
* We first check whether the request is to set signalling voltage
1569
* to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1571
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1572
if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1573
/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1574
ctrl &= ~SDHCI_CTRL_VDD_180;
1575
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1578
usleep_range(5000, 5500);
1580
/* 3.3V regulator output should be stable within 5 ms */
1581
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1582
if (!(ctrl & SDHCI_CTRL_VDD_180))
1585
pr_info(DRIVER_NAME ": Switching to 3.3V "
1586
"signalling voltage failed\n");
1589
} else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1590
(ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1592
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1593
clk &= ~SDHCI_CLOCK_CARD_EN;
1594
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1596
/* Check whether DAT[3:0] is 0000 */
1597
present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1598
if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1599
SDHCI_DATA_LVL_SHIFT)) {
1601
* Enable 1.8V Signal Enable in the Host Control2
1604
ctrl |= SDHCI_CTRL_VDD_180;
1605
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1608
usleep_range(5000, 5500);
1610
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1611
if (ctrl & SDHCI_CTRL_VDD_180) {
1612
/* Provide SDCLK again and wait for 1ms*/
1613
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1614
clk |= SDHCI_CLOCK_CARD_EN;
1615
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1616
usleep_range(1000, 1500);
1619
* If DAT[3:0] level is 1111b, then the card
1620
* was successfully switched to 1.8V signaling.
1622
present_state = sdhci_readl(host,
1623
SDHCI_PRESENT_STATE);
1624
if ((present_state & SDHCI_DATA_LVL_MASK) ==
1625
SDHCI_DATA_LVL_MASK)
1631
* If we are here, that means the switch to 1.8V signaling
1632
* failed. We power cycle the card, and retry initialization
1633
* sequence by setting S18R to 0.
1635
pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1636
pwr &= ~SDHCI_POWER_ON;
1637
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1639
/* Wait for 1ms as per the spec */
1640
usleep_range(1000, 1500);
1641
pwr |= SDHCI_POWER_ON;
1642
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1644
pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1645
"voltage failed, retrying with S18R set to 0\n");
1648
/* No signal voltage switch required */
1652
static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1653
struct mmc_ios *ios)
1655
struct sdhci_host *host = mmc_priv(mmc);
1658
if (host->version < SDHCI_SPEC_300)
1660
sdhci_runtime_pm_get(host);
1661
err = sdhci_do_start_signal_voltage_switch(host, ios);
1662
sdhci_runtime_pm_put(host);
1666
static int sdhci_execute_tuning(struct mmc_host *mmc)
1668
struct sdhci_host *host;
1671
int tuning_loop_counter = MAX_TUNING_LOOP;
1672
unsigned long timeout;
1675
host = mmc_priv(mmc);
1677
sdhci_runtime_pm_get(host);
1678
disable_irq(host->irq);
1679
spin_lock(&host->lock);
1681
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1684
* Host Controller needs tuning only in case of SDR104 mode
1685
* and for SDR50 mode when Use Tuning for SDR50 is set in
1686
* Capabilities register.
1688
if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1689
(((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1690
(host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1691
ctrl |= SDHCI_CTRL_EXEC_TUNING;
1693
spin_unlock(&host->lock);
1694
enable_irq(host->irq);
1695
sdhci_runtime_pm_put(host);
1699
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1702
* As per the Host Controller spec v3.00, tuning command
1703
* generates Buffer Read Ready interrupt, so enable that.
1705
* Note: The spec clearly says that when tuning sequence
1706
* is being performed, the controller does not generate
1707
* interrupts other than Buffer Read Ready interrupt. But
1708
* to make sure we don't hit a controller bug, we _only_
1709
* enable Buffer Read Ready interrupt here.
1711
ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1712
sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1715
* Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1716
* of loops reaches 40 times or a timeout of 150ms occurs.
1720
struct mmc_command cmd = {0};
1721
struct mmc_request mrq = {NULL};
1723
if (!tuning_loop_counter && !timeout)
1726
cmd.opcode = MMC_SEND_TUNING_BLOCK;
1728
cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1737
* In response to CMD19, the card sends 64 bytes of tuning
1738
* block to the Host Controller. So we set the block size
1741
sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1744
* The tuning block is sent by the card to the host controller.
1745
* So we set the TRNS_READ bit in the Transfer Mode register.
1746
* This also takes care of setting DMA Enable and Multi Block
1747
* Select in the same register to 0.
1749
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1751
sdhci_send_command(host, &cmd);
1756
spin_unlock(&host->lock);
1757
enable_irq(host->irq);
1759
/* Wait for Buffer Read Ready interrupt */
1760
wait_event_interruptible_timeout(host->buf_ready_int,
1761
(host->tuning_done == 1),
1762
msecs_to_jiffies(50));
1763
disable_irq(host->irq);
1764
spin_lock(&host->lock);
1766
if (!host->tuning_done) {
1767
pr_info(DRIVER_NAME ": Timeout waiting for "
1768
"Buffer Read Ready interrupt during tuning "
1769
"procedure, falling back to fixed sampling "
1771
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1772
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1773
ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1774
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1780
host->tuning_done = 0;
1782
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1783
tuning_loop_counter--;
1786
} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1789
* The Host Driver has exhausted the maximum number of loops allowed,
1790
* so use fixed sampling frequency.
1792
if (!tuning_loop_counter || !timeout) {
1793
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1794
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1796
if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1797
pr_info(DRIVER_NAME ": Tuning procedure"
1798
" failed, falling back to fixed sampling"
1806
* If this is the very first time we are here, we start the retuning
1807
* timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1808
* flag won't be set, we check this condition before actually starting
1811
if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1812
(host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1813
mod_timer(&host->tuning_timer, jiffies +
1814
host->tuning_count * HZ);
1815
/* Tuning mode 1 limits the maximum data length to 4MB */
1816
mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1818
host->flags &= ~SDHCI_NEEDS_RETUNING;
1819
/* Reload the new initial value for timer */
1820
if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1821
mod_timer(&host->tuning_timer, jiffies +
1822
host->tuning_count * HZ);
1826
* In case tuning fails, host controllers which support re-tuning can
1827
* try tuning again at a later time, when the re-tuning timer expires.
1828
* So for these controllers, we return 0. Since there might be other
1829
* controllers who do not have this capability, we return error for
1832
if (err && host->tuning_count &&
1833
host->tuning_mode == SDHCI_TUNING_MODE_1)
1836
sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1837
spin_unlock(&host->lock);
1838
enable_irq(host->irq);
1839
sdhci_runtime_pm_put(host);
1844
static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1847
unsigned long flags;
1849
/* Host Controller v3.00 defines preset value registers */
1850
if (host->version < SDHCI_SPEC_300)
1853
spin_lock_irqsave(&host->lock, flags);
1855
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1858
* We only enable or disable Preset Value if they are not already
1859
* enabled or disabled respectively. Otherwise, we bail out.
1861
if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1862
ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1863
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1864
host->flags |= SDHCI_PV_ENABLED;
1865
} else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1866
ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1867
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1868
host->flags &= ~SDHCI_PV_ENABLED;
1871
spin_unlock_irqrestore(&host->lock, flags);
1874
static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1876
struct sdhci_host *host = mmc_priv(mmc);
1878
sdhci_runtime_pm_get(host);
1879
sdhci_do_enable_preset_value(host, enable);
1880
sdhci_runtime_pm_put(host);
1883
static const struct mmc_host_ops sdhci_ops = {
1884
.request = sdhci_request,
1885
.set_ios = sdhci_set_ios,
1886
.get_ro = sdhci_get_ro,
1887
.hw_reset = sdhci_hw_reset,
1888
.enable_sdio_irq = sdhci_enable_sdio_irq,
1889
.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
1890
.execute_tuning = sdhci_execute_tuning,
1891
.enable_preset_value = sdhci_enable_preset_value,
1894
/*****************************************************************************\
1898
\*****************************************************************************/
1900
static void sdhci_tasklet_card(unsigned long param)
1902
struct sdhci_host *host;
1903
unsigned long flags;
1905
host = (struct sdhci_host*)param;
1907
spin_lock_irqsave(&host->lock, flags);
1909
/* Check host->mrq first in case we are runtime suspended */
1911
!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1912
pr_err("%s: Card removed during transfer!\n",
1913
mmc_hostname(host->mmc));
1914
pr_err("%s: Resetting controller.\n",
1915
mmc_hostname(host->mmc));
1917
sdhci_reset(host, SDHCI_RESET_CMD);
1918
sdhci_reset(host, SDHCI_RESET_DATA);
1920
host->mrq->cmd->error = -ENOMEDIUM;
1921
tasklet_schedule(&host->finish_tasklet);
1924
spin_unlock_irqrestore(&host->lock, flags);
1926
mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1929
static void sdhci_tasklet_finish(unsigned long param)
1931
struct sdhci_host *host;
1932
unsigned long flags;
1933
struct mmc_request *mrq;
1935
host = (struct sdhci_host*)param;
1937
spin_lock_irqsave(&host->lock, flags);
1940
* If this tasklet gets rescheduled while running, it will
1941
* be run again afterwards but without any active request.
1944
spin_unlock_irqrestore(&host->lock, flags);
1948
del_timer(&host->timer);
1953
* The controller needs a reset of internal state machines
1954
* upon error conditions.
1956
if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1957
((mrq->cmd && mrq->cmd->error) ||
1958
(mrq->data && (mrq->data->error ||
1959
(mrq->data->stop && mrq->data->stop->error))) ||
1960
(host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1962
/* Some controllers need this kick or reset won't work here */
1963
if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1966
/* This is to force an update */
1967
clock = host->clock;
1969
sdhci_set_clock(host, clock);
1972
/* Spec says we should do both at the same time, but Ricoh
1973
controllers do not like that. */
1974
sdhci_reset(host, SDHCI_RESET_CMD);
1975
sdhci_reset(host, SDHCI_RESET_DATA);
1982
#ifndef SDHCI_USE_LEDS_CLASS
1983
sdhci_deactivate_led(host);
1987
spin_unlock_irqrestore(&host->lock, flags);
1989
mmc_request_done(host->mmc, mrq);
1990
sdhci_runtime_pm_put(host);
1993
static void sdhci_timeout_timer(unsigned long data)
1995
struct sdhci_host *host;
1996
unsigned long flags;
1998
host = (struct sdhci_host*)data;
2000
spin_lock_irqsave(&host->lock, flags);
2003
pr_err("%s: Timeout waiting for hardware "
2004
"interrupt.\n", mmc_hostname(host->mmc));
2005
sdhci_dumpregs(host);
2008
host->data->error = -ETIMEDOUT;
2009
sdhci_finish_data(host);
2012
host->cmd->error = -ETIMEDOUT;
2014
host->mrq->cmd->error = -ETIMEDOUT;
2016
tasklet_schedule(&host->finish_tasklet);
2021
spin_unlock_irqrestore(&host->lock, flags);
2024
static void sdhci_tuning_timer(unsigned long data)
2026
struct sdhci_host *host;
2027
unsigned long flags;
2029
host = (struct sdhci_host *)data;
2031
spin_lock_irqsave(&host->lock, flags);
2033
host->flags |= SDHCI_NEEDS_RETUNING;
2035
spin_unlock_irqrestore(&host->lock, flags);
2038
/*****************************************************************************\
2040
* Interrupt handling *
2042
\*****************************************************************************/
2044
static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2046
BUG_ON(intmask == 0);
2049
pr_err("%s: Got command interrupt 0x%08x even "
2050
"though no command operation was in progress.\n",
2051
mmc_hostname(host->mmc), (unsigned)intmask);
2052
sdhci_dumpregs(host);
2056
if (intmask & SDHCI_INT_TIMEOUT)
2057
host->cmd->error = -ETIMEDOUT;
2058
else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2060
host->cmd->error = -EILSEQ;
2062
if (host->cmd->error) {
2063
tasklet_schedule(&host->finish_tasklet);
2068
* The host can send and interrupt when the busy state has
2069
* ended, allowing us to wait without wasting CPU cycles.
2070
* Unfortunately this is overloaded on the "data complete"
2071
* interrupt, so we need to take some care when handling
2074
* Note: The 1.0 specification is a bit ambiguous about this
2075
* feature so there might be some problems with older
2078
if (host->cmd->flags & MMC_RSP_BUSY) {
2079
if (host->cmd->data)
2080
DBG("Cannot wait for busy signal when also "
2081
"doing a data transfer");
2082
else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2085
/* The controller does not support the end-of-busy IRQ,
2086
* fall through and take the SDHCI_INT_RESPONSE */
2089
if (intmask & SDHCI_INT_RESPONSE)
2090
sdhci_finish_command(host);
2093
#ifdef CONFIG_MMC_DEBUG
2094
static void sdhci_show_adma_error(struct sdhci_host *host)
2096
const char *name = mmc_hostname(host->mmc);
2097
u8 *desc = host->adma_desc;
2102
sdhci_dumpregs(host);
2105
dma = (__le32 *)(desc + 4);
2106
len = (__le16 *)(desc + 2);
2109
DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2110
name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2119
static void sdhci_show_adma_error(struct sdhci_host *host) { }
2122
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2124
BUG_ON(intmask == 0);
2126
/* CMD19 generates _only_ Buffer Read Ready interrupt */
2127
if (intmask & SDHCI_INT_DATA_AVAIL) {
2128
if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2129
MMC_SEND_TUNING_BLOCK) {
2130
host->tuning_done = 1;
2131
wake_up(&host->buf_ready_int);
2138
* The "data complete" interrupt is also used to
2139
* indicate that a busy state has ended. See comment
2140
* above in sdhci_cmd_irq().
2142
if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2143
if (intmask & SDHCI_INT_DATA_END) {
2144
sdhci_finish_command(host);
2149
pr_err("%s: Got data interrupt 0x%08x even "
2150
"though no data operation was in progress.\n",
2151
mmc_hostname(host->mmc), (unsigned)intmask);
2152
sdhci_dumpregs(host);
2157
if (intmask & SDHCI_INT_DATA_TIMEOUT)
2158
host->data->error = -ETIMEDOUT;
2159
else if (intmask & SDHCI_INT_DATA_END_BIT)
2160
host->data->error = -EILSEQ;
2161
else if ((intmask & SDHCI_INT_DATA_CRC) &&
2162
SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2164
host->data->error = -EILSEQ;
2165
else if (intmask & SDHCI_INT_ADMA_ERROR) {
2166
pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2167
sdhci_show_adma_error(host);
2168
host->data->error = -EIO;
2171
if (host->data->error)
2172
sdhci_finish_data(host);
2174
if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2175
sdhci_transfer_pio(host);
2178
* We currently don't do anything fancy with DMA
2179
* boundaries, but as we can't disable the feature
2180
* we need to at least restart the transfer.
2182
* According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2183
* should return a valid address to continue from, but as
2184
* some controllers are faulty, don't trust them.
2186
if (intmask & SDHCI_INT_DMA_END) {
2187
u32 dmastart, dmanow;
2188
dmastart = sg_dma_address(host->data->sg);
2189
dmanow = dmastart + host->data->bytes_xfered;
2191
* Force update to the next DMA block boundary.
2194
~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2195
SDHCI_DEFAULT_BOUNDARY_SIZE;
2196
host->data->bytes_xfered = dmanow - dmastart;
2197
DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2199
mmc_hostname(host->mmc), dmastart,
2200
host->data->bytes_xfered, dmanow);
2201
sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2204
if (intmask & SDHCI_INT_DATA_END) {
2207
* Data managed to finish before the
2208
* command completed. Make sure we do
2209
* things in the proper order.
2211
host->data_early = 1;
2213
sdhci_finish_data(host);
2219
static irqreturn_t sdhci_irq(int irq, void *dev_id)
2222
struct sdhci_host *host = dev_id;
2226
spin_lock(&host->lock);
2228
if (host->runtime_suspended) {
2229
spin_unlock(&host->lock);
2230
pr_warning("%s: got irq while runtime suspended\n",
2231
mmc_hostname(host->mmc));
2235
intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2237
if (!intmask || intmask == 0xffffffff) {
2242
DBG("*** %s got interrupt: 0x%08x\n",
2243
mmc_hostname(host->mmc), intmask);
2245
if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2246
u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2250
* There is a observation on i.mx esdhc. INSERT bit will be
2251
* immediately set again when it gets cleared, if a card is
2252
* inserted. We have to mask the irq to prevent interrupt
2253
* storm which will freeze the system. And the REMOVE gets
2254
* the same situation.
2256
* More testing are needed here to ensure it works for other
2259
sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2260
SDHCI_INT_CARD_REMOVE);
2261
sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2262
SDHCI_INT_CARD_INSERT);
2264
sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2265
SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2266
intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2267
tasklet_schedule(&host->card_tasklet);
2270
if (intmask & SDHCI_INT_CMD_MASK) {
2271
sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2273
sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2276
if (intmask & SDHCI_INT_DATA_MASK) {
2277
sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2279
sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2282
intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2284
intmask &= ~SDHCI_INT_ERROR;
2286
if (intmask & SDHCI_INT_BUS_POWER) {
2287
pr_err("%s: Card is consuming too much power!\n",
2288
mmc_hostname(host->mmc));
2289
sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2292
intmask &= ~SDHCI_INT_BUS_POWER;
2294
if (intmask & SDHCI_INT_CARD_INT)
2297
intmask &= ~SDHCI_INT_CARD_INT;
2300
pr_err("%s: Unexpected interrupt 0x%08x.\n",
2301
mmc_hostname(host->mmc), intmask);
2302
sdhci_dumpregs(host);
2304
sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2307
result = IRQ_HANDLED;
2311
spin_unlock(&host->lock);
2314
* We have to delay this as it calls back into the driver.
2317
mmc_signal_sdio_irq(host->mmc);
2322
/*****************************************************************************\
2326
\*****************************************************************************/
2330
int sdhci_suspend_host(struct sdhci_host *host)
2334
sdhci_disable_card_detection(host);
2336
/* Disable tuning since we are suspending */
2337
if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2338
host->tuning_mode == SDHCI_TUNING_MODE_1) {
2339
host->flags &= ~SDHCI_NEEDS_RETUNING;
2340
mod_timer(&host->tuning_timer, jiffies +
2341
host->tuning_count * HZ);
2344
ret = mmc_suspend_host(host->mmc);
2348
free_irq(host->irq, host);
2351
ret = regulator_disable(host->vmmc);
2356
EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2358
int sdhci_resume_host(struct sdhci_host *host)
2363
int ret = regulator_enable(host->vmmc);
2368
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2369
if (host->ops->enable_dma)
2370
host->ops->enable_dma(host);
2373
ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2374
mmc_hostname(host->mmc), host);
2378
sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2381
ret = mmc_resume_host(host->mmc);
2382
sdhci_enable_card_detection(host);
2384
/* Set the re-tuning expiration flag */
2385
if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2386
(host->tuning_mode == SDHCI_TUNING_MODE_1))
2387
host->flags |= SDHCI_NEEDS_RETUNING;
2392
EXPORT_SYMBOL_GPL(sdhci_resume_host);
2394
void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2397
val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2398
val |= SDHCI_WAKE_ON_INT;
2399
sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2402
EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2404
#endif /* CONFIG_PM */
2406
#ifdef CONFIG_PM_RUNTIME
2408
static int sdhci_runtime_pm_get(struct sdhci_host *host)
2410
return pm_runtime_get_sync(host->mmc->parent);
2413
static int sdhci_runtime_pm_put(struct sdhci_host *host)
2415
pm_runtime_mark_last_busy(host->mmc->parent);
2416
return pm_runtime_put_autosuspend(host->mmc->parent);
2419
int sdhci_runtime_suspend_host(struct sdhci_host *host)
2421
unsigned long flags;
2424
/* Disable tuning since we are suspending */
2425
if (host->version >= SDHCI_SPEC_300 &&
2426
host->tuning_mode == SDHCI_TUNING_MODE_1) {
2427
del_timer_sync(&host->tuning_timer);
2428
host->flags &= ~SDHCI_NEEDS_RETUNING;
2431
spin_lock_irqsave(&host->lock, flags);
2432
sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2433
spin_unlock_irqrestore(&host->lock, flags);
2435
synchronize_irq(host->irq);
2437
spin_lock_irqsave(&host->lock, flags);
2438
host->runtime_suspended = true;
2439
spin_unlock_irqrestore(&host->lock, flags);
2443
EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2445
int sdhci_runtime_resume_host(struct sdhci_host *host)
2447
unsigned long flags;
2448
int ret = 0, host_flags = host->flags;
2450
if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2451
if (host->ops->enable_dma)
2452
host->ops->enable_dma(host);
2455
sdhci_init(host, 0);
2457
/* Force clock and power re-program */
2460
sdhci_do_set_ios(host, &host->mmc->ios);
2462
sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2463
if (host_flags & SDHCI_PV_ENABLED)
2464
sdhci_do_enable_preset_value(host, true);
2466
/* Set the re-tuning expiration flag */
2467
if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2468
(host->tuning_mode == SDHCI_TUNING_MODE_1))
2469
host->flags |= SDHCI_NEEDS_RETUNING;
2471
spin_lock_irqsave(&host->lock, flags);
2473
host->runtime_suspended = false;
2475
/* Enable SDIO IRQ */
2476
if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2477
sdhci_enable_sdio_irq_nolock(host, true);
2479
/* Enable Card Detection */
2480
sdhci_enable_card_detection(host);
2482
spin_unlock_irqrestore(&host->lock, flags);
2486
EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2490
/*****************************************************************************\
2492
* Device allocation/registration *
2494
\*****************************************************************************/
2496
struct sdhci_host *sdhci_alloc_host(struct device *dev,
2499
struct mmc_host *mmc;
2500
struct sdhci_host *host;
2502
WARN_ON(dev == NULL);
2504
mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2506
return ERR_PTR(-ENOMEM);
2508
host = mmc_priv(mmc);
2514
EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2516
int sdhci_add_host(struct sdhci_host *host)
2518
struct mmc_host *mmc;
2520
u32 max_current_caps;
2521
unsigned int ocr_avail;
2524
WARN_ON(host == NULL);
2531
host->quirks = debug_quirks;
2533
host->quirks2 = debug_quirks2;
2535
sdhci_reset(host, SDHCI_RESET_ALL);
2537
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2538
host->version = (host->version & SDHCI_SPEC_VER_MASK)
2539
>> SDHCI_SPEC_VER_SHIFT;
2540
if (host->version > SDHCI_SPEC_300) {
2541
pr_err("%s: Unknown controller version (%d). "
2542
"You may experience problems.\n", mmc_hostname(mmc),
2546
caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2547
sdhci_readl(host, SDHCI_CAPABILITIES);
2549
caps[1] = (host->version >= SDHCI_SPEC_300) ?
2550
sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2552
if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2553
host->flags |= SDHCI_USE_SDMA;
2554
else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2555
DBG("Controller doesn't have SDMA capability\n");
2557
host->flags |= SDHCI_USE_SDMA;
2559
if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2560
(host->flags & SDHCI_USE_SDMA)) {
2561
DBG("Disabling DMA as it is marked broken\n");
2562
host->flags &= ~SDHCI_USE_SDMA;
2565
if ((host->version >= SDHCI_SPEC_200) &&
2566
(caps[0] & SDHCI_CAN_DO_ADMA2))
2567
host->flags |= SDHCI_USE_ADMA;
2569
if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2570
(host->flags & SDHCI_USE_ADMA)) {
2571
DBG("Disabling ADMA as it is marked broken\n");
2572
host->flags &= ~SDHCI_USE_ADMA;
2575
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2576
if (host->ops->enable_dma) {
2577
if (host->ops->enable_dma(host)) {
2578
pr_warning("%s: No suitable DMA "
2579
"available. Falling back to PIO.\n",
2582
~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2587
if (host->flags & SDHCI_USE_ADMA) {
2589
* We need to allocate descriptors for all sg entries
2590
* (128) and potentially one alignment transfer for
2591
* each of those entries.
2593
host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2594
host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2595
if (!host->adma_desc || !host->align_buffer) {
2596
kfree(host->adma_desc);
2597
kfree(host->align_buffer);
2598
pr_warning("%s: Unable to allocate ADMA "
2599
"buffers. Falling back to standard DMA.\n",
2601
host->flags &= ~SDHCI_USE_ADMA;
2606
* If we use DMA, then it's up to the caller to set the DMA
2607
* mask, but PIO does not need the hw shim so we set a new
2608
* mask here in that case.
2610
if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2611
host->dma_mask = DMA_BIT_MASK(64);
2612
mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2615
if (host->version >= SDHCI_SPEC_300)
2616
host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2617
>> SDHCI_CLOCK_BASE_SHIFT;
2619
host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2620
>> SDHCI_CLOCK_BASE_SHIFT;
2622
host->max_clk *= 1000000;
2623
if (host->max_clk == 0 || host->quirks &
2624
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2625
if (!host->ops->get_max_clock) {
2626
pr_err("%s: Hardware doesn't specify base clock "
2627
"frequency.\n", mmc_hostname(mmc));
2630
host->max_clk = host->ops->get_max_clock(host);
2634
* In case of Host Controller v3.00, find out whether clock
2635
* multiplier is supported.
2637
host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2638
SDHCI_CLOCK_MUL_SHIFT;
2641
* In case the value in Clock Multiplier is 0, then programmable
2642
* clock mode is not supported, otherwise the actual clock
2643
* multiplier is one more than the value of Clock Multiplier
2644
* in the Capabilities Register.
2650
* Set host parameters.
2652
mmc->ops = &sdhci_ops;
2653
mmc->f_max = host->max_clk;
2654
if (host->ops->get_min_clock)
2655
mmc->f_min = host->ops->get_min_clock(host);
2656
else if (host->version >= SDHCI_SPEC_300) {
2657
if (host->clk_mul) {
2658
mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2659
mmc->f_max = host->max_clk * host->clk_mul;
2661
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2663
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2666
(caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2667
if (host->timeout_clk == 0) {
2668
if (host->ops->get_timeout_clock) {
2669
host->timeout_clk = host->ops->get_timeout_clock(host);
2670
} else if (!(host->quirks &
2671
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2672
pr_err("%s: Hardware doesn't specify timeout clock "
2673
"frequency.\n", mmc_hostname(mmc));
2677
if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2678
host->timeout_clk *= 1000;
2680
if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2681
host->timeout_clk = mmc->f_max / 1000;
2683
mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2685
mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2687
if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2688
host->flags |= SDHCI_AUTO_CMD12;
2690
/* Auto-CMD23 stuff only works in ADMA or PIO. */
2691
if ((host->version >= SDHCI_SPEC_300) &&
2692
((host->flags & SDHCI_USE_ADMA) ||
2693
!(host->flags & SDHCI_USE_SDMA))) {
2694
host->flags |= SDHCI_AUTO_CMD23;
2695
DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2697
DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2701
* A controller may support 8-bit width, but the board itself
2702
* might not have the pins brought out. Boards that support
2703
* 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2704
* their platform code before calling sdhci_add_host(), and we
2705
* won't assume 8-bit width for hosts without that CAP.
2707
if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2708
mmc->caps |= MMC_CAP_4_BIT_DATA;
2710
if (caps[0] & SDHCI_CAN_DO_HISPD)
2711
mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2713
if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2714
mmc_card_is_removable(mmc))
2715
mmc->caps |= MMC_CAP_NEEDS_POLL;
2717
/* UHS-I mode(s) supported by the host controller. */
2718
if (host->version >= SDHCI_SPEC_300)
2719
mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2721
/* SDR104 supports also implies SDR50 support */
2722
if (caps[1] & SDHCI_SUPPORT_SDR104)
2723
mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2724
else if (caps[1] & SDHCI_SUPPORT_SDR50)
2725
mmc->caps |= MMC_CAP_UHS_SDR50;
2727
if (caps[1] & SDHCI_SUPPORT_DDR50)
2728
mmc->caps |= MMC_CAP_UHS_DDR50;
2730
/* Does the host needs tuning for SDR50? */
2731
if (caps[1] & SDHCI_USE_SDR50_TUNING)
2732
host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2734
/* Driver Type(s) (A, C, D) supported by the host */
2735
if (caps[1] & SDHCI_DRIVER_TYPE_A)
2736
mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2737
if (caps[1] & SDHCI_DRIVER_TYPE_C)
2738
mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2739
if (caps[1] & SDHCI_DRIVER_TYPE_D)
2740
mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2743
* If Power Off Notify capability is enabled by the host,
2744
* set notify to short power off notify timeout value.
2746
if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2747
mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2749
mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2751
/* Initial value for re-tuning timer count */
2752
host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2753
SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2756
* In case Re-tuning Timer is not disabled, the actual value of
2757
* re-tuning timer will be 2 ^ (n - 1).
2759
if (host->tuning_count)
2760
host->tuning_count = 1 << (host->tuning_count - 1);
2762
/* Re-tuning mode supported by the Host Controller */
2763
host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2764
SDHCI_RETUNING_MODE_SHIFT;
2768
* According to SD Host Controller spec v3.00, if the Host System
2769
* can afford more than 150mA, Host Driver should set XPC to 1. Also
2770
* the value is meaningful only if Voltage Support in the Capabilities
2771
* register is set. The actual current value is 4 times the register
2774
max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2776
if (caps[0] & SDHCI_CAN_VDD_330) {
2777
int max_current_330;
2779
ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2781
max_current_330 = ((max_current_caps &
2782
SDHCI_MAX_CURRENT_330_MASK) >>
2783
SDHCI_MAX_CURRENT_330_SHIFT) *
2784
SDHCI_MAX_CURRENT_MULTIPLIER;
2786
if (max_current_330 > 150)
2787
mmc->caps |= MMC_CAP_SET_XPC_330;
2789
if (caps[0] & SDHCI_CAN_VDD_300) {
2790
int max_current_300;
2792
ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2794
max_current_300 = ((max_current_caps &
2795
SDHCI_MAX_CURRENT_300_MASK) >>
2796
SDHCI_MAX_CURRENT_300_SHIFT) *
2797
SDHCI_MAX_CURRENT_MULTIPLIER;
2799
if (max_current_300 > 150)
2800
mmc->caps |= MMC_CAP_SET_XPC_300;
2802
if (caps[0] & SDHCI_CAN_VDD_180) {
2803
int max_current_180;
2805
ocr_avail |= MMC_VDD_165_195;
2807
max_current_180 = ((max_current_caps &
2808
SDHCI_MAX_CURRENT_180_MASK) >>
2809
SDHCI_MAX_CURRENT_180_SHIFT) *
2810
SDHCI_MAX_CURRENT_MULTIPLIER;
2812
if (max_current_180 > 150)
2813
mmc->caps |= MMC_CAP_SET_XPC_180;
2815
/* Maximum current capabilities of the host at 1.8V */
2816
if (max_current_180 >= 800)
2817
mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2818
else if (max_current_180 >= 600)
2819
mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2820
else if (max_current_180 >= 400)
2821
mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2823
mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2826
mmc->ocr_avail = ocr_avail;
2827
mmc->ocr_avail_sdio = ocr_avail;
2828
if (host->ocr_avail_sdio)
2829
mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2830
mmc->ocr_avail_sd = ocr_avail;
2831
if (host->ocr_avail_sd)
2832
mmc->ocr_avail_sd &= host->ocr_avail_sd;
2833
else /* normal SD controllers don't support 1.8V */
2834
mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2835
mmc->ocr_avail_mmc = ocr_avail;
2836
if (host->ocr_avail_mmc)
2837
mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2839
if (mmc->ocr_avail == 0) {
2840
pr_err("%s: Hardware doesn't report any "
2841
"support voltages.\n", mmc_hostname(mmc));
2845
spin_lock_init(&host->lock);
2848
* Maximum number of segments. Depends on if the hardware
2849
* can do scatter/gather or not.
2851
if (host->flags & SDHCI_USE_ADMA)
2852
mmc->max_segs = 128;
2853
else if (host->flags & SDHCI_USE_SDMA)
2856
mmc->max_segs = 128;
2859
* Maximum number of sectors in one transfer. Limited by DMA boundary
2862
mmc->max_req_size = 524288;
2865
* Maximum segment size. Could be one segment with the maximum number
2866
* of bytes. When doing hardware scatter/gather, each entry cannot
2867
* be larger than 64 KiB though.
2869
if (host->flags & SDHCI_USE_ADMA) {
2870
if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2871
mmc->max_seg_size = 65535;
2873
mmc->max_seg_size = 65536;
2875
mmc->max_seg_size = mmc->max_req_size;
2879
* Maximum block size. This varies from controller to controller and
2880
* is specified in the capabilities register.
2882
if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2883
mmc->max_blk_size = 2;
2885
mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2886
SDHCI_MAX_BLOCK_SHIFT;
2887
if (mmc->max_blk_size >= 3) {
2888
pr_warning("%s: Invalid maximum block size, "
2889
"assuming 512 bytes\n", mmc_hostname(mmc));
2890
mmc->max_blk_size = 0;
2894
mmc->max_blk_size = 512 << mmc->max_blk_size;
2897
* Maximum block count.
2899
mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2904
tasklet_init(&host->card_tasklet,
2905
sdhci_tasklet_card, (unsigned long)host);
2906
tasklet_init(&host->finish_tasklet,
2907
sdhci_tasklet_finish, (unsigned long)host);
2909
setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2911
if (host->version >= SDHCI_SPEC_300) {
2912
init_waitqueue_head(&host->buf_ready_int);
2914
/* Initialize re-tuning timer */
2915
init_timer(&host->tuning_timer);
2916
host->tuning_timer.data = (unsigned long)host;
2917
host->tuning_timer.function = sdhci_tuning_timer;
2920
ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2921
mmc_hostname(mmc), host);
2925
host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2926
if (IS_ERR(host->vmmc)) {
2927
pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2930
regulator_enable(host->vmmc);
2933
sdhci_init(host, 0);
2935
#ifdef CONFIG_MMC_DEBUG
2936
sdhci_dumpregs(host);
2939
#ifdef SDHCI_USE_LEDS_CLASS
2940
snprintf(host->led_name, sizeof(host->led_name),
2941
"%s::", mmc_hostname(mmc));
2942
host->led.name = host->led_name;
2943
host->led.brightness = LED_OFF;
2944
host->led.default_trigger = mmc_hostname(mmc);
2945
host->led.brightness_set = sdhci_led_control;
2947
ret = led_classdev_register(mmc_dev(mmc), &host->led);
2956
pr_info("%s: SDHCI controller on %s [%s] using %s\n",
2957
mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2958
(host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2959
(host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2961
sdhci_enable_card_detection(host);
2965
#ifdef SDHCI_USE_LEDS_CLASS
2967
sdhci_reset(host, SDHCI_RESET_ALL);
2968
free_irq(host->irq, host);
2971
tasklet_kill(&host->card_tasklet);
2972
tasklet_kill(&host->finish_tasklet);
2977
EXPORT_SYMBOL_GPL(sdhci_add_host);
2979
void sdhci_remove_host(struct sdhci_host *host, int dead)
2981
unsigned long flags;
2984
spin_lock_irqsave(&host->lock, flags);
2986
host->flags |= SDHCI_DEVICE_DEAD;
2989
pr_err("%s: Controller removed during "
2990
" transfer!\n", mmc_hostname(host->mmc));
2992
host->mrq->cmd->error = -ENOMEDIUM;
2993
tasklet_schedule(&host->finish_tasklet);
2996
spin_unlock_irqrestore(&host->lock, flags);
2999
sdhci_disable_card_detection(host);
3001
mmc_remove_host(host->mmc);
3003
#ifdef SDHCI_USE_LEDS_CLASS
3004
led_classdev_unregister(&host->led);
3008
sdhci_reset(host, SDHCI_RESET_ALL);
3010
free_irq(host->irq, host);
3012
del_timer_sync(&host->timer);
3013
if (host->version >= SDHCI_SPEC_300)
3014
del_timer_sync(&host->tuning_timer);
3016
tasklet_kill(&host->card_tasklet);
3017
tasklet_kill(&host->finish_tasklet);
3020
regulator_disable(host->vmmc);
3021
regulator_put(host->vmmc);
3024
kfree(host->adma_desc);
3025
kfree(host->align_buffer);
3027
host->adma_desc = NULL;
3028
host->align_buffer = NULL;
3031
EXPORT_SYMBOL_GPL(sdhci_remove_host);
3033
void sdhci_free_host(struct sdhci_host *host)
3035
mmc_free_host(host->mmc);
3038
EXPORT_SYMBOL_GPL(sdhci_free_host);
3040
/*****************************************************************************\
3042
* Driver init/exit *
3044
\*****************************************************************************/
3046
static int __init sdhci_drv_init(void)
3049
": Secure Digital Host Controller Interface driver\n");
3050
pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3055
static void __exit sdhci_drv_exit(void)
3059
module_init(sdhci_drv_init);
3060
module_exit(sdhci_drv_exit);
3062
module_param(debug_quirks, uint, 0444);
3063
module_param(debug_quirks2, uint, 0444);
3065
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3066
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3067
MODULE_LICENSE("GPL");
3069
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3070
MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");