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* MPC8349E-mITX-GP Device Tree Source
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* Copyright 2007 Freescale Semiconductor Inc.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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model = "MPC8349EMITXGP";
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compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX";
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>; // from bootloader
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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compatible = "fsl-i2c";
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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compatible = "fsl-i2c";
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interrupts = <15 0x8>;
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interrupt-parent = <&ipic>;
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compatible = "dallas,ds1339";
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interrupts = <18 0x8>;
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interrupt-parent = <&ipic>;
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compatible = "fsl,spi";
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reg = <0x7000 0x1000>;
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interrupts = <16 0x8>;
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interrupt-parent = <&ipic>;
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#address-cells = <1>;
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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interrupt-parent = <&ipic>;
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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interrupt-parent = <&ipic>;
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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interrupt-parent = <&ipic>;
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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interrupt-parent = <&ipic>;
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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interrupt-parent = <&ipic>;
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interrupts = <38 0x8>;
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enet0: ethernet@24000 {
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#address-cells = <1>;
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device_type = "network";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <32 0x8 33 0x8 34 0x8>;
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interrupt-parent = <&ipic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy1c>;
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linux,network-index = <0>;
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#address-cells = <1>;
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compatible = "fsl,gianfar-mdio";
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phy1c: ethernet-phy@1c {
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interrupt-parent = <&ipic>;
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interrupts = <18 0x8>;
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device_type = "ethernet-phy";
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device_type = "tbi-phy";
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serial0: serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>; // from bootloader
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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serial1: serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>; // from bootloader
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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compatible = "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x7e>;
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fsl,descriptor-types-mask = <0x01010ebf>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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device_type = "ipic";
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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/* IDSEL 0x0F - PCI Slot */
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0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
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0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
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interrupt-parent = <&ipic>;
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interrupts = <67 0x8>;
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bus-range = <0x1 0x1>;
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ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#address-cells = <3>;
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reg = <0xe0008600 0x100 /* internal registers */
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0xe0008380 0x8>; /* config space access registers */
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compatible = "fsl,mpc8349-pci";