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* Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
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* Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
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* Copyright (C) 2009 Nuvoton PS Team
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* Special thanks to Nuvoton for providing hardware, spec sheets and
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* sample code upon which portions of this driver are based. Indirect
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* thanks also to Maxim Levitsky, whose ene_ir driver this driver is
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pnp.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <media/rc-core.h>
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#include <linux/pci_ids.h>
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#include "nuvoton-cir.h"
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/* write val to config reg */
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static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
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outb(reg, nvt->cr_efir);
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outb(val, nvt->cr_efdr);
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/* read val from config reg */
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static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
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outb(reg, nvt->cr_efir);
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return inb(nvt->cr_efdr);
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/* update config register bit without changing other bits */
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static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
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u8 tmp = nvt_cr_read(nvt, reg) | val;
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nvt_cr_write(nvt, tmp, reg);
61
/* clear config register bit without changing other bits */
62
static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
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u8 tmp = nvt_cr_read(nvt, reg) & ~val;
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nvt_cr_write(nvt, tmp, reg);
68
/* enter extended function mode */
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static inline void nvt_efm_enable(struct nvt_dev *nvt)
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/* Enabling Extended Function Mode explicitly requires writing 2x */
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outb(EFER_EFM_ENABLE, nvt->cr_efir);
73
outb(EFER_EFM_ENABLE, nvt->cr_efir);
76
/* exit extended function mode */
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static inline void nvt_efm_disable(struct nvt_dev *nvt)
79
outb(EFER_EFM_DISABLE, nvt->cr_efir);
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* When you want to address a specific logical device, write its logical
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* device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
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* 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
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static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
89
outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
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outb(ldev, nvt->cr_efdr);
93
/* write val to cir config register */
94
static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
96
outb(val, nvt->cir_addr + offset);
99
/* read val from cir config register */
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static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
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val = inb(nvt->cir_addr + offset);
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/* write val to cir wake register */
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static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
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outb(val, nvt->cir_wake_addr + offset);
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/* read val from cir wake config register */
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static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
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val = inb(nvt->cir_wake_addr + offset);
126
#define pr_reg(text, ...) \
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printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
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/* dump current cir register contents */
130
static void cir_dump_regs(struct nvt_dev *nvt)
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
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pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
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pr_reg(" * CR CIR ACTIVE : 0x%x\n",
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nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
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pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
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(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
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nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
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pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
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nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
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nvt_efm_disable(nvt);
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pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
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pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
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pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
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pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
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pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
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pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
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pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
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pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
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pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
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pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
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pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
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pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
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pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
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pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
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pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
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pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
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pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
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/* dump current cir wake register contents */
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static void cir_wake_dump_regs(struct nvt_dev *nvt)
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
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pr_reg("%s: Dump CIR WAKE logical device registers:\n",
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pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
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nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
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pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
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(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
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nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
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pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
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nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
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nvt_efm_disable(nvt);
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pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
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pr_reg(" * IRCON: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
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pr_reg(" * IRSTS: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
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pr_reg(" * IREN: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
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pr_reg(" * FIFO CMP DEEP: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
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pr_reg(" * FIFO CMP TOL: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
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pr_reg(" * FIFO COUNT: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
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pr_reg(" * SLCH: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
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pr_reg(" * SLCL: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
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pr_reg(" * FIFOCON: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
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pr_reg(" * SRXFSTS: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
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pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
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pr_reg(" * WR FIFO DATA: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
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pr_reg(" * RD FIFO ONLY: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
212
pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
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pr_reg(" * FIFO IGNORE: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
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pr_reg(" * IRFSM: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
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fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
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pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
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pr_reg("* Contents = ");
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for (i = 0; i < fifo_len; i++)
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printk(KERN_CONT "%02x ",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
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printk(KERN_CONT "\n");
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/* detect hardware features */
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static int nvt_hw_detect(struct nvt_dev *nvt)
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u8 chip_major, chip_minor;
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bool chip_unknown = false;
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/* Check if we're wired for the alternate EFER setup */
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chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
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if (chip_major == 0xff) {
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nvt->cr_efir = CR_EFIR2;
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nvt->cr_efdr = CR_EFDR2;
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chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
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chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
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/* these are the known working chip revisions... */
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switch (chip_major) {
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case CHIP_ID_HIGH_667:
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strcpy(chip_id, "w83667hg\0");
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if (chip_minor != CHIP_ID_LOW_667)
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case CHIP_ID_HIGH_677B:
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strcpy(chip_id, "w83677hg\0");
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if (chip_minor != CHIP_ID_LOW_677B2 &&
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chip_minor != CHIP_ID_LOW_677B3)
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case CHIP_ID_HIGH_677C:
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strcpy(chip_id, "w83677hg-c\0");
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if (chip_minor != CHIP_ID_LOW_677C)
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strcpy(chip_id, "w836x7hg\0");
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/* warn, but still let the driver load, if we don't know this chip */
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nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
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"it may not work...", chip_id, chip_major, chip_minor);
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nvt_dbg("%s: chip id: 0x%02x 0x%02x",
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chip_id, chip_major, chip_minor);
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nvt_efm_disable(nvt);
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spin_lock_irqsave(&nvt->nvt_lock, flags);
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nvt->chip_major = chip_major;
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nvt->chip_minor = chip_minor;
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spin_unlock_irqrestore(&nvt->nvt_lock, flags);
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static void nvt_cir_ldev_init(struct nvt_dev *nvt)
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u8 val, psreg, psmask, psval;
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if (nvt->chip_major == CHIP_ID_HIGH_667) {
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psreg = CR_MULTIFUNC_PIN_SEL;
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psmask = MULTIFUNC_PIN_SEL_MASK;
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psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
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psreg = CR_OUTPUT_PIN_SEL;
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psmask = OUTPUT_PIN_SEL_MASK;
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psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
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/* output pin selection: enable CIR, with WB sensor enabled */
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val = nvt_cr_read(nvt, psreg);
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nvt_cr_write(nvt, val, psreg);
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/* Select CIR logical device and enable */
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
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nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
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nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
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nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
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nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
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nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
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nvt->cir_addr, nvt->cir_irq);
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static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
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/* Select ACPI logical device, enable it and CIR Wake */
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nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
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nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
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/* Enable CIR Wake via PSOUT# (Pin60) */
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nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
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/* enable cir interrupt of mouse/keyboard IRQ event */
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nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
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/* enable pme interrupt of cir wakeup event */
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nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
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/* Select CIR Wake logical device and enable */
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
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nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
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nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
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nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
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nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
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nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
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nvt->cir_wake_addr, nvt->cir_wake_irq);
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/* clear out the hardware's cir rx fifo */
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static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
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val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
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nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
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/* clear out the hardware's cir wake rx fifo */
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static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
367
val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
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nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
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/* clear out the hardware's cir tx fifo */
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static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
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val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
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nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
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/* enable RX Trigger Level Reach and Packet End interrupts */
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static void nvt_set_cir_iren(struct nvt_dev *nvt)
386
iren = CIR_IREN_RTR | CIR_IREN_PE;
387
nvt_cir_reg_write(nvt, iren, CIR_IREN);
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static void nvt_cir_regs_init(struct nvt_dev *nvt)
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/* set sample limit count (PE interrupt raised when reached) */
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nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
394
nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
396
/* set fifo irq trigger levels */
397
nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
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CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
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* Enable TX and RX, specify carrier on = low, off = high, and set
402
* sample period (currently 50us)
404
nvt_cir_reg_write(nvt,
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CIR_IRCON_TXEN | CIR_IRCON_RXEN |
406
CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
409
/* clear hardware rx and tx fifos */
410
nvt_clear_cir_fifo(nvt);
411
nvt_clear_tx_fifo(nvt);
413
/* clear any and all stray interrupts */
414
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
416
/* and finally, enable interrupts */
417
nvt_set_cir_iren(nvt);
420
static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
422
/* set number of bytes needed for wake from s3 (default 65) */
423
nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
424
CIR_WAKE_FIFO_CMP_DEEP);
426
/* set tolerance/variance allowed per byte during wake compare */
427
nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
428
CIR_WAKE_FIFO_CMP_TOL);
430
/* set sample limit count (PE interrupt raised when reached) */
431
nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
432
nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
434
/* set cir wake fifo rx trigger level (currently 67) */
435
nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
439
* Enable TX and RX, specific carrier on = low, off = high, and set
440
* sample period (currently 50us)
442
nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
443
CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
444
CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
447
/* clear cir wake rx fifo */
448
nvt_clear_cir_wake_fifo(nvt);
450
/* clear any and all stray interrupts */
451
nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
454
static void nvt_enable_wake(struct nvt_dev *nvt)
458
nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
459
nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
460
nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
461
nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
463
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
464
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
466
nvt_efm_disable(nvt);
468
nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
469
CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
470
CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
472
nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
473
nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
476
/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
477
static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
479
u32 count, carrier, duration = 0;
482
count = nvt_cir_reg_read(nvt, CIR_FCCL) |
483
nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
485
for (i = 0; i < nvt->pkts; i++) {
486
if (nvt->buf[i] & BUF_PULSE_BIT)
487
duration += nvt->buf[i] & BUF_LEN_MASK;
490
duration *= SAMPLE_PERIOD;
492
if (!count || !duration) {
493
nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
498
carrier = MS_TO_NS(count) / duration;
500
if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
501
nvt_dbg("WTF? Carrier frequency out of range!");
503
nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
504
carrier, count, duration);
510
* set carrier frequency
512
* set carrier on 2 registers: CP & CC
513
* always set CP as 0x81
514
* set CC by SPEC, CC = 3MHz/carrier - 1
516
static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
518
struct nvt_dev *nvt = dev->priv;
521
nvt_cir_reg_write(nvt, 1, CIR_CP);
522
val = 3000000 / (carrier) - 1;
523
nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
525
nvt_dbg("cp: 0x%x cc: 0x%x\n",
526
nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
534
* 1) clean TX fifo first (handled by AP)
535
* 2) copy data from user space
536
* 3) disable RX interrupts, enable TX interrupts: TTR & TFU
537
* 4) send 9 packets to TX FIFO to open TTR
538
* in interrupt_handler:
539
* 5) send all data out
540
* go back to write():
541
* 6) disable TX interrupts, re-enable RX interupts
543
* The key problem of this function is user space data may larger than
544
* driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
545
* buf, and keep current copied data buf num in cur_buf_num. But driver's buf
546
* number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
547
* set TXFCONT as 0xff, until buf_count less than 0xff.
549
static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
551
struct nvt_dev *nvt = dev->priv;
557
spin_lock_irqsave(&nvt->tx.lock, flags);
559
ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
560
nvt->tx.buf_count = (ret * sizeof(unsigned));
562
memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
564
nvt->tx.cur_buf_num = 0;
566
/* save currently enabled interrupts */
567
iren = nvt_cir_reg_read(nvt, CIR_IREN);
569
/* now disable all interrupts, save TFU & TTR */
570
nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
572
nvt->tx.tx_state = ST_TX_REPLY;
574
nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
575
CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
577
/* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
578
for (i = 0; i < 9; i++)
579
nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
581
spin_unlock_irqrestore(&nvt->tx.lock, flags);
583
wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
585
spin_lock_irqsave(&nvt->tx.lock, flags);
586
nvt->tx.tx_state = ST_TX_NONE;
587
spin_unlock_irqrestore(&nvt->tx.lock, flags);
589
/* restore enabled interrupts to prior state */
590
nvt_cir_reg_write(nvt, iren, CIR_IREN);
595
/* dump contents of the last rx buffer we got from the hw rx fifo */
596
static void nvt_dump_rx_buf(struct nvt_dev *nvt)
600
printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
601
for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
602
printk(KERN_CONT "0x%02x ", nvt->buf[i]);
603
printk(KERN_CONT "\n");
607
* Process raw data in rx driver buffer, store it in raw IR event kfifo,
608
* trigger decode when appropriate.
610
* We get IR data samples one byte at a time. If the msb is set, its a pulse,
611
* otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
612
* (default 50us) intervals for that pulse/space. A discrete signal is
613
* followed by a series of 0x7f packets, then either 0x7<something> or 0x80
614
* to signal more IR coming (repeats) or end of IR, respectively. We store
615
* sample data in the raw event kfifo until we see 0x7<something> (except f)
616
* or 0x80, at which time, we trigger a decode operation.
618
static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
620
DEFINE_IR_RAW_EVENT(rawir);
625
nvt_dbg_verbose("%s firing", __func__);
628
nvt_dump_rx_buf(nvt);
630
if (nvt->carrier_detect_enabled)
631
carrier = nvt_rx_carrier_detect(nvt);
633
nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
635
init_ir_raw_event(&rawir);
637
for (i = 0; i < nvt->pkts; i++) {
638
sample = nvt->buf[i];
640
rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
641
rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
644
nvt_dbg("Storing %s with duration %d",
645
rawir.pulse ? "pulse" : "space", rawir.duration);
647
ir_raw_event_store_with_filter(nvt->rdev, &rawir);
650
* BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
651
* indicates end of IR signal, but new data incoming. In both
652
* cases, it means we're ready to call ir_raw_event_handle
654
if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
655
nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
656
ir_raw_event_handle(nvt->rdev);
662
nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
663
ir_raw_event_handle(nvt->rdev);
665
nvt_dbg_verbose("%s done", __func__);
668
static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
670
nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
673
nvt_clear_cir_fifo(nvt);
674
ir_raw_event_reset(nvt->rdev);
677
/* copy data from hardware rx fifo into driver buffer */
678
static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
683
bool overrun = false;
686
/* Get count of how many bytes to read from RX FIFO */
687
fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
688
/* if we get 0xff, probably means the logical dev is disabled */
689
if (fifocount == 0xff)
691
/* watch out for a fifo overrun condition */
692
else if (fifocount > RX_BUF_LEN) {
694
fifocount = RX_BUF_LEN;
697
nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
699
spin_lock_irqsave(&nvt->nvt_lock, flags);
703
/* This should never happen, but lets check anyway... */
704
if (b_idx + fifocount > RX_BUF_LEN) {
705
nvt_process_rx_ir_data(nvt);
709
/* Read fifocount bytes from CIR Sample RX FIFO register */
710
for (i = 0; i < fifocount; i++) {
711
val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
712
nvt->buf[b_idx + i] = val;
715
nvt->pkts += fifocount;
716
nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
718
nvt_process_rx_ir_data(nvt);
721
nvt_handle_rx_fifo_overrun(nvt);
723
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
726
static void nvt_cir_log_irqs(u8 status, u8 iren)
728
nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
730
status & CIR_IRSTS_RDR ? " RDR" : "",
731
status & CIR_IRSTS_RTR ? " RTR" : "",
732
status & CIR_IRSTS_PE ? " PE" : "",
733
status & CIR_IRSTS_RFO ? " RFO" : "",
734
status & CIR_IRSTS_TE ? " TE" : "",
735
status & CIR_IRSTS_TTR ? " TTR" : "",
736
status & CIR_IRSTS_TFU ? " TFU" : "",
737
status & CIR_IRSTS_GH ? " GH" : "",
738
status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
739
CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
740
CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
743
static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
749
spin_lock_irqsave(&nvt->tx.lock, flags);
750
tx_state = nvt->tx.tx_state;
751
spin_unlock_irqrestore(&nvt->tx.lock, flags);
753
tx_inactive = (tx_state == ST_TX_NONE);
758
/* interrupt service routine for incoming and outgoing CIR data */
759
static irqreturn_t nvt_cir_isr(int irq, void *data)
761
struct nvt_dev *nvt = data;
762
u8 status, iren, cur_state;
765
nvt_dbg_verbose("%s firing", __func__);
768
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
769
nvt_efm_disable(nvt);
772
* Get IR Status register contents. Write 1 to ack/clear
774
* bit: reg name - description
775
* 7: CIR_IRSTS_RDR - RX Data Ready
776
* 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
777
* 5: CIR_IRSTS_PE - Packet End
778
* 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
779
* 3: CIR_IRSTS_TE - TX FIFO Empty
780
* 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
781
* 1: CIR_IRSTS_TFU - TX FIFO Underrun
782
* 0: CIR_IRSTS_GH - Min Length Detected
784
status = nvt_cir_reg_read(nvt, CIR_IRSTS);
786
nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
787
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
788
return IRQ_RETVAL(IRQ_NONE);
791
/* ack/clear all irq flags we've got */
792
nvt_cir_reg_write(nvt, status, CIR_IRSTS);
793
nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
795
/* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
796
iren = nvt_cir_reg_read(nvt, CIR_IREN);
798
nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
799
return IRQ_RETVAL(IRQ_NONE);
803
nvt_cir_log_irqs(status, iren);
805
if (status & CIR_IRSTS_RTR) {
806
/* FIXME: add code for study/learn mode */
807
/* We only do rx if not tx'ing */
808
if (nvt_cir_tx_inactive(nvt))
809
nvt_get_rx_ir_data(nvt);
812
if (status & CIR_IRSTS_PE) {
813
if (nvt_cir_tx_inactive(nvt))
814
nvt_get_rx_ir_data(nvt);
816
spin_lock_irqsave(&nvt->nvt_lock, flags);
818
cur_state = nvt->study_state;
820
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
822
if (cur_state == ST_STUDY_NONE)
823
nvt_clear_cir_fifo(nvt);
826
if (status & CIR_IRSTS_TE)
827
nvt_clear_tx_fifo(nvt);
829
if (status & CIR_IRSTS_TTR) {
830
unsigned int pos, count;
833
spin_lock_irqsave(&nvt->tx.lock, flags);
835
pos = nvt->tx.cur_buf_num;
836
count = nvt->tx.buf_count;
838
/* Write data into the hardware tx fifo while pos < count */
840
nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
841
nvt->tx.cur_buf_num++;
842
/* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
844
tmp = nvt_cir_reg_read(nvt, CIR_IREN);
845
nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
848
spin_unlock_irqrestore(&nvt->tx.lock, flags);
852
if (status & CIR_IRSTS_TFU) {
853
spin_lock_irqsave(&nvt->tx.lock, flags);
854
if (nvt->tx.tx_state == ST_TX_REPLY) {
855
nvt->tx.tx_state = ST_TX_REQUEST;
856
wake_up(&nvt->tx.queue);
858
spin_unlock_irqrestore(&nvt->tx.lock, flags);
861
nvt_dbg_verbose("%s done", __func__);
862
return IRQ_RETVAL(IRQ_HANDLED);
865
/* Interrupt service routine for CIR Wake */
866
static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
868
u8 status, iren, val;
869
struct nvt_dev *nvt = data;
872
nvt_dbg_wake("%s firing", __func__);
874
status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
876
return IRQ_RETVAL(IRQ_NONE);
878
if (status & CIR_WAKE_IRSTS_IR_PENDING)
879
nvt_clear_cir_wake_fifo(nvt);
881
nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
882
nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
884
/* Interrupt may be shared with CIR, bail if Wake not enabled */
885
iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
887
nvt_dbg_wake("%s exiting, wake not enabled", __func__);
888
return IRQ_RETVAL(IRQ_HANDLED);
891
if ((status & CIR_WAKE_IRSTS_PE) &&
892
(nvt->wake_state == ST_WAKE_START)) {
893
while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
894
val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
895
nvt_dbg("setting wake up key: 0x%x", val);
898
nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
899
spin_lock_irqsave(&nvt->nvt_lock, flags);
900
nvt->wake_state = ST_WAKE_FINISH;
901
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
904
nvt_dbg_wake("%s done", __func__);
905
return IRQ_RETVAL(IRQ_HANDLED);
908
static void nvt_enable_cir(struct nvt_dev *nvt)
910
/* set function enable flags */
911
nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
912
CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
917
/* enable the CIR logical device */
918
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
919
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
921
nvt_efm_disable(nvt);
923
/* clear all pending interrupts */
924
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
926
/* enable interrupts */
927
nvt_set_cir_iren(nvt);
930
static void nvt_disable_cir(struct nvt_dev *nvt)
932
/* disable CIR interrupts */
933
nvt_cir_reg_write(nvt, 0, CIR_IREN);
935
/* clear any and all pending interrupts */
936
nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
938
/* clear all function enable flags */
939
nvt_cir_reg_write(nvt, 0, CIR_IRCON);
941
/* clear hardware rx and tx fifos */
942
nvt_clear_cir_fifo(nvt);
943
nvt_clear_tx_fifo(nvt);
947
/* disable the CIR logical device */
948
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
949
nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
951
nvt_efm_disable(nvt);
954
static int nvt_open(struct rc_dev *dev)
956
struct nvt_dev *nvt = dev->priv;
959
spin_lock_irqsave(&nvt->nvt_lock, flags);
961
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
966
static void nvt_close(struct rc_dev *dev)
968
struct nvt_dev *nvt = dev->priv;
971
spin_lock_irqsave(&nvt->nvt_lock, flags);
972
nvt_disable_cir(nvt);
973
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
976
/* Allocate memory, probe hardware, and initialize everything */
977
static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
983
nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
987
/* input device for IR remote (and tx) */
988
rdev = rc_allocate_device();
993
/* validate pnp resources */
994
if (!pnp_port_valid(pdev, 0) ||
995
pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
996
dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1000
if (!pnp_irq_valid(pdev, 0)) {
1001
dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1005
if (!pnp_port_valid(pdev, 1) ||
1006
pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1007
dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1011
nvt->cir_addr = pnp_port_start(pdev, 0);
1012
nvt->cir_irq = pnp_irq(pdev, 0);
1014
nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1015
/* irq is always shared between cir and cir wake */
1016
nvt->cir_wake_irq = nvt->cir_irq;
1018
nvt->cr_efir = CR_EFIR;
1019
nvt->cr_efdr = CR_EFDR;
1021
spin_lock_init(&nvt->nvt_lock);
1022
spin_lock_init(&nvt->tx.lock);
1025
/* now claim resources */
1026
if (!request_region(nvt->cir_addr,
1027
CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1030
if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1031
NVT_DRIVER_NAME, (void *)nvt))
1034
if (!request_region(nvt->cir_wake_addr,
1035
CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1038
if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1039
NVT_DRIVER_NAME, (void *)nvt))
1042
pnp_set_drvdata(pdev, nvt);
1045
init_waitqueue_head(&nvt->tx.queue);
1047
ret = nvt_hw_detect(nvt);
1051
/* Initialize CIR & CIR Wake Logical Devices */
1052
nvt_efm_enable(nvt);
1053
nvt_cir_ldev_init(nvt);
1054
nvt_cir_wake_ldev_init(nvt);
1055
nvt_efm_disable(nvt);
1057
/* Initialize CIR & CIR Wake Config Registers */
1058
nvt_cir_regs_init(nvt);
1059
nvt_cir_wake_regs_init(nvt);
1061
/* Set up the rc device */
1063
rdev->driver_type = RC_DRIVER_IR_RAW;
1064
rdev->allowed_protos = RC_TYPE_ALL;
1065
rdev->open = nvt_open;
1066
rdev->close = nvt_close;
1067
rdev->tx_ir = nvt_tx_ir;
1068
rdev->s_tx_carrier = nvt_set_tx_carrier;
1069
rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1070
rdev->input_phys = "nuvoton/cir0";
1071
rdev->input_id.bustype = BUS_HOST;
1072
rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1073
rdev->input_id.product = nvt->chip_major;
1074
rdev->input_id.version = nvt->chip_minor;
1075
rdev->dev.parent = &pdev->dev;
1076
rdev->driver_name = NVT_DRIVER_NAME;
1077
rdev->map_name = RC_MAP_RC6_MCE;
1078
rdev->timeout = MS_TO_NS(100);
1079
/* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1080
rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1082
rdev->min_timeout = XYZ;
1083
rdev->max_timeout = XYZ;
1085
rdev->tx_resolution = XYZ;
1088
ret = rc_register_device(rdev);
1092
device_init_wakeup(&pdev->dev, true);
1094
nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1097
cir_wake_dump_regs(nvt);
1104
free_irq(nvt->cir_irq, nvt);
1106
release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1108
if (nvt->cir_wake_irq)
1109
free_irq(nvt->cir_wake_irq, nvt);
1110
if (nvt->cir_wake_addr)
1111
release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1113
rc_free_device(rdev);
1119
static void __devexit nvt_remove(struct pnp_dev *pdev)
1121
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1122
unsigned long flags;
1124
spin_lock_irqsave(&nvt->nvt_lock, flags);
1126
nvt_cir_reg_write(nvt, 0, CIR_IREN);
1127
nvt_disable_cir(nvt);
1128
/* enable CIR Wake (for IR power-on) */
1129
nvt_enable_wake(nvt);
1130
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1132
/* free resources */
1133
free_irq(nvt->cir_irq, nvt);
1134
free_irq(nvt->cir_wake_irq, nvt);
1135
release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1136
release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1138
rc_unregister_device(nvt->rdev);
1143
static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1145
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1146
unsigned long flags;
1148
nvt_dbg("%s called", __func__);
1150
/* zero out misc state tracking */
1151
spin_lock_irqsave(&nvt->nvt_lock, flags);
1152
nvt->study_state = ST_STUDY_NONE;
1153
nvt->wake_state = ST_WAKE_NONE;
1154
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1156
spin_lock_irqsave(&nvt->tx.lock, flags);
1157
nvt->tx.tx_state = ST_TX_NONE;
1158
spin_unlock_irqrestore(&nvt->tx.lock, flags);
1160
/* disable all CIR interrupts */
1161
nvt_cir_reg_write(nvt, 0, CIR_IREN);
1163
nvt_efm_enable(nvt);
1165
/* disable cir logical dev */
1166
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1167
nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1169
nvt_efm_disable(nvt);
1171
/* make sure wake is enabled */
1172
nvt_enable_wake(nvt);
1177
static int nvt_resume(struct pnp_dev *pdev)
1180
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1182
nvt_dbg("%s called", __func__);
1184
/* open interrupt */
1185
nvt_set_cir_iren(nvt);
1187
/* Enable CIR logical device */
1188
nvt_efm_enable(nvt);
1189
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1190
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1192
nvt_efm_disable(nvt);
1194
nvt_cir_regs_init(nvt);
1195
nvt_cir_wake_regs_init(nvt);
1200
static void nvt_shutdown(struct pnp_dev *pdev)
1202
struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1203
nvt_enable_wake(nvt);
1206
static const struct pnp_device_id nvt_ids[] = {
1207
{ "WEC0530", 0 }, /* CIR */
1208
{ "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1212
static struct pnp_driver nvt_driver = {
1213
.name = NVT_DRIVER_NAME,
1214
.id_table = nvt_ids,
1215
.flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1217
.remove = __devexit_p(nvt_remove),
1218
.suspend = nvt_suspend,
1219
.resume = nvt_resume,
1220
.shutdown = nvt_shutdown,
1225
return pnp_register_driver(&nvt_driver);
1230
pnp_unregister_driver(&nvt_driver);
1233
module_param(debug, int, S_IRUGO | S_IWUSR);
1234
MODULE_PARM_DESC(debug, "Enable debugging output");
1236
MODULE_DEVICE_TABLE(pnp, nvt_ids);
1237
MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1239
MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1240
MODULE_LICENSE("GPL");
1242
module_init(nvt_init);
1243
module_exit(nvt_exit);