2
* linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
4
* Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
6
* Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
9
* Based on code written by:
10
* Sven Luther, <luther@dpt-info.u-strasbg.fr>
11
* Alan Hourihane, <alanh@fairlite.demon.co.uk>
12
* Russell King, <rmk@arm.linux.org.uk>
13
* Based on linux/drivers/video/skeletonfb.c:
14
* Copyright (C) 1997 Geert Uytterhoeven
15
* Based on linux/driver/video/pm2fb.c:
16
* Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
17
* Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
19
* This file is subject to the terms and conditions of the GNU General Public
20
* License. See the file COPYING in the main directory of this archive for
25
#include <linux/module.h>
26
#include <linux/kernel.h>
27
#include <linux/errno.h>
28
#include <linux/string.h>
30
#include <linux/slab.h>
31
#include <linux/delay.h>
33
#include <linux/init.h>
34
#include <linux/pci.h>
39
#include <video/pm3fb.h>
41
#if !defined(CONFIG_PCI)
42
#error "Only generic PCI cards supported."
45
#undef PM3FB_MASTER_DEBUG
46
#ifdef PM3FB_MASTER_DEBUG
47
#define DPRINTK(a, b...) \
48
printk(KERN_DEBUG "pm3fb: %s: " a, __func__ , ## b)
50
#define DPRINTK(a, b...)
53
#define PM3_PIXMAP_SIZE (2048 * 4)
58
static int hwcursor = 1;
59
static char *mode_option __devinitdata;
60
static int noaccel __devinitdata;
64
static int nomtrr __devinitdata;
68
* This structure defines the hardware state of the graphics card. Normally
69
* you place this in a header file in linux/include/video. This file usually
70
* also includes register information. That allows other driver subsystems
71
* and userland applications the ability to use the same header file to
72
* avoid duplicate work and easy porting of software.
75
unsigned char __iomem *v_regs;/* virtual address of p_regs */
76
u32 video; /* video flags before blanking */
77
u32 base; /* screen base in 128 bits unit */
83
* Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
84
* if we don't use modedb. If we do use modedb see pm3fb_init how to use it
85
* to get a fb_var_screeninfo. Otherwise define a default var as well.
87
static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
89
.type = FB_TYPE_PACKED_PIXELS,
90
.visual = FB_VISUAL_PSEUDOCOLOR,
94
.accel = FB_ACCEL_3DLABS_PERMEDIA3,
101
static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
103
return fb_readl(par->v_regs + off);
106
static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
108
fb_writel(v, par->v_regs + off);
111
static inline void PM3_WAIT(struct pm3_par *par, u32 n)
113
while (PM3_READ_REG(par, PM3InFIFOSpace) < n)
117
static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
120
PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
121
PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
123
PM3_WRITE_REG(par, PM3RD_IndexedData, v);
127
static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
128
unsigned char r, unsigned char g, unsigned char b)
131
PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
133
PM3_WRITE_REG(par, PM3RD_PaletteData, r);
135
PM3_WRITE_REG(par, PM3RD_PaletteData, g);
137
PM3_WRITE_REG(par, PM3RD_PaletteData, b);
141
static void pm3fb_clear_colormap(struct pm3_par *par,
142
unsigned char r, unsigned char g, unsigned char b)
146
for (i = 0; i < 256 ; i++)
147
pm3fb_set_color(par, i, r, g, b);
151
/* Calculating various clock parameters */
152
static void pm3fb_calculate_clock(unsigned long reqclock,
153
unsigned char *prescale,
154
unsigned char *feedback,
155
unsigned char *postscale)
162
for (f = 1; f < 256; f++) {
163
for (pre = 1; pre < 256; pre++) {
164
for (post = 0; post < 5; post++) {
165
freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
166
currerr = (reqclock > freq)
169
if (currerr < freqerr) {
180
static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
182
if (var->bits_per_pixel == 16)
183
return var->red.length + var->green.length
186
return var->bits_per_pixel;
189
static inline int pm3fb_shift_bpp(unsigned bpp, int v)
199
DPRINTK("Unsupported depth %u\n", bpp);
204
static int pm3fb_sync(struct fb_info *info)
206
struct pm3_par *par = info->par;
209
PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
210
PM3_WRITE_REG(par, PM3Sync, 0);
213
while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0)
215
} while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
220
static void pm3fb_init_engine(struct fb_info *info)
222
struct pm3_par *par = info->par;
223
const u32 width = (info->var.xres_virtual + 7) & ~7;
226
PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
227
PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
228
PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
229
PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
230
PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
231
PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
232
PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
233
PM3_WRITE_REG(par, PM3GIDMode, 0x0);
234
PM3_WRITE_REG(par, PM3DepthMode, 0x0);
235
PM3_WRITE_REG(par, PM3StencilMode, 0x0);
236
PM3_WRITE_REG(par, PM3StencilData, 0x0);
237
PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
238
PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
239
PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
240
PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
241
PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
242
PM3_WRITE_REG(par, PM3LUTMode, 0x0);
243
PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
244
PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
245
PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
246
PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
247
PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
248
PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
249
PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
250
PM3_WRITE_REG(par, PM3FogMode, 0x0);
251
PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
252
PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
253
PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
254
PM3_WRITE_REG(par, PM3YUVMode, 0x0);
255
PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
256
PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
257
PM3_WRITE_REG(par, PM3DitherMode, 0x0);
258
PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
259
PM3_WRITE_REG(par, PM3RouterMode, 0x0);
260
PM3_WRITE_REG(par, PM3Window, 0x0);
262
PM3_WRITE_REG(par, PM3Config2D, 0x0);
264
PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
266
PM3_WRITE_REG(par, PM3XBias, 0x0);
267
PM3_WRITE_REG(par, PM3YBias, 0x0);
268
PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
270
PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
272
PM3_WRITE_REG(par, PM3FBDestReadEnables,
273
PM3FBDestReadEnables_E(0xff) |
274
PM3FBDestReadEnables_R(0xff) |
275
PM3FBDestReadEnables_ReferenceAlpha(0xff));
276
PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
277
PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
278
PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
279
PM3FBDestReadBufferWidth_Width(width));
281
PM3_WRITE_REG(par, PM3FBDestReadMode,
282
PM3FBDestReadMode_ReadEnable |
283
PM3FBDestReadMode_Enable0);
284
PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
285
PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
286
PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
287
PM3FBSourceReadBufferWidth_Width(width));
288
PM3_WRITE_REG(par, PM3FBSourceReadMode,
289
PM3FBSourceReadMode_Blocking |
290
PM3FBSourceReadMode_ReadEnable);
294
/* invert bits in bitmask */
295
unsigned long rm = 1 | (3 << 7);
296
switch (info->var.bits_per_pixel) {
298
PM3_WRITE_REG(par, PM3PixelSize,
299
PM3PixelSize_GLOBAL_8BIT);
305
PM3_WRITE_REG(par, PM3PixelSize,
306
PM3PixelSize_GLOBAL_16BIT);
312
PM3_WRITE_REG(par, PM3PixelSize,
313
PM3PixelSize_GLOBAL_32BIT);
316
DPRINTK(1, "Unsupported depth %d\n",
317
info->var.bits_per_pixel);
320
PM3_WRITE_REG(par, PM3RasterizerMode, rm);
324
PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
325
PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
326
PM3_WRITE_REG(par, PM3FBWriteMode,
327
PM3FBWriteMode_WriteEnable |
328
PM3FBWriteMode_OpaqueSpan |
329
PM3FBWriteMode_Enable0);
330
PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
331
PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
332
PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
333
PM3FBWriteBufferWidth_Width(width));
335
PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
337
/* size in lines of FB */
338
unsigned long sofb = info->screen_size /
339
info->fix.line_length;
341
PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
343
PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
345
switch (info->var.bits_per_pixel) {
347
PM3_WRITE_REG(par, PM3DitherMode,
348
(1 << 10) | (2 << 3));
351
PM3_WRITE_REG(par, PM3DitherMode,
352
(1 << 10) | (1 << 3));
355
PM3_WRITE_REG(par, PM3DitherMode,
356
(1 << 10) | (0 << 3));
359
DPRINTK(1, "Unsupported depth %d\n",
360
info->current_par->depth);
365
PM3_WRITE_REG(par, PM3dXDom, 0x0);
366
PM3_WRITE_REG(par, PM3dXSub, 0x0);
367
PM3_WRITE_REG(par, PM3dY, 1 << 16);
368
PM3_WRITE_REG(par, PM3StartXDom, 0x0);
369
PM3_WRITE_REG(par, PM3StartXSub, 0x0);
370
PM3_WRITE_REG(par, PM3StartY, 0x0);
371
PM3_WRITE_REG(par, PM3Count, 0x0);
373
/* Disable LocalBuffer. better safe than sorry */
374
PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
375
PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
376
PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
377
PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
382
static void pm3fb_fillrect(struct fb_info *info,
383
const struct fb_fillrect *region)
385
struct pm3_par *par = info->par;
386
struct fb_fillrect modded;
389
u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
390
((u32 *)info->pseudo_palette)[region->color] : region->color;
392
if (info->state != FBINFO_STATE_RUNNING)
394
if (info->flags & FBINFO_HWACCEL_DISABLED) {
395
cfb_fillrect(info, region);
398
if (region->rop == ROP_COPY )
399
rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */
401
rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */
402
PM3Config2D_FBDestReadEnable;
404
vxres = info->var.xres_virtual;
405
vyres = info->var.yres_virtual;
407
memcpy(&modded, region, sizeof(struct fb_fillrect));
409
if (!modded.width || !modded.height ||
410
modded.dx >= vxres || modded.dy >= vyres)
413
if (modded.dx + modded.width > vxres)
414
modded.width = vxres - modded.dx;
415
if (modded.dy + modded.height > vyres)
416
modded.height = vyres - modded.dy;
418
if (info->var.bits_per_pixel == 8)
420
if (info->var.bits_per_pixel <= 16)
421
color |= color << 16;
424
/* ROP Ox3 is GXcopy */
425
PM3_WRITE_REG(par, PM3Config2D,
426
PM3Config2D_UseConstantSource |
427
PM3Config2D_ForegroundROPEnable |
429
PM3Config2D_FBWriteEnable);
431
PM3_WRITE_REG(par, PM3ForegroundColor, color);
433
PM3_WRITE_REG(par, PM3RectanglePosition,
434
PM3RectanglePosition_XOffset(modded.dx) |
435
PM3RectanglePosition_YOffset(modded.dy));
437
PM3_WRITE_REG(par, PM3Render2D,
438
PM3Render2D_XPositive |
439
PM3Render2D_YPositive |
440
PM3Render2D_Operation_Normal |
441
PM3Render2D_SpanOperation |
442
PM3Render2D_Width(modded.width) |
443
PM3Render2D_Height(modded.height));
446
static void pm3fb_copyarea(struct fb_info *info,
447
const struct fb_copyarea *area)
449
struct pm3_par *par = info->par;
450
struct fb_copyarea modded;
452
int x_align, o_x, o_y;
454
if (info->state != FBINFO_STATE_RUNNING)
456
if (info->flags & FBINFO_HWACCEL_DISABLED) {
457
cfb_copyarea(info, area);
461
memcpy(&modded, area, sizeof(struct fb_copyarea));
463
vxres = info->var.xres_virtual;
464
vyres = info->var.yres_virtual;
466
if (!modded.width || !modded.height ||
467
modded.sx >= vxres || modded.sy >= vyres ||
468
modded.dx >= vxres || modded.dy >= vyres)
471
if (modded.sx + modded.width > vxres)
472
modded.width = vxres - modded.sx;
473
if (modded.dx + modded.width > vxres)
474
modded.width = vxres - modded.dx;
475
if (modded.sy + modded.height > vyres)
476
modded.height = vyres - modded.sy;
477
if (modded.dy + modded.height > vyres)
478
modded.height = vyres - modded.dy;
480
o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */
481
o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */
483
x_align = (modded.sx & 0x1f);
487
PM3_WRITE_REG(par, PM3Config2D,
488
PM3Config2D_UserScissorEnable |
489
PM3Config2D_ForegroundROPEnable |
490
PM3Config2D_Blocking |
491
PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */
492
PM3Config2D_FBWriteEnable);
494
PM3_WRITE_REG(par, PM3ScissorMinXY,
495
((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
496
PM3_WRITE_REG(par, PM3ScissorMaxXY,
497
(((modded.dy + modded.height) & 0x0fff) << 16) |
498
((modded.dx + modded.width) & 0x0fff));
500
PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
501
PM3FBSourceReadBufferOffset_XOffset(o_x) |
502
PM3FBSourceReadBufferOffset_YOffset(o_y));
504
PM3_WRITE_REG(par, PM3RectanglePosition,
505
PM3RectanglePosition_XOffset(modded.dx - x_align) |
506
PM3RectanglePosition_YOffset(modded.dy));
508
PM3_WRITE_REG(par, PM3Render2D,
509
((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
510
((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
511
PM3Render2D_Operation_Normal |
512
PM3Render2D_SpanOperation |
513
PM3Render2D_FBSourceReadEnable |
514
PM3Render2D_Width(modded.width + x_align) |
515
PM3Render2D_Height(modded.height));
518
static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
520
struct pm3_par *par = info->par;
521
u32 height = image->height;
523
const u32 *src = (const u32 *)image->data;
525
if (info->state != FBINFO_STATE_RUNNING)
527
if (info->flags & FBINFO_HWACCEL_DISABLED) {
528
cfb_imageblit(info, image);
531
switch (info->fix.visual) {
532
case FB_VISUAL_PSEUDOCOLOR:
533
fgx = image->fg_color;
534
bgx = image->bg_color;
536
case FB_VISUAL_TRUECOLOR:
538
fgx = par->palette[image->fg_color];
539
bgx = par->palette[image->bg_color];
542
if (image->depth != 1) {
543
cfb_imageblit(info, image);
547
if (info->var.bits_per_pixel == 8) {
551
if (info->var.bits_per_pixel <= 16) {
558
PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
559
PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
561
/* ROP Ox3 is GXcopy */
562
PM3_WRITE_REG(par, PM3Config2D,
563
PM3Config2D_UserScissorEnable |
564
PM3Config2D_UseConstantSource |
565
PM3Config2D_ForegroundROPEnable |
566
PM3Config2D_ForegroundROP(0x3) |
567
PM3Config2D_OpaqueSpan |
568
PM3Config2D_FBWriteEnable);
569
PM3_WRITE_REG(par, PM3ScissorMinXY,
570
((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
571
PM3_WRITE_REG(par, PM3ScissorMaxXY,
572
(((image->dy + image->height) & 0x0fff) << 16) |
573
((image->dx + image->width) & 0x0fff));
574
PM3_WRITE_REG(par, PM3RectanglePosition,
575
PM3RectanglePosition_XOffset(image->dx) |
576
PM3RectanglePosition_YOffset(image->dy));
577
PM3_WRITE_REG(par, PM3Render2D,
578
PM3Render2D_XPositive |
579
PM3Render2D_YPositive |
580
PM3Render2D_Operation_SyncOnBitMask |
581
PM3Render2D_SpanOperation |
582
PM3Render2D_Width(image->width) |
583
PM3Render2D_Height(image->height));
587
int width = ((image->width + 7) >> 3)
588
+ info->pixmap.scan_align - 1;
591
while (width >= PM3_FIFO_SIZE) {
592
int i = PM3_FIFO_SIZE - 1;
594
PM3_WAIT(par, PM3_FIFO_SIZE);
596
PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
599
width -= PM3_FIFO_SIZE - 1;
602
PM3_WAIT(par, width + 1);
604
PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
609
/* end of acceleration functions */
612
* Hardware Cursor support.
614
static const u8 cursor_bits_lookup[16] = {
615
0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
616
0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
619
static int pm3fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
621
struct pm3_par *par = info->par;
625
return -EINVAL; /* just to force soft_cursor() call */
627
/* Too large of a cursor or wrong bpp :-( */
628
if (cursor->image.width > 64 ||
629
cursor->image.height > 64 ||
630
cursor->image.depth > 1)
633
mode = PM3RD_CursorMode_TYPE_X;
635
mode |= PM3RD_CursorMode_CURSOR_ENABLE;
637
PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, mode);
640
* If the cursor is not be changed this means either we want the
641
* current cursor state (if enable is set) or we want to query what
642
* we can do with the cursor (if enable is not set)
647
if (cursor->set & FB_CUR_SETPOS) {
648
int x = cursor->image.dx - info->var.xoffset;
649
int y = cursor->image.dy - info->var.yoffset;
651
PM3_WRITE_DAC_REG(par, PM3RD_CursorXLow, x & 0xff);
652
PM3_WRITE_DAC_REG(par, PM3RD_CursorXHigh, (x >> 8) & 0xf);
653
PM3_WRITE_DAC_REG(par, PM3RD_CursorYLow, y & 0xff);
654
PM3_WRITE_DAC_REG(par, PM3RD_CursorYHigh, (y >> 8) & 0xf);
657
if (cursor->set & FB_CUR_SETHOT) {
658
PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotX,
659
cursor->hot.x & 0x3f);
660
PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotY,
661
cursor->hot.y & 0x3f);
664
if (cursor->set & FB_CUR_SETCMAP) {
665
u32 fg_idx = cursor->image.fg_color;
666
u32 bg_idx = cursor->image.bg_color;
667
struct fb_cmap cmap = info->cmap;
669
/* the X11 driver says one should use these color registers */
670
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(39),
671
cmap.red[fg_idx] >> 8 );
672
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(40),
673
cmap.green[fg_idx] >> 8 );
674
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(41),
675
cmap.blue[fg_idx] >> 8 );
677
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(42),
678
cmap.red[bg_idx] >> 8 );
679
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(43),
680
cmap.green[bg_idx] >> 8 );
681
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(44),
682
cmap.blue[bg_idx] >> 8 );
685
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
686
u8 *bitmap = (u8 *)cursor->image.data;
687
u8 *mask = (u8 *)cursor->mask;
689
int pos = PM3RD_CursorPattern(0);
691
for (i = 0; i < cursor->image.height; i++) {
692
int j = (cursor->image.width + 7) >> 3;
696
u8 data = *bitmap ^ *mask;
698
if (cursor->rop == ROP_COPY)
699
data = *mask & *bitmap;
700
/* Upper 4 bits of bitmap data */
701
PM3_WRITE_DAC_REG(par, pos++,
702
cursor_bits_lookup[data >> 4] |
703
(cursor_bits_lookup[*mask >> 4] << 1));
704
/* Lower 4 bits of bitmap */
705
PM3_WRITE_DAC_REG(par, pos++,
706
cursor_bits_lookup[data & 0xf] |
707
(cursor_bits_lookup[*mask & 0xf] << 1));
712
PM3_WRITE_DAC_REG(par, pos++, 0);
713
PM3_WRITE_DAC_REG(par, pos++, 0);
716
while (pos < PM3RD_CursorPattern(1024))
717
PM3_WRITE_DAC_REG(par, pos++, 0);
722
/* write the mode to registers */
723
static void pm3fb_write_mode(struct fb_info *info)
725
struct pm3_par *par = info->par;
726
char tempsync = 0x00;
727
char tempmisc = 0x00;
728
const u32 hsstart = info->var.right_margin;
729
const u32 hsend = hsstart + info->var.hsync_len;
730
const u32 hbend = hsend + info->var.left_margin;
731
const u32 xres = (info->var.xres + 31) & ~31;
732
const u32 htotal = xres + hbend;
733
const u32 vsstart = info->var.lower_margin;
734
const u32 vsend = vsstart + info->var.vsync_len;
735
const u32 vbend = vsend + info->var.upper_margin;
736
const u32 vtotal = info->var.yres + vbend;
737
const u32 width = (info->var.xres_virtual + 7) & ~7;
738
const unsigned bpp = info->var.bits_per_pixel;
741
PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
742
PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
743
PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
744
PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
746
PM3_WRITE_REG(par, PM3HTotal,
747
pm3fb_shift_bpp(bpp, htotal - 1));
748
PM3_WRITE_REG(par, PM3HsEnd,
749
pm3fb_shift_bpp(bpp, hsend));
750
PM3_WRITE_REG(par, PM3HsStart,
751
pm3fb_shift_bpp(bpp, hsstart));
752
PM3_WRITE_REG(par, PM3HbEnd,
753
pm3fb_shift_bpp(bpp, hbend));
754
PM3_WRITE_REG(par, PM3HgEnd,
755
pm3fb_shift_bpp(bpp, hbend));
756
PM3_WRITE_REG(par, PM3ScreenStride,
757
pm3fb_shift_bpp(bpp, width));
758
PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
759
PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
760
PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
761
PM3_WRITE_REG(par, PM3VbEnd, vbend);
765
PM3_WRITE_REG(par, PM3ByAperture1Mode,
766
PM3ByApertureMode_PIXELSIZE_8BIT);
767
PM3_WRITE_REG(par, PM3ByAperture2Mode,
768
PM3ByApertureMode_PIXELSIZE_8BIT);
773
PM3_WRITE_REG(par, PM3ByAperture1Mode,
774
PM3ByApertureMode_PIXELSIZE_16BIT);
775
PM3_WRITE_REG(par, PM3ByAperture2Mode,
776
PM3ByApertureMode_PIXELSIZE_16BIT);
778
PM3_WRITE_REG(par, PM3ByAperture1Mode,
779
PM3ByApertureMode_PIXELSIZE_16BIT |
780
PM3ByApertureMode_BYTESWAP_BADC);
781
PM3_WRITE_REG(par, PM3ByAperture2Mode,
782
PM3ByApertureMode_PIXELSIZE_16BIT |
783
PM3ByApertureMode_BYTESWAP_BADC);
784
#endif /* ! __BIG_ENDIAN */
789
PM3_WRITE_REG(par, PM3ByAperture1Mode,
790
PM3ByApertureMode_PIXELSIZE_32BIT);
791
PM3_WRITE_REG(par, PM3ByAperture2Mode,
792
PM3ByApertureMode_PIXELSIZE_32BIT);
794
PM3_WRITE_REG(par, PM3ByAperture1Mode,
795
PM3ByApertureMode_PIXELSIZE_32BIT |
796
PM3ByApertureMode_BYTESWAP_DCBA);
797
PM3_WRITE_REG(par, PM3ByAperture2Mode,
798
PM3ByApertureMode_PIXELSIZE_32BIT |
799
PM3ByApertureMode_BYTESWAP_DCBA);
800
#endif /* ! __BIG_ENDIAN */
804
DPRINTK("Unsupported depth %d\n", bpp);
809
* Oxygen VX1 - it appears that setting PM3VideoControl and
810
* then PM3RD_SyncControl to the same SYNC settings undoes
811
* any net change - they seem to xor together. Only set the
812
* sync options in PM3RD_SyncControl. --rmk
815
unsigned int video = par->video;
817
video &= ~(PM3VideoControl_HSYNC_MASK |
818
PM3VideoControl_VSYNC_MASK);
819
video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
820
PM3VideoControl_VSYNC_ACTIVE_HIGH;
821
PM3_WRITE_REG(par, PM3VideoControl, video);
823
PM3_WRITE_REG(par, PM3VClkCtl,
824
(PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
825
PM3_WRITE_REG(par, PM3ScreenBase, par->base);
826
PM3_WRITE_REG(par, PM3ChipConfig,
827
(PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
831
unsigned char uninitialized_var(m); /* ClkPreScale */
832
unsigned char uninitialized_var(n); /* ClkFeedBackScale */
833
unsigned char uninitialized_var(p); /* ClkPostScale */
834
unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
836
(void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
838
DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
839
pixclock, (int) m, (int) n, (int) p);
841
PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
842
PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
843
PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
846
PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
849
PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
851
if ((par->video & PM3VideoControl_HSYNC_MASK) ==
852
PM3VideoControl_HSYNC_ACTIVE_HIGH)
853
tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
854
if ((par->video & PM3VideoControl_VSYNC_MASK) ==
855
PM3VideoControl_VSYNC_ACTIVE_HIGH)
856
tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
858
PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
859
DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
861
PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
863
switch (pm3fb_depth(&info->var)) {
865
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
866
PM3RD_PixelSize_8_BIT_PIXELS);
867
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
868
PM3RD_ColorFormat_CI8_COLOR |
869
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
870
tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
873
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
874
PM3RD_PixelSize_16_BIT_PIXELS);
875
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
876
PM3RD_ColorFormat_4444_COLOR |
877
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
878
PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
879
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
880
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
883
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
884
PM3RD_PixelSize_16_BIT_PIXELS);
885
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
886
PM3RD_ColorFormat_5551_FRONT_COLOR |
887
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
888
PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
889
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
890
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
893
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
894
PM3RD_PixelSize_16_BIT_PIXELS);
895
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
896
PM3RD_ColorFormat_565_FRONT_COLOR |
897
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
898
PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
899
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
900
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
903
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
904
PM3RD_PixelSize_32_BIT_PIXELS);
905
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
906
PM3RD_ColorFormat_8888_COLOR |
907
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
908
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
909
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
912
PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
916
* hardware independent functions
918
static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
921
unsigned bpp = var->red.length + var->green.length
922
+ var->blue.length + var->transp.length;
924
if (bpp != var->bits_per_pixel) {
925
/* set predefined mode for bits_per_pixel settings */
927
switch (var->bits_per_pixel) {
930
var->green.length = 8;
931
var->blue.length = 8;
933
var->green.offset = 0;
934
var->blue.offset = 0;
935
var->transp.offset = 0;
936
var->transp.length = 0;
940
var->blue.length = 5;
941
var->green.length = 6;
942
var->transp.length = 0;
946
var->green.length = 8;
947
var->blue.length = 8;
948
var->transp.length = 8;
951
DPRINTK("depth not supported: %u\n",
952
var->bits_per_pixel);
956
/* it is assumed BGRA order */
957
if (var->bits_per_pixel > 8 ) {
958
var->blue.offset = 0;
959
var->green.offset = var->blue.length;
960
var->red.offset = var->green.offset + var->green.length;
961
var->transp.offset = var->red.offset + var->red.length;
966
if (var->xres != var->xres_virtual) {
967
DPRINTK("virtual x resolution != "
968
"physical x resolution not supported\n");
972
if (var->yres > var->yres_virtual) {
973
DPRINTK("virtual y resolution < "
974
"physical y resolution not possible\n");
979
DPRINTK("xoffset not supported\n");
983
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
984
DPRINTK("interlace not supported\n");
988
var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
989
lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
991
if (var->xres < 200 || var->xres > 2048) {
992
DPRINTK("width not supported: %u\n", var->xres);
996
if (var->yres < 200 || var->yres > 4095) {
997
DPRINTK("height not supported: %u\n", var->yres);
1001
if (lpitch * var->yres_virtual > info->fix.smem_len) {
1002
DPRINTK("no memory for screen (%ux%ux%u)\n",
1003
var->xres, var->yres_virtual, var->bits_per_pixel);
1007
if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
1008
DPRINTK("pixclock too high (%ldKHz)\n",
1009
PICOS2KHZ(var->pixclock));
1013
var->accel_flags = 0; /* Can't mmap if this is on */
1015
DPRINTK("Checking graphics mode at %dx%d depth %d\n",
1016
var->xres, var->yres, var->bits_per_pixel);
1020
static int pm3fb_set_par(struct fb_info *info)
1022
struct pm3_par *par = info->par;
1023
const u32 xres = (info->var.xres + 31) & ~31;
1024
const unsigned bpp = info->var.bits_per_pixel;
1026
par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
1027
+ info->var.xoffset);
1030
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
1031
par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
1033
par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
1035
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
1036
par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
1038
par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
1040
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
1041
par->video |= PM3VideoControl_LINE_DOUBLE_ON;
1043
if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1044
par->video |= PM3VideoControl_ENABLE;
1046
DPRINTK("PM3Video disabled\n");
1050
par->video |= PM3VideoControl_PIXELSIZE_8BIT;
1053
par->video |= PM3VideoControl_PIXELSIZE_16BIT;
1056
par->video |= PM3VideoControl_PIXELSIZE_32BIT;
1059
DPRINTK("Unsupported depth\n");
1064
(bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1065
info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp;
1067
/* pm3fb_clear_memory(info, 0);*/
1068
pm3fb_clear_colormap(par, 0, 0, 0);
1069
PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
1070
pm3fb_init_engine(info);
1071
pm3fb_write_mode(info);
1075
static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1076
unsigned blue, unsigned transp,
1077
struct fb_info *info)
1079
struct pm3_par *par = info->par;
1081
if (regno >= 256) /* no. of hw registers */
1084
/* grayscale works only partially under directcolor */
1085
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
1086
if (info->var.grayscale)
1087
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1090
* var->{color}.offset contains start of bitfield
1091
* var->{color}.length contains length of bitfield
1092
* {hardwarespecific} contains width of DAC
1093
* pseudo_palette[X] is programmed to (X << red.offset) |
1094
* (X << green.offset) |
1095
* (X << blue.offset)
1096
* RAMDAC[X] is programmed to (red, green, blue)
1097
* color depth = SUM(var->{color}.length)
1100
* var->{color}.offset is 0
1101
* var->{color}.length contains width of DAC or the number
1102
* of unique colors available (color depth)
1103
* pseudo_palette is not used
1104
* RAMDAC[X] is programmed to (red, green, blue)
1105
* color depth = var->{color}.length
1109
* This is the point where the color is converted to something that
1110
* is acceptable by the hardware.
1112
#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
1113
red = CNVT_TOHW(red, info->var.red.length);
1114
green = CNVT_TOHW(green, info->var.green.length);
1115
blue = CNVT_TOHW(blue, info->var.blue.length);
1116
transp = CNVT_TOHW(transp, info->var.transp.length);
1119
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
1120
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1126
v = (red << info->var.red.offset) |
1127
(green << info->var.green.offset) |
1128
(blue << info->var.blue.offset) |
1129
(transp << info->var.transp.offset);
1131
switch (info->var.bits_per_pixel) {
1136
((u32 *)(info->pseudo_palette))[regno] = v;
1140
} else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
1141
pm3fb_set_color(par, regno, red, green, blue);
1146
static int pm3fb_pan_display(struct fb_var_screeninfo *var,
1147
struct fb_info *info)
1149
struct pm3_par *par = info->par;
1150
const u32 xres = (info->var.xres + 31) & ~31;
1152
par->base = pm3fb_shift_bpp(info->var.bits_per_pixel,
1153
(var->yoffset * xres)
1156
PM3_WRITE_REG(par, PM3ScreenBase, par->base);
1160
static int pm3fb_blank(int blank_mode, struct fb_info *info)
1162
struct pm3_par *par = info->par;
1163
u32 video = par->video;
1166
* Oxygen VX1 - it appears that setting PM3VideoControl and
1167
* then PM3RD_SyncControl to the same SYNC settings undoes
1168
* any net change - they seem to xor together. Only set the
1169
* sync options in PM3RD_SyncControl. --rmk
1171
video &= ~(PM3VideoControl_HSYNC_MASK |
1172
PM3VideoControl_VSYNC_MASK);
1173
video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1174
PM3VideoControl_VSYNC_ACTIVE_HIGH;
1176
switch (blank_mode) {
1177
case FB_BLANK_UNBLANK:
1178
video |= PM3VideoControl_ENABLE;
1180
case FB_BLANK_NORMAL:
1181
video &= ~PM3VideoControl_ENABLE;
1183
case FB_BLANK_HSYNC_SUSPEND:
1184
video &= ~(PM3VideoControl_HSYNC_MASK |
1185
PM3VideoControl_BLANK_ACTIVE_LOW);
1187
case FB_BLANK_VSYNC_SUSPEND:
1188
video &= ~(PM3VideoControl_VSYNC_MASK |
1189
PM3VideoControl_BLANK_ACTIVE_LOW);
1191
case FB_BLANK_POWERDOWN:
1192
video &= ~(PM3VideoControl_HSYNC_MASK |
1193
PM3VideoControl_VSYNC_MASK |
1194
PM3VideoControl_BLANK_ACTIVE_LOW);
1197
DPRINTK("Unsupported blanking %d\n", blank_mode);
1202
PM3_WRITE_REG(par, PM3VideoControl, video);
1207
* Frame buffer operations
1210
static struct fb_ops pm3fb_ops = {
1211
.owner = THIS_MODULE,
1212
.fb_check_var = pm3fb_check_var,
1213
.fb_set_par = pm3fb_set_par,
1214
.fb_setcolreg = pm3fb_setcolreg,
1215
.fb_pan_display = pm3fb_pan_display,
1216
.fb_fillrect = pm3fb_fillrect,
1217
.fb_copyarea = pm3fb_copyarea,
1218
.fb_imageblit = pm3fb_imageblit,
1219
.fb_blank = pm3fb_blank,
1220
.fb_sync = pm3fb_sync,
1221
.fb_cursor = pm3fb_cursor,
1224
/* ------------------------------------------------------------------------- */
1230
/* mmio register are already mapped when this function is called */
1231
/* the pm3fb_fix.smem_start is also set */
1232
static unsigned long __devinit pm3fb_size_memory(struct pm3_par *par)
1234
unsigned long memsize = 0;
1235
unsigned long tempBypass, i, temp1, temp2;
1236
unsigned char __iomem *screen_mem;
1238
pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
1239
/* Linear frame buffer - request region and map it. */
1240
if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1242
printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1246
ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1248
printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1249
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1253
/* TODO: card-specific stuff, *before* accessing *any* FB memory */
1254
/* For Appian Jeronimo 2000 board second head */
1256
tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1258
DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1261
PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1263
/* pm3 split up memory, replicates, and do a lot of
1264
* nasty stuff IMHO ;-)
1266
for (i = 0; i < 32; i++) {
1267
fb_writel(i * 0x00345678,
1268
(screen_mem + (i * 1048576)));
1270
temp1 = fb_readl((screen_mem + (i * 1048576)));
1272
/* Let's check for wrapover, write will fail at 16MB boundary */
1273
if (temp1 == (i * 0x00345678))
1279
DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1281
if (memsize + 1 == i) {
1282
for (i = 0; i < 32; i++) {
1283
/* Clear first 32MB ; 0 is 0, no need to byteswap */
1284
writel(0x0000000, (screen_mem + (i * 1048576)));
1288
for (i = 32; i < 64; i++) {
1289
fb_writel(i * 0x00345678,
1290
(screen_mem + (i * 1048576)));
1293
fb_readl((screen_mem + (i * 1048576)));
1295
fb_readl((screen_mem + ((i - 32) * 1048576)));
1296
/* different value, different RAM... */
1297
if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1303
DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1306
PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1308
iounmap(screen_mem);
1309
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1310
memsize = 1048576 * (memsize + 1);
1312
DPRINTK("Returning 0x%08lx bytes\n", memsize);
1317
static int __devinit pm3fb_probe(struct pci_dev *dev,
1318
const struct pci_device_id *ent)
1320
struct fb_info *info;
1321
struct pm3_par *par;
1322
struct device *device = &dev->dev; /* for pci drivers */
1324
int retval = -ENXIO;
1326
err = pci_enable_device(dev);
1328
printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1332
* Dynamically allocate info and par
1334
info = framebuffer_alloc(sizeof(struct pm3_par), device);
1341
* Here we set the screen_base to the virtual memory address
1342
* for the framebuffer.
1344
pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1345
pm3fb_fix.mmio_len = PM3_REGS_SIZE;
1346
#if defined(__BIG_ENDIAN)
1347
pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1348
DPRINTK("Adjusting register base for big-endian.\n");
1351
/* Registers - request region and map it. */
1352
if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1354
printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1355
goto err_exit_neither;
1358
ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1360
printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1362
release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1363
goto err_exit_neither;
1366
/* Linear frame buffer - request region and map it. */
1367
pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1368
pm3fb_fix.smem_len = pm3fb_size_memory(par);
1369
if (!pm3fb_fix.smem_len) {
1370
printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1373
if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1375
printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1379
ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1380
if (!info->screen_base) {
1381
printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1382
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1385
info->screen_size = pm3fb_fix.smem_len;
1389
par->mtrr_handle = mtrr_add(pm3fb_fix.smem_start,
1391
MTRR_TYPE_WRCOMB, 1);
1393
info->fbops = &pm3fb_ops;
1395
par->video = PM3_READ_REG(par, PM3VideoControl);
1397
info->fix = pm3fb_fix;
1398
info->pseudo_palette = par->palette;
1399
info->flags = FBINFO_DEFAULT |
1400
FBINFO_HWACCEL_XPAN |
1401
FBINFO_HWACCEL_YPAN |
1402
FBINFO_HWACCEL_COPYAREA |
1403
FBINFO_HWACCEL_IMAGEBLIT |
1404
FBINFO_HWACCEL_FILLRECT;
1407
printk(KERN_DEBUG "disabling acceleration\n");
1408
info->flags |= FBINFO_HWACCEL_DISABLED;
1410
info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
1411
if (!info->pixmap.addr) {
1413
goto err_exit_pixmap;
1415
info->pixmap.size = PM3_PIXMAP_SIZE;
1416
info->pixmap.buf_align = 4;
1417
info->pixmap.scan_align = 4;
1418
info->pixmap.access_align = 32;
1419
info->pixmap.flags = FB_PIXMAP_SYSTEM;
1422
* This should give a reasonable default video mode. The following is
1423
* done when we can set a video mode.
1426
mode_option = "640x480@60";
1428
retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1430
if (!retval || retval == 4) {
1435
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1441
* For drivers that can...
1443
pm3fb_check_var(&info->var, info);
1445
if (register_framebuffer(info) < 0) {
1449
printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1451
pci_set_drvdata(dev, info);
1455
fb_dealloc_cmap(&info->cmap);
1457
kfree(info->pixmap.addr);
1459
iounmap(info->screen_base);
1460
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1462
iounmap(par->v_regs);
1463
release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1465
framebuffer_release(info);
1472
static void __devexit pm3fb_remove(struct pci_dev *dev)
1474
struct fb_info *info = pci_get_drvdata(dev);
1477
struct fb_fix_screeninfo *fix = &info->fix;
1478
struct pm3_par *par = info->par;
1480
unregister_framebuffer(info);
1481
fb_dealloc_cmap(&info->cmap);
1484
if (par->mtrr_handle >= 0)
1485
mtrr_del(par->mtrr_handle, info->fix.smem_start,
1486
info->fix.smem_len);
1487
#endif /* CONFIG_MTRR */
1488
iounmap(info->screen_base);
1489
release_mem_region(fix->smem_start, fix->smem_len);
1490
iounmap(par->v_regs);
1491
release_mem_region(fix->mmio_start, fix->mmio_len);
1493
pci_set_drvdata(dev, NULL);
1494
kfree(info->pixmap.addr);
1495
framebuffer_release(info);
1499
static struct pci_device_id pm3fb_id_table[] = {
1500
{ PCI_VENDOR_ID_3DLABS, 0x0a,
1501
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1505
/* For PCI drivers */
1506
static struct pci_driver pm3fb_driver = {
1508
.id_table = pm3fb_id_table,
1509
.probe = pm3fb_probe,
1510
.remove = __devexit_p(pm3fb_remove),
1513
MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1521
* Only necessary if your driver takes special options,
1522
* otherwise we fall back on the generic fb_setup().
1524
static int __init pm3fb_setup(char *options)
1528
/* Parse user specified options (`video=pm3fb:') */
1529
if (!options || !*options)
1532
while ((this_opt = strsep(&options, ",")) != NULL) {
1535
else if (!strncmp(this_opt, "noaccel", 7))
1537
else if (!strncmp(this_opt, "hwcursor=", 9))
1538
hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1540
else if (!strncmp(this_opt, "nomtrr", 6))
1544
mode_option = this_opt;
1550
static int __init pm3fb_init(void)
1553
* For kernel boot options (in 'video=pm3fb:<options>' format)
1556
char *option = NULL;
1558
if (fb_get_options("pm3fb", &option))
1560
pm3fb_setup(option);
1563
return pci_register_driver(&pm3fb_driver);
1567
static void __exit pm3fb_exit(void)
1569
pci_unregister_driver(&pm3fb_driver);
1572
module_exit(pm3fb_exit);
1574
module_init(pm3fb_init);
1576
module_param(mode_option, charp, 0);
1577
MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1578
module_param(noaccel, bool, 0);
1579
MODULE_PARM_DESC(noaccel, "Disable acceleration");
1580
module_param(hwcursor, int, 0644);
1581
MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1582
"(1=enable, 0=disable, default=1)");
1584
module_param(nomtrr, bool, 0);
1585
MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1588
MODULE_DESCRIPTION("Permedia3 framebuffer device driver");
1589
MODULE_LICENSE("GPL");