4
* Copyright (C) 1999 Intel Corp.
5
* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6
* Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7
* Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8
* David Mosberger-Tang <davidm@hpl.hp.com>
9
* Copyright (C) 1999 VA Linux Systems
10
* Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12
* 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
13
* APIC code. In particular, we now have separate
14
* handlers for edge and level triggered
16
* 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17
* allocation PCI to vector mapping, shared PCI
19
* 00/10/27 D. Mosberger Document things a bit more to make them more
20
* understandable. Clean up much of the old
22
* 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
23
* and fixes for ACPI S5(SoftOff) support.
24
* 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
25
* 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
26
* vectors in iosapic_set_affinity(),
27
* initializations for /proc/irq/#/smp_affinity
28
* 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
29
* 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
30
* 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
31
* IOSAPIC mapping error
32
* 02/07/29 T. Kochi Allocate interrupt vectors dynamically
33
* 02/08/04 T. Kochi Cleaned up terminology (irq, global system
34
* interrupt, vector, etc.)
35
* 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
37
* 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
38
* Remove iosapic_address & gsi_base from
39
* external interfaces. Rationalize
40
* __init/__devinit attributes.
41
* 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
42
* Updated to work with irq migration necessary
46
* Here is what the interrupt logic between a PCI device and the kernel looks
49
* (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50
* INTD). The device is uniquely identified by its bus-, and slot-number
51
* (the function number does not matter here because all functions share
52
* the same interrupt lines).
54
* (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55
* controller. Multiple interrupt lines may have to share the same
56
* IOSAPIC pin (if they're level triggered and use the same polarity).
57
* Each interrupt line has a unique Global System Interrupt (GSI) number
58
* which can be calculated as the sum of the controller's base GSI number
59
* and the IOSAPIC pin number to which the line connects.
61
* (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62
* IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
65
* (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
66
* used as architecture-independent interrupt handling mechanism in Linux.
67
* As an IRQ is a number, we have to have
68
* IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69
* systems, we use one-to-one mapping between IA-64 vector and IRQ. A
70
* platform can implement platform_irq_to_vector(irq) and
71
* platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72
* Please see also arch/ia64/include/asm/hw_irq.h for those APIs.
74
* To sum up, there are three levels of mappings involved:
76
* PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
78
* Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79
* describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
80
* (isa_irq) is the only exception in this source code.
83
#include <linux/acpi.h>
84
#include <linux/init.h>
85
#include <linux/irq.h>
86
#include <linux/kernel.h>
87
#include <linux/list.h>
88
#include <linux/pci.h>
89
#include <linux/slab.h>
90
#include <linux/smp.h>
91
#include <linux/string.h>
92
#include <linux/bootmem.h>
94
#include <asm/delay.h>
95
#include <asm/hw_irq.h>
97
#include <asm/iosapic.h>
98
#include <asm/machvec.h>
99
#include <asm/processor.h>
100
#include <asm/ptrace.h>
101
#include <asm/system.h>
103
#undef DEBUG_INTERRUPT_ROUTING
105
#ifdef DEBUG_INTERRUPT_ROUTING
106
#define DBG(fmt...) printk(fmt)
111
static DEFINE_SPINLOCK(iosapic_lock);
114
* These tables map IA-64 vectors to the IOSAPIC pin that generates this
120
static struct iosapic {
121
char __iomem *addr; /* base address of IOSAPIC */
122
unsigned int gsi_base; /* GSI base */
123
unsigned short num_rte; /* # of RTEs on this IOSAPIC */
124
int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
126
unsigned short node; /* numa node association via pxm */
128
spinlock_t lock; /* lock for indirect reg access */
129
} iosapic_lists[NR_IOSAPICS];
131
struct iosapic_rte_info {
132
struct list_head rte_list; /* RTEs sharing the same vector */
133
char rte_index; /* IOSAPIC RTE index */
134
int refcnt; /* reference counter */
135
struct iosapic *iosapic;
136
} ____cacheline_aligned;
138
static struct iosapic_intr_info {
139
struct list_head rtes; /* RTEs using this vector (empty =>
140
* not an IOSAPIC interrupt) */
141
int count; /* # of registered RTEs */
142
u32 low32; /* current value of low word of
143
* Redirection table entry */
144
unsigned int dest; /* destination CPU physical ID */
145
unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
146
unsigned char polarity: 1; /* interrupt polarity
148
unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
149
} iosapic_intr_info[NR_IRQS];
151
static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
154
iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
158
spin_lock_irqsave(&iosapic->lock, flags);
159
__iosapic_write(iosapic->addr, reg, val);
160
spin_unlock_irqrestore(&iosapic->lock, flags);
164
* Find an IOSAPIC associated with a GSI
167
find_iosapic (unsigned int gsi)
171
for (i = 0; i < NR_IOSAPICS; i++) {
172
if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
173
iosapic_lists[i].num_rte)
180
static inline int __gsi_to_irq(unsigned int gsi)
183
struct iosapic_intr_info *info;
184
struct iosapic_rte_info *rte;
186
for (irq = 0; irq < NR_IRQS; irq++) {
187
info = &iosapic_intr_info[irq];
188
list_for_each_entry(rte, &info->rtes, rte_list)
189
if (rte->iosapic->gsi_base + rte->rte_index == gsi)
196
gsi_to_irq (unsigned int gsi)
201
spin_lock_irqsave(&iosapic_lock, flags);
202
irq = __gsi_to_irq(gsi);
203
spin_unlock_irqrestore(&iosapic_lock, flags);
207
static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
209
struct iosapic_rte_info *rte;
211
list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
212
if (rte->iosapic->gsi_base + rte->rte_index == gsi)
218
set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
220
unsigned long pol, trigger, dmode;
224
struct iosapic_rte_info *rte;
225
ia64_vector vector = irq_to_vector(irq);
227
DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
229
rte = find_rte(irq, gsi);
231
return; /* not an IOSAPIC interrupt */
233
rte_index = rte->rte_index;
234
pol = iosapic_intr_info[irq].polarity;
235
trigger = iosapic_intr_info[irq].trigger;
236
dmode = iosapic_intr_info[irq].dmode;
238
redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
241
set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
244
low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
245
(trigger << IOSAPIC_TRIGGER_SHIFT) |
246
(dmode << IOSAPIC_DELIVERY_SHIFT) |
247
((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
250
/* dest contains both id and eid */
251
high32 = (dest << IOSAPIC_DEST_SHIFT);
253
iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
254
iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
255
iosapic_intr_info[irq].low32 = low32;
256
iosapic_intr_info[irq].dest = dest;
260
nop (struct irq_data *data)
268
kexec_disable_iosapic(void)
270
struct iosapic_intr_info *info;
271
struct iosapic_rte_info *rte;
275
for (irq = 0; irq < NR_IRQS; irq++) {
276
info = &iosapic_intr_info[irq];
277
vec = irq_to_vector(irq);
278
list_for_each_entry(rte, &info->rtes,
280
iosapic_write(rte->iosapic,
281
IOSAPIC_RTE_LOW(rte->rte_index),
283
iosapic_eoi(rte->iosapic->addr, vec);
290
mask_irq (struct irq_data *data)
292
unsigned int irq = data->irq;
295
struct iosapic_rte_info *rte;
297
if (!iosapic_intr_info[irq].count)
298
return; /* not an IOSAPIC interrupt! */
300
/* set only the mask bit */
301
low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
302
list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
303
rte_index = rte->rte_index;
304
iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
309
unmask_irq (struct irq_data *data)
311
unsigned int irq = data->irq;
314
struct iosapic_rte_info *rte;
316
if (!iosapic_intr_info[irq].count)
317
return; /* not an IOSAPIC interrupt! */
319
low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
320
list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
321
rte_index = rte->rte_index;
322
iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
328
iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
332
unsigned int irq = data->irq;
334
int cpu, dest, rte_index;
335
int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
336
struct iosapic_rte_info *rte;
337
struct iosapic *iosapic;
339
irq &= (~IA64_IRQ_REDIRECTED);
341
cpu = cpumask_first_and(cpu_online_mask, mask);
342
if (cpu >= nr_cpu_ids)
345
if (irq_prepare_move(irq, cpu))
348
dest = cpu_physical_id(cpu);
350
if (!iosapic_intr_info[irq].count)
351
return -1; /* not an IOSAPIC interrupt */
353
set_irq_affinity_info(irq, dest, redir);
355
/* dest contains both id and eid */
356
high32 = dest << IOSAPIC_DEST_SHIFT;
358
low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
360
/* change delivery mode to lowest priority */
361
low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
363
/* change delivery mode to fixed */
364
low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
365
low32 &= IOSAPIC_VECTOR_MASK;
366
low32 |= irq_to_vector(irq);
368
iosapic_intr_info[irq].low32 = low32;
369
iosapic_intr_info[irq].dest = dest;
370
list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
371
iosapic = rte->iosapic;
372
rte_index = rte->rte_index;
373
iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
374
iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
382
* Handlers for level-triggered interrupts.
386
iosapic_startup_level_irq (struct irq_data *data)
393
iosapic_unmask_level_irq (struct irq_data *data)
395
unsigned int irq = data->irq;
396
ia64_vector vec = irq_to_vector(irq);
397
struct iosapic_rte_info *rte;
398
int do_unmask_irq = 0;
400
irq_complete_move(irq);
401
if (unlikely(irqd_is_setaffinity_pending(data))) {
407
list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
408
iosapic_eoi(rte->iosapic->addr, vec);
410
if (unlikely(do_unmask_irq)) {
411
irq_move_masked_irq(data);
416
#define iosapic_shutdown_level_irq mask_irq
417
#define iosapic_enable_level_irq unmask_irq
418
#define iosapic_disable_level_irq mask_irq
419
#define iosapic_ack_level_irq nop
421
static struct irq_chip irq_type_iosapic_level = {
422
.name = "IO-SAPIC-level",
423
.irq_startup = iosapic_startup_level_irq,
424
.irq_shutdown = iosapic_shutdown_level_irq,
425
.irq_enable = iosapic_enable_level_irq,
426
.irq_disable = iosapic_disable_level_irq,
427
.irq_ack = iosapic_ack_level_irq,
428
.irq_mask = mask_irq,
429
.irq_unmask = iosapic_unmask_level_irq,
430
.irq_set_affinity = iosapic_set_affinity
434
* Handlers for edge-triggered interrupts.
438
iosapic_startup_edge_irq (struct irq_data *data)
442
* IOSAPIC simply drops interrupts pended while the
443
* corresponding pin was masked, so we can't know if an
444
* interrupt is pending already. Let's hope not...
450
iosapic_ack_edge_irq (struct irq_data *data)
452
irq_complete_move(data->irq);
456
#define iosapic_enable_edge_irq unmask_irq
457
#define iosapic_disable_edge_irq nop
459
static struct irq_chip irq_type_iosapic_edge = {
460
.name = "IO-SAPIC-edge",
461
.irq_startup = iosapic_startup_edge_irq,
462
.irq_shutdown = iosapic_disable_edge_irq,
463
.irq_enable = iosapic_enable_edge_irq,
464
.irq_disable = iosapic_disable_edge_irq,
465
.irq_ack = iosapic_ack_edge_irq,
466
.irq_mask = mask_irq,
467
.irq_unmask = unmask_irq,
468
.irq_set_affinity = iosapic_set_affinity
472
iosapic_version (char __iomem *addr)
475
* IOSAPIC Version Register return 32 bit structure like:
477
* unsigned int version : 8;
478
* unsigned int reserved1 : 8;
479
* unsigned int max_redir : 8;
480
* unsigned int reserved2 : 8;
483
return __iosapic_read(addr, IOSAPIC_VERSION);
486
static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
488
int i, irq = -ENOSPC, min_count = -1;
489
struct iosapic_intr_info *info;
492
* shared vectors for edge-triggered interrupts are not
495
if (trigger == IOSAPIC_EDGE)
498
for (i = 0; i < NR_IRQS; i++) {
499
info = &iosapic_intr_info[i];
500
if (info->trigger == trigger && info->polarity == pol &&
501
(info->dmode == IOSAPIC_FIXED ||
502
info->dmode == IOSAPIC_LOWEST_PRIORITY) &&
503
can_request_irq(i, IRQF_SHARED)) {
504
if (min_count == -1 || info->count < min_count) {
506
min_count = info->count;
514
* if the given vector is already owned by other,
515
* assign a new vector for the other and make the vector available
518
iosapic_reassign_vector (int irq)
522
if (iosapic_intr_info[irq].count) {
523
new_irq = create_irq();
525
panic("%s: out of interrupt vectors!\n", __func__);
526
printk(KERN_INFO "Reassigning vector %d to %d\n",
527
irq_to_vector(irq), irq_to_vector(new_irq));
528
memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
529
sizeof(struct iosapic_intr_info));
530
INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
531
list_move(iosapic_intr_info[irq].rtes.next,
532
&iosapic_intr_info[new_irq].rtes);
533
memset(&iosapic_intr_info[irq], 0,
534
sizeof(struct iosapic_intr_info));
535
iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
536
INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
540
static inline int irq_is_shared (int irq)
542
return (iosapic_intr_info[irq].count > 1);
546
ia64_native_iosapic_get_irq_chip(unsigned long trigger)
548
if (trigger == IOSAPIC_EDGE)
549
return &irq_type_iosapic_edge;
551
return &irq_type_iosapic_level;
555
register_intr (unsigned int gsi, int irq, unsigned char delivery,
556
unsigned long polarity, unsigned long trigger)
558
struct irq_chip *chip, *irq_type;
560
struct iosapic_rte_info *rte;
562
index = find_iosapic(gsi);
564
printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
569
rte = find_rte(irq, gsi);
571
rte = kzalloc(sizeof (*rte), GFP_ATOMIC);
573
printk(KERN_WARNING "%s: cannot allocate memory\n",
578
rte->iosapic = &iosapic_lists[index];
579
rte->rte_index = gsi - rte->iosapic->gsi_base;
581
list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
582
iosapic_intr_info[irq].count++;
583
iosapic_lists[index].rtes_inuse++;
585
else if (rte->refcnt == NO_REF_RTE) {
586
struct iosapic_intr_info *info = &iosapic_intr_info[irq];
587
if (info->count > 0 &&
588
(info->trigger != trigger || info->polarity != polarity)){
590
"%s: cannot override the interrupt\n",
595
iosapic_intr_info[irq].count++;
596
iosapic_lists[index].rtes_inuse++;
599
iosapic_intr_info[irq].polarity = polarity;
600
iosapic_intr_info[irq].dmode = delivery;
601
iosapic_intr_info[irq].trigger = trigger;
603
irq_type = iosapic_get_irq_chip(trigger);
605
chip = irq_get_chip(irq);
606
if (irq_type != NULL && chip != irq_type) {
607
if (chip != &no_irq_chip)
609
"%s: changing vector %d from %s to %s\n",
610
__func__, irq_to_vector(irq),
611
chip->name, irq_type->name);
614
__irq_set_chip_handler_name_locked(irq, chip, trigger == IOSAPIC_EDGE ?
615
handle_edge_irq : handle_level_irq,
621
get_target_cpu (unsigned int gsi, int irq)
625
extern int cpe_vector;
626
cpumask_t domain = irq_to_domain(irq);
629
* In case of vector shared by multiple RTEs, all RTEs that
630
* share the vector need to use the same destination CPU.
632
if (iosapic_intr_info[irq].count)
633
return iosapic_intr_info[irq].dest;
636
* If the platform supports redirection via XTP, let it
637
* distribute interrupts.
639
if (smp_int_redirect & SMP_IRQ_REDIRECTION)
640
return cpu_physical_id(smp_processor_id());
643
* Some interrupts (ACPI SCI, for instance) are registered
644
* before the BSP is marked as online.
646
if (!cpu_online(smp_processor_id()))
647
return cpu_physical_id(smp_processor_id());
650
if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
651
return get_cpei_target_cpu();
656
int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
657
const struct cpumask *cpu_mask;
659
iosapic_index = find_iosapic(gsi);
660
if (iosapic_index < 0 ||
661
iosapic_lists[iosapic_index].node == MAX_NUMNODES)
662
goto skip_numa_setup;
664
cpu_mask = cpumask_of_node(iosapic_lists[iosapic_index].node);
666
for_each_cpu_and(numa_cpu, cpu_mask, &domain) {
667
if (cpu_online(numa_cpu))
672
goto skip_numa_setup;
674
/* Use irq assignment to distribute across cpus in node */
675
cpu_index = irq % num_cpus;
677
for_each_cpu_and(numa_cpu, cpu_mask, &domain)
678
if (cpu_online(numa_cpu) && i++ >= cpu_index)
681
if (numa_cpu < nr_cpu_ids)
682
return cpu_physical_id(numa_cpu);
687
* Otherwise, round-robin interrupt vectors across all the
688
* processors. (It'd be nice if we could be smarter in the
692
if (++cpu >= nr_cpu_ids)
694
} while (!cpu_online(cpu) || !cpu_isset(cpu, domain));
696
return cpu_physical_id(cpu);
697
#else /* CONFIG_SMP */
698
return cpu_physical_id(smp_processor_id());
702
static inline unsigned char choose_dmode(void)
705
if (smp_int_redirect & SMP_IRQ_REDIRECTION)
706
return IOSAPIC_LOWEST_PRIORITY;
708
return IOSAPIC_FIXED;
712
* ACPI can describe IOSAPIC interrupts via static tables and namespace
713
* methods. This provides an interface to register those interrupts and
714
* program the IOSAPIC RTE.
717
iosapic_register_intr (unsigned int gsi,
718
unsigned long polarity, unsigned long trigger)
720
int irq, mask = 1, err;
723
struct iosapic_rte_info *rte;
726
struct irq_desc *desc;
729
* If this GSI has already been registered (i.e., it's a
730
* shared interrupt, or we lost a race to register it),
731
* don't touch the RTE.
733
spin_lock_irqsave(&iosapic_lock, flags);
734
irq = __gsi_to_irq(gsi);
736
rte = find_rte(irq, gsi);
737
if(iosapic_intr_info[irq].count == 0) {
738
assign_irq_vector(irq);
739
dynamic_irq_init(irq);
740
} else if (rte->refcnt != NO_REF_RTE) {
742
goto unlock_iosapic_lock;
747
/* If vector is running out, we try to find a sharable vector */
749
irq = iosapic_find_sharable_irq(trigger, polarity);
751
goto unlock_iosapic_lock;
754
desc = irq_to_desc(irq);
755
raw_spin_lock(&desc->lock);
756
dest = get_target_cpu(gsi, irq);
757
dmode = choose_dmode();
758
err = register_intr(gsi, irq, dmode, polarity, trigger);
760
raw_spin_unlock(&desc->lock);
762
goto unlock_iosapic_lock;
766
* If the vector is shared and already unmasked for other
767
* interrupt sources, don't mask it.
769
low32 = iosapic_intr_info[irq].low32;
770
if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
772
set_rte(gsi, irq, dest, mask);
774
printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
775
gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
776
(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
777
cpu_logical_id(dest), dest, irq_to_vector(irq));
779
raw_spin_unlock(&desc->lock);
781
spin_unlock_irqrestore(&iosapic_lock, flags);
786
iosapic_unregister_intr (unsigned int gsi)
791
unsigned long trigger, polarity;
793
struct iosapic_rte_info *rte;
796
* If the irq associated with the gsi is not found,
797
* iosapic_unregister_intr() is unbalanced. We need to check
798
* this again after getting locks.
800
irq = gsi_to_irq(gsi);
802
printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
808
spin_lock_irqsave(&iosapic_lock, flags);
809
if ((rte = find_rte(irq, gsi)) == NULL) {
810
printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
816
if (--rte->refcnt > 0)
819
rte->refcnt = NO_REF_RTE;
821
/* Mask the interrupt */
822
low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
823
iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
825
iosapic_intr_info[irq].count--;
826
index = find_iosapic(gsi);
827
iosapic_lists[index].rtes_inuse--;
828
WARN_ON(iosapic_lists[index].rtes_inuse < 0);
830
trigger = iosapic_intr_info[irq].trigger;
831
polarity = iosapic_intr_info[irq].polarity;
832
dest = iosapic_intr_info[irq].dest;
834
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
835
gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
836
(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
837
cpu_logical_id(dest), dest, irq_to_vector(irq));
839
if (iosapic_intr_info[irq].count == 0) {
842
cpumask_setall(irq_get_irq_data(irq)->affinity);
844
/* Clear the interrupt information */
845
iosapic_intr_info[irq].dest = 0;
846
iosapic_intr_info[irq].dmode = 0;
847
iosapic_intr_info[irq].polarity = 0;
848
iosapic_intr_info[irq].trigger = 0;
849
iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
851
/* Destroy and reserve IRQ */
852
destroy_and_reserve_irq(irq);
855
spin_unlock_irqrestore(&iosapic_lock, flags);
859
* ACPI calls this when it finds an entry for a platform interrupt.
862
iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
863
int iosapic_vector, u16 eid, u16 id,
864
unsigned long polarity, unsigned long trigger)
866
static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
867
unsigned char delivery;
868
int irq, vector, mask = 0;
869
unsigned int dest = ((id << 8) | eid) & 0xffff;
872
case ACPI_INTERRUPT_PMI:
873
irq = vector = iosapic_vector;
874
bind_irq_vector(irq, vector, CPU_MASK_ALL);
876
* since PMI vector is alloc'd by FW(ACPI) not by kernel,
877
* we need to make sure the vector is available
879
iosapic_reassign_vector(irq);
880
delivery = IOSAPIC_PMI;
882
case ACPI_INTERRUPT_INIT:
885
panic("%s: out of interrupt vectors!\n", __func__);
886
vector = irq_to_vector(irq);
887
delivery = IOSAPIC_INIT;
889
case ACPI_INTERRUPT_CPEI:
890
irq = vector = IA64_CPE_VECTOR;
891
BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
892
delivery = IOSAPIC_FIXED;
896
printk(KERN_ERR "%s: invalid int type 0x%x\n", __func__,
901
register_intr(gsi, irq, delivery, polarity, trigger);
904
"PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
906
int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
907
int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
908
(polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
909
cpu_logical_id(dest), dest, vector);
911
set_rte(gsi, irq, dest, mask);
916
* ACPI calls this when it finds an entry for a legacy ISA IRQ override.
919
iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
920
unsigned long polarity,
921
unsigned long trigger)
924
unsigned int dest = cpu_physical_id(smp_processor_id());
927
irq = vector = isa_irq_to_vector(isa_irq);
928
BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
929
dmode = choose_dmode();
930
register_intr(gsi, irq, dmode, polarity, trigger);
932
DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
933
isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
934
polarity == IOSAPIC_POL_HIGH ? "high" : "low",
935
cpu_logical_id(dest), dest, vector);
937
set_rte(gsi, irq, dest, 1);
941
ia64_native_iosapic_pcat_compat_init(void)
945
* Disable the compatibility mode interrupts (8259 style),
946
* needs IN/OUT support enabled.
949
"%s: Disabling PC-AT compatible 8259 interrupts\n",
957
iosapic_system_init (int system_pcat_compat)
961
for (irq = 0; irq < NR_IRQS; ++irq) {
962
iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
964
INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
966
iosapic_intr_info[irq].count = 0;
969
pcat_compat = system_pcat_compat;
971
iosapic_pcat_compat_init();
979
for (index = 0; index < NR_IOSAPICS; index++)
980
if (!iosapic_lists[index].addr)
983
printk(KERN_WARNING "%s: failed to allocate iosapic\n", __func__);
988
iosapic_free (int index)
990
memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
994
iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
997
unsigned int gsi_end, base, end;
999
/* check gsi range */
1000
gsi_end = gsi_base + ((ver >> 16) & 0xff);
1001
for (index = 0; index < NR_IOSAPICS; index++) {
1002
if (!iosapic_lists[index].addr)
1005
base = iosapic_lists[index].gsi_base;
1006
end = base + iosapic_lists[index].num_rte - 1;
1008
if (gsi_end < base || end < gsi_base)
1017
iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1019
int num_rte, err, index;
1020
unsigned int isa_irq, ver;
1022
unsigned long flags;
1024
spin_lock_irqsave(&iosapic_lock, flags);
1025
index = find_iosapic(gsi_base);
1027
spin_unlock_irqrestore(&iosapic_lock, flags);
1031
addr = ioremap(phys_addr, 0);
1033
spin_unlock_irqrestore(&iosapic_lock, flags);
1036
ver = iosapic_version(addr);
1037
if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1039
spin_unlock_irqrestore(&iosapic_lock, flags);
1044
* The MAX_REDIR register holds the highest input pin number
1045
* (starting from 0). We add 1 so that we can use it for
1046
* number of pins (= RTEs)
1048
num_rte = ((ver >> 16) & 0xff) + 1;
1050
index = iosapic_alloc();
1051
iosapic_lists[index].addr = addr;
1052
iosapic_lists[index].gsi_base = gsi_base;
1053
iosapic_lists[index].num_rte = num_rte;
1055
iosapic_lists[index].node = MAX_NUMNODES;
1057
spin_lock_init(&iosapic_lists[index].lock);
1058
spin_unlock_irqrestore(&iosapic_lock, flags);
1060
if ((gsi_base == 0) && pcat_compat) {
1062
* Map the legacy ISA devices into the IOSAPIC data. Some of
1063
* these may get reprogrammed later on with data from the ACPI
1064
* Interrupt Source Override table.
1066
for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1067
iosapic_override_isa_irq(isa_irq, isa_irq,
1074
#ifdef CONFIG_HOTPLUG
1076
iosapic_remove (unsigned int gsi_base)
1079
unsigned long flags;
1081
spin_lock_irqsave(&iosapic_lock, flags);
1082
index = find_iosapic(gsi_base);
1084
printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1085
__func__, gsi_base);
1089
if (iosapic_lists[index].rtes_inuse) {
1091
printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1092
__func__, gsi_base);
1096
iounmap(iosapic_lists[index].addr);
1097
iosapic_free(index);
1099
spin_unlock_irqrestore(&iosapic_lock, flags);
1102
#endif /* CONFIG_HOTPLUG */
1106
map_iosapic_to_node(unsigned int gsi_base, int node)
1110
index = find_iosapic(gsi_base);
1112
printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1113
__func__, gsi_base);
1116
iosapic_lists[index].node = node;