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/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
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from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
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#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
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#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
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#define MEMARB_INTR_VECT 0x31
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#define GEN_IO_INTR_VECT 0x32
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#define GIO_INTR_VECT GEN_IO_INTR_VECT
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#define IOP0_INTR_VECT 0x33
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#define IOP1_INTR_VECT 0x34
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#define IOP2_INTR_VECT 0x35
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#define IOP3_INTR_VECT 0x36
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#define DMA0_INTR_VECT 0x37
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#define DMA1_INTR_VECT 0x38
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#define DMA2_INTR_VECT 0x39
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#define DMA3_INTR_VECT 0x3a
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#define DMA4_INTR_VECT 0x3b
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#define DMA5_INTR_VECT 0x3c
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#define DMA6_INTR_VECT 0x3d
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#define DMA7_INTR_VECT 0x3e
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#define DMA8_INTR_VECT 0x3f
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#define DMA9_INTR_VECT 0x40
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#define ATA_INTR_VECT 0x41
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#define SSER0_INTR_VECT 0x42
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#define SSER1_INTR_VECT 0x43
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#define SER0_INTR_VECT 0x44
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#define SER1_INTR_VECT 0x45
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#define SER2_INTR_VECT 0x46
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#define SER3_INTR_VECT 0x47
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#define P21_INTR_VECT 0x48
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#define ETH0_INTR_VECT 0x49
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#define ETH1_INTR_VECT 0x4a
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#define TIMER_INTR_VECT 0x4b
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#define TIMER0_INTR_VECT TIMER_INTR_VECT
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#define BIF_ARB_INTR_VECT 0x4c
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#define BIF_DMA_INTR_VECT 0x4d
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#define EXT_INTR_VECT 0x4e
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#define IPI_INTR_VECT 0x4f
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#define NBR_INTR_VECT 0x50