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* Copyright (C) 2006, 2007 Eugene Konev
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/moduleparam.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/if_vlan.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/skbuff.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/phy_fixed.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/atomic.h>
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MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
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MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:cpmac");
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static int debug_level = 8;
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static int dumb_switch;
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/* Next 2 are only used in cpmac_probe, so it's pointless to change them */
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module_param(debug_level, int, 0444);
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module_param(dumb_switch, int, 0444);
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MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
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MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
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#define CPMAC_VERSION "0.5.2"
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/* frame size + 802.1q tag + FCS size */
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#define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
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#define CPMAC_QUEUES 8
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/* Ethernet registers */
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#define CPMAC_TX_CONTROL 0x0004
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#define CPMAC_TX_TEARDOWN 0x0008
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#define CPMAC_RX_CONTROL 0x0014
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#define CPMAC_RX_TEARDOWN 0x0018
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#define CPMAC_MBP 0x0100
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# define MBP_RXPASSCRC 0x40000000
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# define MBP_RXQOS 0x20000000
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# define MBP_RXNOCHAIN 0x10000000
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# define MBP_RXCMF 0x01000000
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# define MBP_RXSHORT 0x00800000
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# define MBP_RXCEF 0x00400000
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# define MBP_RXPROMISC 0x00200000
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# define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
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# define MBP_RXBCAST 0x00002000
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# define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
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# define MBP_RXMCAST 0x00000020
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# define MBP_MCASTCHAN(channel) ((channel) & 0x7)
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#define CPMAC_UNICAST_ENABLE 0x0104
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#define CPMAC_UNICAST_CLEAR 0x0108
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#define CPMAC_MAX_LENGTH 0x010c
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#define CPMAC_BUFFER_OFFSET 0x0110
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#define CPMAC_MAC_CONTROL 0x0160
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# define MAC_TXPTYPE 0x00000200
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# define MAC_TXPACE 0x00000040
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# define MAC_MII 0x00000020
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# define MAC_TXFLOW 0x00000010
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# define MAC_RXFLOW 0x00000008
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# define MAC_MTEST 0x00000004
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# define MAC_LOOPBACK 0x00000002
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# define MAC_FDX 0x00000001
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#define CPMAC_MAC_STATUS 0x0164
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# define MAC_STATUS_QOS 0x00000004
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# define MAC_STATUS_RXFLOW 0x00000002
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# define MAC_STATUS_TXFLOW 0x00000001
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#define CPMAC_TX_INT_ENABLE 0x0178
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#define CPMAC_TX_INT_CLEAR 0x017c
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#define CPMAC_MAC_INT_VECTOR 0x0180
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# define MAC_INT_STATUS 0x00080000
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# define MAC_INT_HOST 0x00040000
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# define MAC_INT_RX 0x00020000
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# define MAC_INT_TX 0x00010000
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#define CPMAC_MAC_EOI_VECTOR 0x0184
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#define CPMAC_RX_INT_ENABLE 0x0198
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#define CPMAC_RX_INT_CLEAR 0x019c
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#define CPMAC_MAC_INT_ENABLE 0x01a8
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#define CPMAC_MAC_INT_CLEAR 0x01ac
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#define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
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#define CPMAC_MAC_ADDR_MID 0x01d0
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#define CPMAC_MAC_ADDR_HI 0x01d4
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#define CPMAC_MAC_HASH_LO 0x01d8
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#define CPMAC_MAC_HASH_HI 0x01dc
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#define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
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#define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
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#define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
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#define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
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#define CPMAC_REG_END 0x0680
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* TODO: use some of them to fill stats in cpmac_stats()
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#define CPMAC_STATS_RX_GOOD 0x0200
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#define CPMAC_STATS_RX_BCAST 0x0204
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#define CPMAC_STATS_RX_MCAST 0x0208
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#define CPMAC_STATS_RX_PAUSE 0x020c
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#define CPMAC_STATS_RX_CRC 0x0210
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#define CPMAC_STATS_RX_ALIGN 0x0214
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#define CPMAC_STATS_RX_OVER 0x0218
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#define CPMAC_STATS_RX_JABBER 0x021c
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#define CPMAC_STATS_RX_UNDER 0x0220
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#define CPMAC_STATS_RX_FRAG 0x0224
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#define CPMAC_STATS_RX_FILTER 0x0228
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#define CPMAC_STATS_RX_QOSFILTER 0x022c
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#define CPMAC_STATS_RX_OCTETS 0x0230
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#define CPMAC_STATS_TX_GOOD 0x0234
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#define CPMAC_STATS_TX_BCAST 0x0238
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#define CPMAC_STATS_TX_MCAST 0x023c
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#define CPMAC_STATS_TX_PAUSE 0x0240
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#define CPMAC_STATS_TX_DEFER 0x0244
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#define CPMAC_STATS_TX_COLLISION 0x0248
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#define CPMAC_STATS_TX_SINGLECOLL 0x024c
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#define CPMAC_STATS_TX_MULTICOLL 0x0250
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#define CPMAC_STATS_TX_EXCESSCOLL 0x0254
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#define CPMAC_STATS_TX_LATECOLL 0x0258
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#define CPMAC_STATS_TX_UNDERRUN 0x025c
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#define CPMAC_STATS_TX_CARRIERSENSE 0x0260
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#define CPMAC_STATS_TX_OCTETS 0x0264
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#define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
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#define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
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#define CPMAC_MDIO_VERSION 0x0000
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#define CPMAC_MDIO_CONTROL 0x0004
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# define MDIOC_IDLE 0x80000000
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# define MDIOC_ENABLE 0x40000000
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# define MDIOC_PREAMBLE 0x00100000
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# define MDIOC_FAULT 0x00080000
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# define MDIOC_FAULTDETECT 0x00040000
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# define MDIOC_INTTEST 0x00020000
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# define MDIOC_CLKDIV(div) ((div) & 0xff)
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#define CPMAC_MDIO_ALIVE 0x0008
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#define CPMAC_MDIO_LINK 0x000c
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#define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
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# define MDIO_BUSY 0x80000000
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# define MDIO_WRITE 0x40000000
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# define MDIO_REG(reg) (((reg) & 0x1f) << 21)
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# define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
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# define MDIO_DATA(data) ((data) & 0xffff)
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#define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
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# define PHYSEL_LINKSEL 0x00000040
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# define PHYSEL_LINKINT 0x00000020
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#define CPMAC_SOP 0x8000
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#define CPMAC_EOP 0x4000
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#define CPMAC_OWN 0x2000
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#define CPMAC_EOQ 0x1000
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struct cpmac_desc *next;
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struct cpmac_desc *prev;
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dma_addr_t data_mapping;
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struct cpmac_desc *rx_head;
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struct cpmac_desc *desc_ring;
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struct mii_bus *mii_bus;
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struct phy_device *phy;
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char phy_name[MII_BUS_ID_SIZE + 3];
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int oldlink, oldspeed, oldduplex;
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struct net_device *dev;
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struct work_struct reset_work;
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struct platform_device *pdev;
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struct napi_struct napi;
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atomic_t reset_pending;
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static irqreturn_t cpmac_irq(int, void *);
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static void cpmac_hw_start(struct net_device *dev);
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static void cpmac_hw_stop(struct net_device *dev);
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static int cpmac_stop(struct net_device *dev);
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static int cpmac_open(struct net_device *dev);
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static void cpmac_dump_regs(struct net_device *dev)
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struct cpmac_priv *priv = netdev_priv(dev);
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for (i = 0; i < CPMAC_REG_END; i += 4) {
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printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
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printk(" %08x", cpmac_read(priv->regs, i));
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static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
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printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
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for (i = 0; i < sizeof(*desc) / 4; i++)
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printk(" %08x", ((u32 *)desc)[i]);
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static void cpmac_dump_all_desc(struct net_device *dev)
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struct cpmac_priv *priv = netdev_priv(dev);
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struct cpmac_desc *dump = priv->rx_head;
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cpmac_dump_desc(dev, dump);
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} while (dump != priv->rx_head);
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static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
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printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
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for (i = 0; i < skb->len; i++) {
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printk(KERN_DEBUG "%s: data[%p]:", dev->name,
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printk(" %02x", ((u8 *)skb->data)[i]);
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static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
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cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
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while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
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return MDIO_DATA(val);
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static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
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while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
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cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
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MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
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static int cpmac_mdio_reset(struct mii_bus *bus)
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struct clk *cpmac_clk;
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cpmac_clk = clk_get(&bus->dev, "cpmac");
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if (IS_ERR(cpmac_clk)) {
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printk(KERN_ERR "unable to get cpmac clock\n");
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ar7_device_reset(AR7_RESET_BIT_MDIO);
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cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
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MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
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static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
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static struct mii_bus *cpmac_mii;
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static int cpmac_config(struct net_device *dev, struct ifmap *map)
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if (dev->flags & IFF_UP)
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/* Don't allow changing the I/O address */
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if (map->base_addr != dev->base_addr)
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/* ignore other fields */
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static void cpmac_set_multicast_list(struct net_device *dev)
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struct netdev_hw_addr *ha;
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u32 mbp, bit, hash[2] = { 0, };
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struct cpmac_priv *priv = netdev_priv(dev);
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mbp = cpmac_read(priv->regs, CPMAC_MBP);
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if (dev->flags & IFF_PROMISC) {
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cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
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cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
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if (dev->flags & IFF_ALLMULTI) {
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/* enable all multicast mode */
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cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
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cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
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* cpmac uses some strange mac address hashing
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netdev_for_each_mc_addr(ha, dev) {
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bit ^= (tmp >> 2) ^ (tmp << 4);
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bit ^= (tmp >> 4) ^ (tmp << 2);
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bit ^= (tmp >> 6) ^ tmp;
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bit ^= (tmp >> 2) ^ (tmp << 4);
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bit ^= (tmp >> 4) ^ (tmp << 2);
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bit ^= (tmp >> 6) ^ tmp;
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hash[bit / 32] |= 1 << (bit % 32);
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cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
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cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
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static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
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struct cpmac_desc *desc)
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struct sk_buff *skb, *result = NULL;
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if (unlikely(netif_msg_hw(priv)))
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cpmac_dump_desc(priv->dev, desc);
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cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
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if (unlikely(!desc->datalen)) {
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if (netif_msg_rx_err(priv) && net_ratelimit())
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printk(KERN_WARNING "%s: rx: spurious interrupt\n",
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skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
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skb_put(desc->skb, desc->datalen);
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desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
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skb_checksum_none_assert(desc->skb);
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priv->dev->stats.rx_packets++;
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priv->dev->stats.rx_bytes += desc->datalen;
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dma_unmap_single(&priv->dev->dev, desc->data_mapping,
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CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
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desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
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desc->hw_data = (u32)desc->data_mapping;
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if (unlikely(netif_msg_pktdata(priv))) {
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printk(KERN_DEBUG "%s: received packet:\n",
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cpmac_dump_skb(priv->dev, result);
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if (netif_msg_rx_err(priv) && net_ratelimit())
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"%s: low on skbs, dropping packet\n",
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priv->dev->stats.rx_dropped++;
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desc->buflen = CPMAC_SKB_SIZE;
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desc->dataflags = CPMAC_OWN;
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static int cpmac_poll(struct napi_struct *napi, int budget)
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struct cpmac_desc *desc, *restart;
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struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
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int received = 0, processed = 0;
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spin_lock(&priv->rx_lock);
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if (unlikely(!priv->rx_head)) {
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if (netif_msg_rx_err(priv) && net_ratelimit())
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printk(KERN_WARNING "%s: rx: polling, but no queue\n",
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spin_unlock(&priv->rx_lock);
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desc = priv->rx_head;
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while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
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if ((desc->dataflags & CPMAC_EOQ) != 0) {
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/* The last update to eoq->hw_next didn't happen
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* soon enough, and the receiver stopped here.
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*Remember this descriptor so we can restart
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* the receiver after freeing some space.
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if (unlikely(restart)) {
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if (netif_msg_rx_err(priv))
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printk(KERN_ERR "%s: poll found a"
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" duplicate EOQ: %p and %p\n",
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priv->dev->name, restart, desc);
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restart = desc->next;
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skb = cpmac_rx_one(priv, desc);
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netif_receive_skb(skb);
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if (desc != priv->rx_head) {
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/* We freed some buffers, but not the whole ring,
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* add what we did free to the rx list */
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desc->prev->hw_next = (u32)0;
476
priv->rx_head->prev->hw_next = priv->rx_head->mapping;
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/* Optimization: If we did not actually process an EOQ (perhaps because
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* of quota limits), check to see if the tail of the queue has EOQ set.
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* We should immediately restart in that case so that the receiver can
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* restart and run in parallel with more packet processing.
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* This lets us handle slightly larger bursts before running
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* out of ring space (assuming dev->weight < ring_size) */
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(priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
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(priv->rx_head->dataflags & CPMAC_OWN) != 0) {
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/* reset EOQ so the poll loop (above) doesn't try to
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* restart this when it eventually gets to this descriptor.
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priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
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restart = priv->rx_head;
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priv->dev->stats.rx_errors++;
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priv->dev->stats.rx_fifo_errors++;
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if (netif_msg_rx_err(priv) && net_ratelimit())
501
printk(KERN_WARNING "%s: rx dma ring overrun\n",
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if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
505
if (netif_msg_drv(priv))
506
printk(KERN_ERR "%s: cpmac_poll is trying to "
507
"restart rx from a descriptor that's "
509
priv->dev->name, restart);
513
cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
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priv->rx_head = desc;
517
spin_unlock(&priv->rx_lock);
518
if (unlikely(netif_msg_rx_status(priv)))
519
printk(KERN_DEBUG "%s: poll processed %d packets\n",
520
priv->dev->name, received);
521
if (processed == 0) {
522
/* we ran out of packets to read,
523
* revert to interrupt-driven mode */
525
cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
532
/* Something went horribly wrong.
533
* Reset hardware to try to recover rather than wedging. */
535
if (netif_msg_drv(priv)) {
536
printk(KERN_ERR "%s: cpmac_poll is confused. "
537
"Resetting hardware\n", priv->dev->name);
538
cpmac_dump_all_desc(priv->dev);
539
printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
541
cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
542
cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
545
spin_unlock(&priv->rx_lock);
547
netif_tx_stop_all_queues(priv->dev);
548
napi_disable(&priv->napi);
550
atomic_inc(&priv->reset_pending);
551
cpmac_hw_stop(priv->dev);
552
if (!schedule_work(&priv->reset_work))
553
atomic_dec(&priv->reset_pending);
558
static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
561
struct cpmac_desc *desc;
562
struct cpmac_priv *priv = netdev_priv(dev);
564
if (unlikely(atomic_read(&priv->reset_pending)))
565
return NETDEV_TX_BUSY;
567
if (unlikely(skb_padto(skb, ETH_ZLEN)))
570
len = max(skb->len, ETH_ZLEN);
571
queue = skb_get_queue_mapping(skb);
572
netif_stop_subqueue(dev, queue);
574
desc = &priv->desc_ring[queue];
575
if (unlikely(desc->dataflags & CPMAC_OWN)) {
576
if (netif_msg_tx_err(priv) && net_ratelimit())
577
printk(KERN_WARNING "%s: tx dma ring full\n",
579
return NETDEV_TX_BUSY;
582
spin_lock(&priv->lock);
583
spin_unlock(&priv->lock);
584
desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
586
desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
588
desc->hw_data = (u32)desc->data_mapping;
591
if (unlikely(netif_msg_tx_queued(priv)))
592
printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
594
if (unlikely(netif_msg_hw(priv)))
595
cpmac_dump_desc(dev, desc);
596
if (unlikely(netif_msg_pktdata(priv)))
597
cpmac_dump_skb(dev, skb);
598
cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
603
static void cpmac_end_xmit(struct net_device *dev, int queue)
605
struct cpmac_desc *desc;
606
struct cpmac_priv *priv = netdev_priv(dev);
608
desc = &priv->desc_ring[queue];
609
cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
610
if (likely(desc->skb)) {
611
spin_lock(&priv->lock);
612
dev->stats.tx_packets++;
613
dev->stats.tx_bytes += desc->skb->len;
614
spin_unlock(&priv->lock);
615
dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
618
if (unlikely(netif_msg_tx_done(priv)))
619
printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
620
desc->skb, desc->skb->len);
622
dev_kfree_skb_irq(desc->skb);
624
if (__netif_subqueue_stopped(dev, queue))
625
netif_wake_subqueue(dev, queue);
627
if (netif_msg_tx_err(priv) && net_ratelimit())
629
"%s: end_xmit: spurious interrupt\n", dev->name);
630
if (__netif_subqueue_stopped(dev, queue))
631
netif_wake_subqueue(dev, queue);
635
static void cpmac_hw_stop(struct net_device *dev)
638
struct cpmac_priv *priv = netdev_priv(dev);
639
struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
641
ar7_device_reset(pdata->reset_bit);
642
cpmac_write(priv->regs, CPMAC_RX_CONTROL,
643
cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
644
cpmac_write(priv->regs, CPMAC_TX_CONTROL,
645
cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
646
for (i = 0; i < 8; i++) {
647
cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
648
cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
650
cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
651
cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
652
cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
653
cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
654
cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
655
cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
658
static void cpmac_hw_start(struct net_device *dev)
661
struct cpmac_priv *priv = netdev_priv(dev);
662
struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
664
ar7_device_reset(pdata->reset_bit);
665
for (i = 0; i < 8; i++) {
666
cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
667
cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
669
cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
671
cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
673
cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
674
for (i = 0; i < 8; i++)
675
cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
676
cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
677
cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
678
(dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
679
(dev->dev_addr[3] << 24));
680
cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
681
cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
682
cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
683
cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
684
cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
685
cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
686
cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
687
cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
688
cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
690
cpmac_write(priv->regs, CPMAC_RX_CONTROL,
691
cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
692
cpmac_write(priv->regs, CPMAC_TX_CONTROL,
693
cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
694
cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
695
cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
699
static void cpmac_clear_rx(struct net_device *dev)
701
struct cpmac_priv *priv = netdev_priv(dev);
702
struct cpmac_desc *desc;
704
if (unlikely(!priv->rx_head))
706
desc = priv->rx_head;
707
for (i = 0; i < priv->ring_size; i++) {
708
if ((desc->dataflags & CPMAC_OWN) == 0) {
709
if (netif_msg_rx_err(priv) && net_ratelimit())
710
printk(KERN_WARNING "%s: packet dropped\n",
712
if (unlikely(netif_msg_hw(priv)))
713
cpmac_dump_desc(dev, desc);
714
desc->dataflags = CPMAC_OWN;
715
dev->stats.rx_dropped++;
717
desc->hw_next = desc->next->mapping;
720
priv->rx_head->prev->hw_next = 0;
723
static void cpmac_clear_tx(struct net_device *dev)
725
struct cpmac_priv *priv = netdev_priv(dev);
727
if (unlikely(!priv->desc_ring))
729
for (i = 0; i < CPMAC_QUEUES; i++) {
730
priv->desc_ring[i].dataflags = 0;
731
if (priv->desc_ring[i].skb) {
732
dev_kfree_skb_any(priv->desc_ring[i].skb);
733
priv->desc_ring[i].skb = NULL;
738
static void cpmac_hw_error(struct work_struct *work)
740
struct cpmac_priv *priv =
741
container_of(work, struct cpmac_priv, reset_work);
743
spin_lock(&priv->rx_lock);
744
cpmac_clear_rx(priv->dev);
745
spin_unlock(&priv->rx_lock);
746
cpmac_clear_tx(priv->dev);
747
cpmac_hw_start(priv->dev);
749
atomic_dec(&priv->reset_pending);
751
netif_tx_wake_all_queues(priv->dev);
752
cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
755
static void cpmac_check_status(struct net_device *dev)
757
struct cpmac_priv *priv = netdev_priv(dev);
759
u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
760
int rx_channel = (macstatus >> 8) & 7;
761
int rx_code = (macstatus >> 12) & 15;
762
int tx_channel = (macstatus >> 16) & 7;
763
int tx_code = (macstatus >> 20) & 15;
765
if (rx_code || tx_code) {
766
if (netif_msg_drv(priv) && net_ratelimit()) {
767
/* Can't find any documentation on what these
768
*error codes actually are. So just log them and hope..
771
printk(KERN_WARNING "%s: host error %d on rx "
772
"channel %d (macstatus %08x), resetting\n",
773
dev->name, rx_code, rx_channel, macstatus);
775
printk(KERN_WARNING "%s: host error %d on tx "
776
"channel %d (macstatus %08x), resetting\n",
777
dev->name, tx_code, tx_channel, macstatus);
780
netif_tx_stop_all_queues(dev);
782
if (schedule_work(&priv->reset_work))
783
atomic_inc(&priv->reset_pending);
784
if (unlikely(netif_msg_hw(priv)))
785
cpmac_dump_regs(dev);
787
cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
790
static irqreturn_t cpmac_irq(int irq, void *dev_id)
792
struct net_device *dev = dev_id;
793
struct cpmac_priv *priv;
797
priv = netdev_priv(dev);
799
status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
801
if (unlikely(netif_msg_intr(priv)))
802
printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
805
if (status & MAC_INT_TX)
806
cpmac_end_xmit(dev, (status & 7));
808
if (status & MAC_INT_RX) {
809
queue = (status >> 8) & 7;
810
if (napi_schedule_prep(&priv->napi)) {
811
cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
812
__napi_schedule(&priv->napi);
816
cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
818
if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
819
cpmac_check_status(dev);
824
static void cpmac_tx_timeout(struct net_device *dev)
826
struct cpmac_priv *priv = netdev_priv(dev);
828
spin_lock(&priv->lock);
829
dev->stats.tx_errors++;
830
spin_unlock(&priv->lock);
831
if (netif_msg_tx_err(priv) && net_ratelimit())
832
printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
834
atomic_inc(&priv->reset_pending);
838
atomic_dec(&priv->reset_pending);
840
netif_tx_wake_all_queues(priv->dev);
843
static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
845
struct cpmac_priv *priv = netdev_priv(dev);
846
if (!(netif_running(dev)))
851
return phy_mii_ioctl(priv->phy, ifr, cmd);
854
static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
856
struct cpmac_priv *priv = netdev_priv(dev);
859
return phy_ethtool_gset(priv->phy, cmd);
864
static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
866
struct cpmac_priv *priv = netdev_priv(dev);
868
if (!capable(CAP_NET_ADMIN))
872
return phy_ethtool_sset(priv->phy, cmd);
877
static void cpmac_get_ringparam(struct net_device *dev,
878
struct ethtool_ringparam *ring)
880
struct cpmac_priv *priv = netdev_priv(dev);
882
ring->rx_max_pending = 1024;
883
ring->rx_mini_max_pending = 1;
884
ring->rx_jumbo_max_pending = 1;
885
ring->tx_max_pending = 1;
887
ring->rx_pending = priv->ring_size;
888
ring->rx_mini_pending = 1;
889
ring->rx_jumbo_pending = 1;
890
ring->tx_pending = 1;
893
static int cpmac_set_ringparam(struct net_device *dev,
894
struct ethtool_ringparam *ring)
896
struct cpmac_priv *priv = netdev_priv(dev);
898
if (netif_running(dev))
900
priv->ring_size = ring->rx_pending;
904
static void cpmac_get_drvinfo(struct net_device *dev,
905
struct ethtool_drvinfo *info)
907
strcpy(info->driver, "cpmac");
908
strcpy(info->version, CPMAC_VERSION);
909
info->fw_version[0] = '\0';
910
sprintf(info->bus_info, "%s", "cpmac");
911
info->regdump_len = 0;
914
static const struct ethtool_ops cpmac_ethtool_ops = {
915
.get_settings = cpmac_get_settings,
916
.set_settings = cpmac_set_settings,
917
.get_drvinfo = cpmac_get_drvinfo,
918
.get_link = ethtool_op_get_link,
919
.get_ringparam = cpmac_get_ringparam,
920
.set_ringparam = cpmac_set_ringparam,
923
static void cpmac_adjust_link(struct net_device *dev)
925
struct cpmac_priv *priv = netdev_priv(dev);
928
spin_lock(&priv->lock);
929
if (priv->phy->link) {
930
netif_tx_start_all_queues(dev);
931
if (priv->phy->duplex != priv->oldduplex) {
933
priv->oldduplex = priv->phy->duplex;
936
if (priv->phy->speed != priv->oldspeed) {
938
priv->oldspeed = priv->phy->speed;
941
if (!priv->oldlink) {
945
} else if (priv->oldlink) {
949
priv->oldduplex = -1;
952
if (new_state && netif_msg_link(priv) && net_ratelimit())
953
phy_print_status(priv->phy);
955
spin_unlock(&priv->lock);
958
static int cpmac_open(struct net_device *dev)
961
struct cpmac_priv *priv = netdev_priv(dev);
962
struct resource *mem;
963
struct cpmac_desc *desc;
966
mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
967
if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
968
if (netif_msg_drv(priv))
969
printk(KERN_ERR "%s: failed to request registers\n",
975
priv->regs = ioremap(mem->start, resource_size(mem));
977
if (netif_msg_drv(priv))
978
printk(KERN_ERR "%s: failed to remap registers\n",
984
size = priv->ring_size + CPMAC_QUEUES;
985
priv->desc_ring = dma_alloc_coherent(&dev->dev,
986
sizeof(struct cpmac_desc) * size,
989
if (!priv->desc_ring) {
994
for (i = 0; i < size; i++)
995
priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
997
priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
998
for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
999
skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
1000
if (unlikely(!skb)) {
1005
desc->data_mapping = dma_map_single(&dev->dev, skb->data,
1008
desc->hw_data = (u32)desc->data_mapping;
1009
desc->buflen = CPMAC_SKB_SIZE;
1010
desc->dataflags = CPMAC_OWN;
1011
desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
1012
desc->next->prev = desc;
1013
desc->hw_next = (u32)desc->next->mapping;
1016
priv->rx_head->prev->hw_next = (u32)0;
1018
res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev);
1020
if (netif_msg_drv(priv))
1021
printk(KERN_ERR "%s: failed to obtain irq\n",
1026
atomic_set(&priv->reset_pending, 0);
1027
INIT_WORK(&priv->reset_work, cpmac_hw_error);
1028
cpmac_hw_start(dev);
1030
napi_enable(&priv->napi);
1031
priv->phy->state = PHY_CHANGELINK;
1032
phy_start(priv->phy);
1038
for (i = 0; i < priv->ring_size; i++) {
1039
if (priv->rx_head[i].skb) {
1040
dma_unmap_single(&dev->dev,
1041
priv->rx_head[i].data_mapping,
1044
kfree_skb(priv->rx_head[i].skb);
1048
kfree(priv->desc_ring);
1049
iounmap(priv->regs);
1052
release_mem_region(mem->start, resource_size(mem));
1058
static int cpmac_stop(struct net_device *dev)
1061
struct cpmac_priv *priv = netdev_priv(dev);
1062
struct resource *mem;
1064
netif_tx_stop_all_queues(dev);
1066
cancel_work_sync(&priv->reset_work);
1067
napi_disable(&priv->napi);
1068
phy_stop(priv->phy);
1072
for (i = 0; i < 8; i++)
1073
cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1074
cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1075
cpmac_write(priv->regs, CPMAC_MBP, 0);
1077
free_irq(dev->irq, dev);
1078
iounmap(priv->regs);
1079
mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1080
release_mem_region(mem->start, resource_size(mem));
1081
priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1082
for (i = 0; i < priv->ring_size; i++) {
1083
if (priv->rx_head[i].skb) {
1084
dma_unmap_single(&dev->dev,
1085
priv->rx_head[i].data_mapping,
1088
kfree_skb(priv->rx_head[i].skb);
1092
dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1093
(CPMAC_QUEUES + priv->ring_size),
1094
priv->desc_ring, priv->dma_ring);
1098
static const struct net_device_ops cpmac_netdev_ops = {
1099
.ndo_open = cpmac_open,
1100
.ndo_stop = cpmac_stop,
1101
.ndo_start_xmit = cpmac_start_xmit,
1102
.ndo_tx_timeout = cpmac_tx_timeout,
1103
.ndo_set_rx_mode = cpmac_set_multicast_list,
1104
.ndo_do_ioctl = cpmac_ioctl,
1105
.ndo_set_config = cpmac_config,
1106
.ndo_change_mtu = eth_change_mtu,
1107
.ndo_validate_addr = eth_validate_addr,
1108
.ndo_set_mac_address = eth_mac_addr,
1111
static int external_switch;
1113
static int __devinit cpmac_probe(struct platform_device *pdev)
1116
char mdio_bus_id[MII_BUS_ID_SIZE];
1117
struct resource *mem;
1118
struct cpmac_priv *priv;
1119
struct net_device *dev;
1120
struct plat_cpmac_data *pdata;
1122
pdata = pdev->dev.platform_data;
1124
if (external_switch || dumb_switch) {
1125
strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
1128
for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1129
if (!(pdata->phy_mask & (1 << phy_id)))
1131
if (!cpmac_mii->phy_map[phy_id])
1133
strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1138
if (phy_id == PHY_MAX_ADDR) {
1139
dev_err(&pdev->dev, "no PHY present, falling back "
1140
"to switch on MDIO bus 0\n");
1141
strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
1145
dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1148
printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1152
platform_set_drvdata(pdev, dev);
1153
priv = netdev_priv(dev);
1156
mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1162
dev->irq = platform_get_irq_byname(pdev, "irq");
1164
dev->netdev_ops = &cpmac_netdev_ops;
1165
dev->ethtool_ops = &cpmac_ethtool_ops;
1167
netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1169
spin_lock_init(&priv->lock);
1170
spin_lock_init(&priv->rx_lock);
1172
priv->ring_size = 64;
1173
priv->msg_enable = netif_msg_init(debug_level, 0xff);
1174
memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
1176
snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
1177
mdio_bus_id, phy_id);
1179
priv->phy = phy_connect(dev, priv->phy_name, cpmac_adjust_link, 0,
1180
PHY_INTERFACE_MODE_MII);
1182
if (IS_ERR(priv->phy)) {
1183
if (netif_msg_drv(priv))
1184
printk(KERN_ERR "%s: Could not attach to PHY\n",
1186
rc = PTR_ERR(priv->phy);
1190
rc = register_netdev(dev);
1192
printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1197
if (netif_msg_probe(priv)) {
1199
"cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1200
"mac: %pM)\n", dev->name, (void *)mem->start, dev->irq,
1201
priv->phy_name, dev->dev_addr);
1210
static int __devexit cpmac_remove(struct platform_device *pdev)
1212
struct net_device *dev = platform_get_drvdata(pdev);
1213
unregister_netdev(dev);
1218
static struct platform_driver cpmac_driver = {
1219
.driver.name = "cpmac",
1220
.driver.owner = THIS_MODULE,
1221
.probe = cpmac_probe,
1222
.remove = __devexit_p(cpmac_remove),
1225
int __devinit cpmac_init(void)
1230
cpmac_mii = mdiobus_alloc();
1231
if (cpmac_mii == NULL)
1234
cpmac_mii->name = "cpmac-mii";
1235
cpmac_mii->read = cpmac_mdio_read;
1236
cpmac_mii->write = cpmac_mdio_write;
1237
cpmac_mii->reset = cpmac_mdio_reset;
1238
cpmac_mii->irq = mii_irqs;
1240
cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1242
if (!cpmac_mii->priv) {
1243
printk(KERN_ERR "Can't ioremap mdio registers\n");
1248
#warning FIXME: unhardcode gpio&reset bits
1249
ar7_gpio_disable(26);
1250
ar7_gpio_disable(27);
1251
ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1252
ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1253
ar7_device_reset(AR7_RESET_BIT_EPHY);
1255
cpmac_mii->reset(cpmac_mii);
1257
for (i = 0; i < 300; i++) {
1258
mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE);
1266
if (mask & (mask - 1)) {
1267
external_switch = 1;
1271
cpmac_mii->phy_mask = ~(mask | 0x80000000);
1272
snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1");
1274
res = mdiobus_register(cpmac_mii);
1278
res = platform_driver_register(&cpmac_driver);
1285
mdiobus_unregister(cpmac_mii);
1288
iounmap(cpmac_mii->priv);
1291
mdiobus_free(cpmac_mii);
1296
void __devexit cpmac_exit(void)
1298
platform_driver_unregister(&cpmac_driver);
1299
mdiobus_unregister(cpmac_mii);
1300
iounmap(cpmac_mii->priv);
1301
mdiobus_free(cpmac_mii);
1304
module_init(cpmac_init);
1305
module_exit(cpmac_exit);