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#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
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* OMAP3430 Clock Management register bits
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2008 Nokia Corporation
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* Written by Paul Walmsley
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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/* Bits shared between registers */
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/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
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#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
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#define OMAP3430ES2_EN_MMC3_SHIFT 30
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#define OMAP3430_EN_MSPRO_MASK (1 << 23)
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#define OMAP3430_EN_MSPRO_SHIFT 23
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#define OMAP3430_EN_HDQ_MASK (1 << 22)
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#define OMAP3430_EN_HDQ_SHIFT 22
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#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
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#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
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#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
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#define OMAP3430ES1_EN_D2D_SHIFT 3
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#define OMAP3430_EN_SSI_MASK (1 << 0)
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#define OMAP3430_EN_SSI_SHIFT 0
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/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
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#define OMAP3430ES2_EN_USBTLL_SHIFT 2
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#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
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/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
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#define OMAP3430_EN_WDT2_MASK (1 << 5)
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#define OMAP3430_EN_WDT2_SHIFT 5
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/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
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#define OMAP3430_EN_CAM_MASK (1 << 0)
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#define OMAP3430_EN_CAM_SHIFT 0
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/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
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#define OMAP3430_EN_WDT3_MASK (1 << 12)
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#define OMAP3430_EN_WDT3_SHIFT 12
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/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
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#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
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/* Bits specific to each register */
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#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
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#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
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/* CM_CLKEN_PLL_IVA2 */
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#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
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#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
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#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
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#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
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#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
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#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
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#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
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#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
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#define OMAP3430_ST_IVA2_MASK (1 << 0)
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/* CM_IDLEST_PLL_IVA2 */
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#define OMAP3430_ST_IVA2_CLK_SHIFT 0
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#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
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/* CM_AUTOIDLE_PLL_IVA2 */
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#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
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#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
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/* CM_CLKSEL1_PLL_IVA2 */
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#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
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#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
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#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
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#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
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#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
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#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
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/* CM_CLKSEL2_PLL_IVA2 */
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#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
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#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
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/* CM_CLKSTCTRL_IVA2 */
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#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
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#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
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#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
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#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
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/* CM_REVISION specific bits */
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/* CM_SYSCONFIG specific bits */
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/* CM_CLKEN_PLL_MPU */
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#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
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#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
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#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
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#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
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#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
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#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
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#define OMAP3430_EN_MPU_DPLL_SHIFT 0
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#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
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#define OMAP3430_ST_MPU_MASK (1 << 0)
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/* CM_IDLEST_PLL_MPU */
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#define OMAP3430_ST_MPU_CLK_SHIFT 0
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#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
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/* CM_AUTOIDLE_PLL_MPU */
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#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
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#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
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/* CM_CLKSEL1_PLL_MPU */
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#define OMAP3430_MPU_CLK_SRC_SHIFT 19
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#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
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#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
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#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
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#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
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#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
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/* CM_CLKSEL2_PLL_MPU */
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#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
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#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
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/* CM_CLKSTCTRL_MPU */
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#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
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#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
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#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
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#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
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/* CM_FCLKEN1_CORE specific bits */
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#define OMAP3430_EN_MODEM_MASK (1 << 31)
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#define OMAP3430_EN_MODEM_SHIFT 31
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/* CM_ICLKEN1_CORE specific bits */
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#define OMAP3430_EN_ICR_MASK (1 << 29)
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#define OMAP3430_EN_ICR_SHIFT 29
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#define OMAP3430_EN_AES2_MASK (1 << 28)
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#define OMAP3430_EN_AES2_SHIFT 28
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#define OMAP3430_EN_SHA12_MASK (1 << 27)
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#define OMAP3430_EN_SHA12_SHIFT 27
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#define OMAP3430_EN_DES2_MASK (1 << 26)
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#define OMAP3430_EN_DES2_SHIFT 26
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#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
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#define OMAP3430ES1_EN_FAC_SHIFT 8
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#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
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#define OMAP3430_EN_MAILBOXES_SHIFT 7
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#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
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#define OMAP3430_EN_OMAPCTRL_SHIFT 6
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#define OMAP3430_EN_SAD2D_MASK (1 << 3)
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#define OMAP3430_EN_SAD2D_SHIFT 3
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#define OMAP3430_EN_SDRC_MASK (1 << 1)
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#define OMAP3430_EN_SDRC_SHIFT 1
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/* AM35XX specific CM_ICLKEN1_CORE bits */
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#define AM35XX_EN_IPSS_MASK (1 << 4)
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#define AM35XX_EN_IPSS_SHIFT 4
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#define AM35XX_EN_UART4_MASK (1 << 23)
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#define AM35XX_EN_UART4_SHIFT 23
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/* CM_ICLKEN2_CORE */
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#define OMAP3430_EN_PKA_MASK (1 << 4)
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#define OMAP3430_EN_PKA_SHIFT 4
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#define OMAP3430_EN_AES1_MASK (1 << 3)
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#define OMAP3430_EN_AES1_SHIFT 3
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#define OMAP3430_EN_RNG_MASK (1 << 2)
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#define OMAP3430_EN_RNG_SHIFT 2
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#define OMAP3430_EN_SHA11_MASK (1 << 1)
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#define OMAP3430_EN_SHA11_SHIFT 1
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#define OMAP3430_EN_DES1_MASK (1 << 0)
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#define OMAP3430_EN_DES1_SHIFT 0
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/* CM_ICLKEN3_CORE */
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#define OMAP3430_EN_MAD2D_SHIFT 3
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#define OMAP3430_EN_MAD2D_MASK (1 << 3)
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/* CM_FCLKEN3_CORE specific bits */
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#define OMAP3430ES2_EN_TS_SHIFT 1
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#define OMAP3430ES2_EN_TS_MASK (1 << 1)
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#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
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#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
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/* CM_IDLEST1_CORE specific bits */
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#define OMAP3430ES2_ST_MMC3_SHIFT 30
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#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
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#define OMAP3430_ST_ICR_SHIFT 29
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#define OMAP3430_ST_ICR_MASK (1 << 29)
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#define OMAP3430_ST_AES2_SHIFT 28
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#define OMAP3430_ST_AES2_MASK (1 << 28)
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#define OMAP3430_ST_SHA12_SHIFT 27
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#define OMAP3430_ST_SHA12_MASK (1 << 27)
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#define OMAP3430_ST_DES2_SHIFT 26
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#define OMAP3430_ST_DES2_MASK (1 << 26)
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#define OMAP3430_ST_MSPRO_SHIFT 23
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#define OMAP3430_ST_MSPRO_MASK (1 << 23)
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#define OMAP3430_ST_HDQ_SHIFT 22
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#define OMAP3430_ST_HDQ_MASK (1 << 22)
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#define OMAP3430ES1_ST_FAC_SHIFT 8
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#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
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#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
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#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
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#define OMAP3430_ST_MAILBOXES_SHIFT 7
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#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
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#define OMAP3430_ST_OMAPCTRL_SHIFT 6
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#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
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#define OMAP3430_ST_SDMA_SHIFT 2
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#define OMAP3430_ST_SDMA_MASK (1 << 2)
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#define OMAP3430_ST_SDRC_SHIFT 1
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#define OMAP3430_ST_SDRC_MASK (1 << 1)
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#define OMAP3430_ST_SSI_STDBY_SHIFT 0
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#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
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/* AM35xx specific CM_IDLEST1_CORE bits */
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#define AM35XX_ST_IPSS_SHIFT 5
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#define AM35XX_ST_IPSS_MASK (1 << 5)
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/* CM_IDLEST2_CORE */
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#define OMAP3430_ST_PKA_SHIFT 4
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#define OMAP3430_ST_PKA_MASK (1 << 4)
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#define OMAP3430_ST_AES1_SHIFT 3
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#define OMAP3430_ST_AES1_MASK (1 << 3)
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#define OMAP3430_ST_RNG_SHIFT 2
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#define OMAP3430_ST_RNG_MASK (1 << 2)
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#define OMAP3430_ST_SHA11_SHIFT 1
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#define OMAP3430_ST_SHA11_MASK (1 << 1)
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#define OMAP3430_ST_DES1_SHIFT 0
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#define OMAP3430_ST_DES1_MASK (1 << 0)
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/* CM_IDLEST3_CORE */
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#define OMAP3430ES2_ST_USBTLL_SHIFT 2
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#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
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#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
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#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
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/* CM_AUTOIDLE1_CORE */
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#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
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#define OMAP3430_AUTO_MODEM_SHIFT 31
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#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
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#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
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#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
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#define OMAP3430ES2_AUTO_ICR_SHIFT 29
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#define OMAP3430_AUTO_AES2_MASK (1 << 28)
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#define OMAP3430_AUTO_AES2_SHIFT 28
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#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
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#define OMAP3430_AUTO_SHA12_SHIFT 27
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#define OMAP3430_AUTO_DES2_MASK (1 << 26)
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#define OMAP3430_AUTO_DES2_SHIFT 26
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#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
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#define OMAP3430_AUTO_MMC2_SHIFT 25
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#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
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#define OMAP3430_AUTO_MMC1_SHIFT 24
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#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
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#define OMAP3430_AUTO_MSPRO_SHIFT 23
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#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
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#define OMAP3430_AUTO_HDQ_SHIFT 22
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#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
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#define OMAP3430_AUTO_MCSPI4_SHIFT 21
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#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
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#define OMAP3430_AUTO_MCSPI3_SHIFT 20
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#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
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#define OMAP3430_AUTO_MCSPI2_SHIFT 19
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#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
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#define OMAP3430_AUTO_MCSPI1_SHIFT 18
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#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
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#define OMAP3430_AUTO_I2C3_SHIFT 17
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#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
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#define OMAP3430_AUTO_I2C2_SHIFT 16
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#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
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#define OMAP3430_AUTO_I2C1_SHIFT 15
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#define OMAP3430_AUTO_UART2_MASK (1 << 14)
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#define OMAP3430_AUTO_UART2_SHIFT 14
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#define OMAP3430_AUTO_UART1_MASK (1 << 13)
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#define OMAP3430_AUTO_UART1_SHIFT 13
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#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
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#define OMAP3430_AUTO_GPT11_SHIFT 12
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#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
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#define OMAP3430_AUTO_GPT10_SHIFT 11
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#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
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#define OMAP3430_AUTO_MCBSP5_SHIFT 10
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#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
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#define OMAP3430_AUTO_MCBSP1_SHIFT 9
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#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
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#define OMAP3430ES1_AUTO_FAC_SHIFT 8
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#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
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#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
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#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
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#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
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#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
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#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
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#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
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#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
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#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
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#define OMAP3430ES1_AUTO_D2D_SHIFT 3
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#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
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#define OMAP3430_AUTO_SAD2D_SHIFT 3
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#define OMAP3430_AUTO_SSI_MASK (1 << 0)
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#define OMAP3430_AUTO_SSI_SHIFT 0
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/* CM_AUTOIDLE2_CORE */
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#define OMAP3430_AUTO_PKA_MASK (1 << 4)
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#define OMAP3430_AUTO_PKA_SHIFT 4
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#define OMAP3430_AUTO_AES1_MASK (1 << 3)
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#define OMAP3430_AUTO_AES1_SHIFT 3
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#define OMAP3430_AUTO_RNG_MASK (1 << 2)
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#define OMAP3430_AUTO_RNG_SHIFT 2
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#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
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#define OMAP3430_AUTO_SHA11_SHIFT 1
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#define OMAP3430_AUTO_DES1_MASK (1 << 0)
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#define OMAP3430_AUTO_DES1_SHIFT 0
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/* CM_AUTOIDLE3_CORE */
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#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
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#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
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#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
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#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
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#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
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#define OMAP3430_AUTO_MAD2D_SHIFT 3
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#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
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#define OMAP3430_CLKSEL_SSI_SHIFT 8
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#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
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#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
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#define OMAP3430_CLKSEL_GPT11_SHIFT 7
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#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
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#define OMAP3430_CLKSEL_GPT10_SHIFT 6
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#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
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#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
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#define OMAP3430_CLKSEL_L4_SHIFT 2
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#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
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#define OMAP3430_CLKSEL_L3_SHIFT 0
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#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
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#define OMAP3630_CLKSEL_96M_SHIFT 12
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#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
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/* CM_CLKSTCTRL_CORE */
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#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
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#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
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#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
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#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
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#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
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#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
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/* CM_CLKSTST_CORE */
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#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
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#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
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#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
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#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
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#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
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#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
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#define OMAP3430ES1_EN_3D_MASK (1 << 2)
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#define OMAP3430ES1_EN_3D_SHIFT 2
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#define OMAP3430ES1_EN_2D_MASK (1 << 1)
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#define OMAP3430ES1_EN_2D_SHIFT 1
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/* CM_ICLKEN_GFX specific bits */
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/* CM_IDLEST_GFX specific bits */
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/* CM_CLKSEL_GFX specific bits */
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/* CM_SLEEPDEP_GFX specific bits */
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/* CM_CLKSTCTRL_GFX */
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#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
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#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
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#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
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#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
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#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
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#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
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#define OMAP3430ES2_ST_SGX_SHIFT 1
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#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
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#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
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#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
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#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
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#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
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/* CM_CLKSTCTRL_SGX */
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#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
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#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
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#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
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#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
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/* CM_FCLKEN_WKUP specific bits */
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#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
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#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
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/* CM_ICLKEN_WKUP specific bits */
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#define OMAP3430_EN_WDT1_MASK (1 << 4)
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#define OMAP3430_EN_WDT1_SHIFT 4
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#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
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#define OMAP3430_EN_32KSYNC_SHIFT 2
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/* CM_IDLEST_WKUP specific bits */
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#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
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#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
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#define OMAP3430_ST_WDT2_SHIFT 5
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#define OMAP3430_ST_WDT2_MASK (1 << 5)
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#define OMAP3430_ST_WDT1_SHIFT 4
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#define OMAP3430_ST_WDT1_MASK (1 << 4)
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#define OMAP3430_ST_32KSYNC_SHIFT 2
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#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
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/* CM_AUTOIDLE_WKUP */
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#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
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#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
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#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
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#define OMAP3430_AUTO_WDT2_SHIFT 5
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#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
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#define OMAP3430_AUTO_WDT1_SHIFT 4
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#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
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#define OMAP3430_AUTO_GPIO1_SHIFT 3
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#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
442
#define OMAP3430_AUTO_32KSYNC_SHIFT 2
443
#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
444
#define OMAP3430_AUTO_GPT12_SHIFT 1
445
#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
446
#define OMAP3430_AUTO_GPT1_SHIFT 0
449
#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
450
#define OMAP3430_CLKSEL_RM_SHIFT 1
451
#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
452
#define OMAP3430_CLKSEL_GPT1_SHIFT 0
453
#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
456
#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
457
#define OMAP3430_PWRDN_CAM_SHIFT 30
458
#define OMAP3430_PWRDN_DSS1_SHIFT 29
459
#define OMAP3430_PWRDN_TV_SHIFT 28
460
#define OMAP3430_PWRDN_96M_SHIFT 27
461
#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
462
#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
463
#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
464
#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
465
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
466
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
467
#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
468
#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
469
#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
470
#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
471
#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
472
#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
473
#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
474
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
475
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
476
#define OMAP3430_EN_CORE_DPLL_SHIFT 0
477
#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
480
#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
481
#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
482
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
483
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
484
#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
485
#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
486
#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
488
/* CM_IDLEST_CKGEN */
489
#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
490
#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
491
#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
492
#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
493
#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
494
#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
495
#define OMAP3430_ST_CORE_CLK_SHIFT 0
496
#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
498
/* CM_IDLEST2_CKGEN */
499
#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
500
#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
501
#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
502
#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
503
#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
504
#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
506
/* CM_AUTOIDLE_PLL */
507
#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
508
#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
509
#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
510
#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
512
/* CM_AUTOIDLE2_PLL */
513
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
514
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
517
/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
518
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
519
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
520
#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
521
#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
522
#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
523
#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
524
#define OMAP3430_SOURCE_96M_SHIFT 6
525
#define OMAP3430_SOURCE_96M_MASK (1 << 6)
526
#define OMAP3430_SOURCE_54M_SHIFT 5
527
#define OMAP3430_SOURCE_54M_MASK (1 << 5)
528
#define OMAP3430_SOURCE_48M_SHIFT 3
529
#define OMAP3430_SOURCE_48M_MASK (1 << 3)
532
#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
533
#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
534
#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
535
#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
536
#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
537
#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
538
#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
539
#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
540
#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
543
#define OMAP3430_DIV_96M_SHIFT 0
544
#define OMAP3430_DIV_96M_MASK (0x1f << 0)
545
#define OMAP3630_DIV_96M_MASK (0x3f << 0)
548
#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
549
#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
550
#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
551
#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
554
#define OMAP3430ES2_DIV_120M_SHIFT 0
555
#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
558
#define OMAP3430_CLKOUT2_EN_SHIFT 7
559
#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
560
#define OMAP3430_CLKOUT2_DIV_SHIFT 3
561
#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
562
#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
563
#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
566
#define OMAP3430_EN_TV_MASK (1 << 2)
567
#define OMAP3430_EN_TV_SHIFT 2
568
#define OMAP3430_EN_DSS2_MASK (1 << 1)
569
#define OMAP3430_EN_DSS2_SHIFT 1
570
#define OMAP3430_EN_DSS1_MASK (1 << 0)
571
#define OMAP3430_EN_DSS1_SHIFT 0
574
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
575
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
578
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
579
#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
580
#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
581
#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
582
#define OMAP3430ES1_ST_DSS_SHIFT 0
583
#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
585
/* CM_AUTOIDLE_DSS */
586
#define OMAP3430_AUTO_DSS_MASK (1 << 0)
587
#define OMAP3430_AUTO_DSS_SHIFT 0
590
#define OMAP3430_CLKSEL_TV_SHIFT 8
591
#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
592
#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
593
#define OMAP3430_CLKSEL_DSS1_SHIFT 0
594
#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
595
#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
597
/* CM_SLEEPDEP_DSS specific bits */
599
/* CM_CLKSTCTRL_DSS */
600
#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
601
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
604
#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
605
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
607
/* CM_FCLKEN_CAM specific bits */
608
#define OMAP3430_EN_CSI2_MASK (1 << 1)
609
#define OMAP3430_EN_CSI2_SHIFT 1
611
/* CM_ICLKEN_CAM specific bits */
614
#define OMAP3430_ST_CAM_MASK (1 << 0)
616
/* CM_AUTOIDLE_CAM */
617
#define OMAP3430_AUTO_CAM_MASK (1 << 0)
618
#define OMAP3430_AUTO_CAM_SHIFT 0
621
#define OMAP3430_CLKSEL_CAM_SHIFT 0
622
#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
623
#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
625
/* CM_SLEEPDEP_CAM specific bits */
627
/* CM_CLKSTCTRL_CAM */
628
#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
629
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
632
#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
633
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
635
/* CM_FCLKEN_PER specific bits */
637
/* CM_ICLKEN_PER specific bits */
640
#define OMAP3430_ST_WDT3_SHIFT 12
641
#define OMAP3430_ST_WDT3_MASK (1 << 12)
642
#define OMAP3430_ST_MCBSP4_SHIFT 2
643
#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
644
#define OMAP3430_ST_MCBSP3_SHIFT 1
645
#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
646
#define OMAP3430_ST_MCBSP2_SHIFT 0
647
#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
649
/* CM_AUTOIDLE_PER */
650
#define OMAP3630_AUTO_UART4_MASK (1 << 18)
651
#define OMAP3630_AUTO_UART4_SHIFT 18
652
#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
653
#define OMAP3430_AUTO_GPIO6_SHIFT 17
654
#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
655
#define OMAP3430_AUTO_GPIO5_SHIFT 16
656
#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
657
#define OMAP3430_AUTO_GPIO4_SHIFT 15
658
#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
659
#define OMAP3430_AUTO_GPIO3_SHIFT 14
660
#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
661
#define OMAP3430_AUTO_GPIO2_SHIFT 13
662
#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
663
#define OMAP3430_AUTO_WDT3_SHIFT 12
664
#define OMAP3430_AUTO_UART3_MASK (1 << 11)
665
#define OMAP3430_AUTO_UART3_SHIFT 11
666
#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
667
#define OMAP3430_AUTO_GPT9_SHIFT 10
668
#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
669
#define OMAP3430_AUTO_GPT8_SHIFT 9
670
#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
671
#define OMAP3430_AUTO_GPT7_SHIFT 8
672
#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
673
#define OMAP3430_AUTO_GPT6_SHIFT 7
674
#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
675
#define OMAP3430_AUTO_GPT5_SHIFT 6
676
#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
677
#define OMAP3430_AUTO_GPT4_SHIFT 5
678
#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
679
#define OMAP3430_AUTO_GPT3_SHIFT 4
680
#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
681
#define OMAP3430_AUTO_GPT2_SHIFT 3
682
#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
683
#define OMAP3430_AUTO_MCBSP4_SHIFT 2
684
#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
685
#define OMAP3430_AUTO_MCBSP3_SHIFT 1
686
#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
687
#define OMAP3430_AUTO_MCBSP2_SHIFT 0
690
#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
691
#define OMAP3430_CLKSEL_GPT9_SHIFT 7
692
#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
693
#define OMAP3430_CLKSEL_GPT8_SHIFT 6
694
#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
695
#define OMAP3430_CLKSEL_GPT7_SHIFT 5
696
#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
697
#define OMAP3430_CLKSEL_GPT6_SHIFT 4
698
#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
699
#define OMAP3430_CLKSEL_GPT5_SHIFT 3
700
#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
701
#define OMAP3430_CLKSEL_GPT4_SHIFT 2
702
#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
703
#define OMAP3430_CLKSEL_GPT3_SHIFT 1
704
#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
705
#define OMAP3430_CLKSEL_GPT2_SHIFT 0
707
/* CM_SLEEPDEP_PER specific bits */
708
#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
710
/* CM_CLKSTCTRL_PER */
711
#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
712
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
715
#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
716
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
719
#define OMAP3430_DIV_DPLL4_SHIFT 24
720
#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
721
#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
722
#define OMAP3430_DIV_DPLL3_SHIFT 16
723
#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
724
#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
725
#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
726
#define OMAP3430_CLKSEL_PCLK_SHIFT 8
727
#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
728
#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
729
#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
730
#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
731
#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
732
#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
733
#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
734
#define OMAP3430_MUX_CTRL_SHIFT 0
735
#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
737
/* CM_CLKSTCTRL_EMU */
738
#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
739
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
742
#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
743
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
745
/* CM_CLKSEL2_EMU specific bits */
746
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
747
#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
748
#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
749
#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
751
/* CM_CLKSEL3_EMU specific bits */
752
#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
753
#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
754
#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
755
#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
758
#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
761
#define OMAP3430_ST_NEON_MASK (1 << 0)
763
/* CM_CLKSTCTRL_NEON */
764
#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
765
#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
767
/* CM_FCLKEN_USBHOST */
768
#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
769
#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
770
#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
771
#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
773
/* CM_ICLKEN_USBHOST */
774
#define OMAP3430ES2_EN_USBHOST_SHIFT 0
775
#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
777
/* CM_IDLEST_USBHOST */
778
#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
779
#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
780
#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
781
#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
783
/* CM_AUTOIDLE_USBHOST */
784
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
785
#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
787
/* CM_SLEEPDEP_USBHOST */
788
#define OMAP3430ES2_EN_MPU_SHIFT 1
789
#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
790
#define OMAP3430ES2_EN_IVA2_SHIFT 2
791
#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
793
/* CM_CLKSTCTRL_USBHOST */
794
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
795
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
797
/* CM_CLKSTST_USBHOST */
798
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
799
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
805
/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
806
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
807
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
808
#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
809
#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3