2
* Copyright (C) 2008 Nokia Corporation
3
* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
5
* This program is free software; you can redistribute it and/or modify it
6
* under the terms of the GNU General Public License version 2 as published by
7
* the Free Software Foundation.
9
* This program is distributed in the hope that it will be useful, but WITHOUT
10
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14
* You should have received a copy of the GNU General Public License along with
15
* this program. If not, see <http://www.gnu.org/licenses/>.
18
#ifndef __OMAP_OMAPDSS_H
19
#define __OMAP_OMAPDSS_H
21
#include <linux/list.h>
22
#include <linux/kobject.h>
23
#include <linux/device.h>
25
#define DISPC_IRQ_FRAMEDONE (1 << 0)
26
#define DISPC_IRQ_VSYNC (1 << 1)
27
#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28
#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29
#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30
#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31
#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32
#define DISPC_IRQ_GFX_END_WIN (1 << 7)
33
#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34
#define DISPC_IRQ_OCP_ERR (1 << 9)
35
#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36
#define DISPC_IRQ_VID1_END_WIN (1 << 11)
37
#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38
#define DISPC_IRQ_VID2_END_WIN (1 << 13)
39
#define DISPC_IRQ_SYNC_LOST (1 << 14)
40
#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41
#define DISPC_IRQ_WAKEUP (1 << 16)
42
#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43
#define DISPC_IRQ_VSYNC2 (1 << 18)
44
#define DISPC_IRQ_VID3_END_WIN (1 << 19)
45
#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
46
#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
47
#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
48
#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
49
#define DISPC_IRQ_FRAMEDONETV (1 << 24)
50
#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
52
struct omap_dss_device;
53
struct omap_overlay_manager;
55
enum omap_display_type {
56
OMAP_DISPLAY_TYPE_NONE = 0,
57
OMAP_DISPLAY_TYPE_DPI = 1 << 0,
58
OMAP_DISPLAY_TYPE_DBI = 1 << 1,
59
OMAP_DISPLAY_TYPE_SDI = 1 << 2,
60
OMAP_DISPLAY_TYPE_DSI = 1 << 3,
61
OMAP_DISPLAY_TYPE_VENC = 1 << 4,
62
OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
73
OMAP_DSS_CHANNEL_LCD = 0,
74
OMAP_DSS_CHANNEL_DIGIT = 1,
75
OMAP_DSS_CHANNEL_LCD2 = 2,
78
enum omap_color_mode {
79
OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
80
OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
81
OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
82
OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
83
OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
84
OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
85
OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
86
OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
87
OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
88
OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
89
OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
90
OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
91
OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
92
OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
93
OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
94
OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
95
OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
96
OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
97
OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
100
enum omap_lcd_display_type {
101
OMAP_DSS_LCD_DISPLAY_STN,
102
OMAP_DSS_LCD_DISPLAY_TFT,
105
enum omap_dss_load_mode {
106
OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
107
OMAP_DSS_LOAD_CLUT_ONLY = 1,
108
OMAP_DSS_LOAD_FRAME_ONLY = 2,
109
OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
112
enum omap_dss_trans_key_type {
113
OMAP_DSS_COLOR_KEY_GFX_DST = 0,
114
OMAP_DSS_COLOR_KEY_VID_SRC = 1,
117
enum omap_rfbi_te_mode {
118
OMAP_DSS_RFBI_TE_MODE_1 = 1,
119
OMAP_DSS_RFBI_TE_MODE_2 = 2,
122
enum omap_panel_config {
123
OMAP_DSS_LCD_IVS = 1<<0,
124
OMAP_DSS_LCD_IHS = 1<<1,
125
OMAP_DSS_LCD_IPC = 1<<2,
126
OMAP_DSS_LCD_IEO = 1<<3,
127
OMAP_DSS_LCD_RF = 1<<4,
128
OMAP_DSS_LCD_ONOFF = 1<<5,
130
OMAP_DSS_LCD_TFT = 1<<20,
133
enum omap_dss_venc_type {
134
OMAP_DSS_VENC_TYPE_COMPOSITE,
135
OMAP_DSS_VENC_TYPE_SVIDEO,
138
enum omap_dss_dsi_pixel_format {
139
OMAP_DSS_DSI_FMT_RGB888,
140
OMAP_DSS_DSI_FMT_RGB666,
141
OMAP_DSS_DSI_FMT_RGB666_PACKED,
142
OMAP_DSS_DSI_FMT_RGB565,
145
enum omap_dss_dsi_mode {
146
OMAP_DSS_DSI_CMD_MODE = 0,
147
OMAP_DSS_DSI_VIDEO_MODE,
150
enum omap_display_caps {
151
OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
152
OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
155
enum omap_dss_display_state {
156
OMAP_DSS_DISPLAY_DISABLED = 0,
157
OMAP_DSS_DISPLAY_ACTIVE,
158
OMAP_DSS_DISPLAY_SUSPENDED,
161
/* XXX perhaps this should be removed */
162
enum omap_dss_overlay_managers {
163
OMAP_DSS_OVL_MGR_LCD,
165
OMAP_DSS_OVL_MGR_LCD2,
168
enum omap_dss_rotation_type {
169
OMAP_DSS_ROT_DMA = 0,
170
OMAP_DSS_ROT_VRFB = 1,
173
/* clockwise rotation angle */
174
enum omap_dss_rotation_angle {
177
OMAP_DSS_ROT_180 = 2,
178
OMAP_DSS_ROT_270 = 3,
181
enum omap_overlay_caps {
182
OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
183
OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
184
OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
185
OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
188
enum omap_overlay_manager_caps {
189
OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
192
enum omap_dss_clk_source {
193
OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
195
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
196
* OMAP4: PLL1_CLK1 */
197
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
198
* OMAP4: PLL1_CLK2 */
199
OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
200
OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
205
struct rfbi_timings {
219
u32 tim[5]; /* set by rfbi_convert_timings() */
224
void omap_rfbi_write_command(const void *buf, u32 len);
225
void omap_rfbi_read_data(void *buf, u32 len);
226
void omap_rfbi_write_data(const void *buf, u32 len);
227
void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
230
int omap_rfbi_enable_te(bool enable, unsigned line);
231
int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
232
unsigned hs_pulse_time, unsigned vs_pulse_time,
233
int hs_pol_inv, int vs_pol_inv, int extif_div);
234
void rfbi_bus_lock(void);
235
void rfbi_bus_unlock(void);
239
struct omap_dss_dsi_videomode_data {
240
/* DSI video mode blanking data */
241
/* Unit: byte clock cycles */
245
/* Unit: line clocks */
250
/* DSI blanking modes */
252
int hsa_blanking_mode;
253
int hbp_blanking_mode;
254
int hfp_blanking_mode;
256
/* Video port sync events */
263
bool ddr_clk_always_on;
267
void dsi_bus_lock(struct omap_dss_device *dssdev);
268
void dsi_bus_unlock(struct omap_dss_device *dssdev);
269
int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
271
int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
273
int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
274
int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
275
int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
277
int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
279
int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
280
u8 param1, u8 param2);
281
int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
283
int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
285
int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
286
u8 *buf, int buflen);
287
int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
289
int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
290
u8 *buf, int buflen);
291
int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
292
u8 param1, u8 param2, u8 *buf, int buflen);
293
int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
295
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
296
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
297
int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel);
298
void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel);
300
/* Board specific data */
301
struct omap_dss_board_info {
302
int (*get_context_loss_count)(struct device *dev);
304
struct omap_dss_device **devices;
305
struct omap_dss_device *default_device;
306
int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
307
void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
310
/* Init with the board info */
311
extern int omap_display_init(struct omap_dss_board_info *board_data);
313
struct omap_display_platform_data {
314
struct omap_dss_board_info *board_data;
315
/* TODO: Additional members to be added when PM is considered */
318
struct omap_video_timings {
325
/* Unit: pixel clocks */
326
u16 hsw; /* Horizontal synchronization pulse width */
327
/* Unit: pixel clocks */
328
u16 hfp; /* Horizontal front porch */
329
/* Unit: pixel clocks */
330
u16 hbp; /* Horizontal back porch */
331
/* Unit: line clocks */
332
u16 vsw; /* Vertical synchronization pulse width */
333
/* Unit: line clocks */
334
u16 vfp; /* Vertical front porch */
335
/* Unit: line clocks */
336
u16 vbp; /* Vertical back porch */
339
#ifdef CONFIG_OMAP2_DSS_VENC
340
/* Hardcoded timings for tv modes. Venc only uses these to
341
* identify the mode, and does not actually use the configs
342
* itself. However, the configs should be something that
343
* a normal monitor can also show */
344
extern const struct omap_video_timings omap_dss_pal_timings;
345
extern const struct omap_video_timings omap_dss_ntsc_timings;
348
struct omap_dss_cpr_coefs {
354
struct omap_overlay_info {
358
u32 p_uv_addr; /* for NV12 format */
362
enum omap_color_mode color_mode;
364
enum omap_dss_rotation_type rotation_type;
369
u16 out_width; /* if 0, out_width == width */
370
u16 out_height; /* if 0, out_height == height */
376
struct omap_overlay {
378
struct list_head list;
383
enum omap_color_mode supported_modes;
384
enum omap_overlay_caps caps;
387
struct omap_overlay_manager *manager;
388
struct omap_overlay_info info;
390
bool manager_changed;
391
/* if true, info has been changed, but not applied() yet */
394
int (*set_manager)(struct omap_overlay *ovl,
395
struct omap_overlay_manager *mgr);
396
int (*unset_manager)(struct omap_overlay *ovl);
398
int (*set_overlay_info)(struct omap_overlay *ovl,
399
struct omap_overlay_info *info);
400
void (*get_overlay_info)(struct omap_overlay *ovl,
401
struct omap_overlay_info *info);
403
int (*wait_for_go)(struct omap_overlay *ovl);
406
struct omap_overlay_manager_info {
409
enum omap_dss_trans_key_type trans_key_type;
413
bool partial_alpha_enabled;
416
struct omap_dss_cpr_coefs cpr_coefs;
419
struct omap_overlay_manager {
421
struct list_head list;
425
enum omap_channel id;
426
enum omap_overlay_manager_caps caps;
428
struct omap_overlay **overlays;
429
enum omap_display_type supported_displays;
432
struct omap_dss_device *device;
433
struct omap_overlay_manager_info info;
436
/* if true, info has been changed but not applied() yet */
439
int (*set_device)(struct omap_overlay_manager *mgr,
440
struct omap_dss_device *dssdev);
441
int (*unset_device)(struct omap_overlay_manager *mgr);
443
int (*set_manager_info)(struct omap_overlay_manager *mgr,
444
struct omap_overlay_manager_info *info);
445
void (*get_manager_info)(struct omap_overlay_manager *mgr,
446
struct omap_overlay_manager_info *info);
448
int (*apply)(struct omap_overlay_manager *mgr);
449
int (*wait_for_go)(struct omap_overlay_manager *mgr);
450
int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
452
int (*enable)(struct omap_overlay_manager *mgr);
453
int (*disable)(struct omap_overlay_manager *mgr);
456
struct omap_dss_device {
459
enum omap_display_type type;
461
enum omap_channel channel;
496
enum omap_dss_venc_type type;
497
bool invert_polarity;
506
enum omap_dss_clk_source lcd_clk_src;
509
enum omap_dss_clk_source dispc_fclk_src;
513
/* regn is one greater than TRM's REGN value */
520
enum omap_dss_clk_source dsi_fclk_src;
524
/* regn is one greater than TRM's REGN value */
531
struct omap_video_timings timings;
533
int acbi; /* ac-bias pin transitions per interrupt */
534
/* Unit: line clocks */
535
int acb; /* ac-bias pin frequency */
537
enum omap_panel_config config;
539
enum omap_dss_dsi_pixel_format dsi_pix_fmt;
540
enum omap_dss_dsi_mode dsi_mode;
541
struct omap_dss_dsi_videomode_data dsi_vm_data;
546
struct rfbi_timings rfbi_timings;
551
int max_backlight_level;
555
/* used to match device to driver */
556
const char *driver_name;
560
struct omap_dss_driver *driver;
562
/* helper variable for driver suspend/resume */
563
bool activate_after_resume;
565
enum omap_display_caps caps;
567
struct omap_overlay_manager *manager;
569
enum omap_dss_display_state state;
571
/* platform specific */
572
int (*platform_enable)(struct omap_dss_device *dssdev);
573
void (*platform_disable)(struct omap_dss_device *dssdev);
574
int (*set_backlight)(struct omap_dss_device *dssdev, int level);
575
int (*get_backlight)(struct omap_dss_device *dssdev);
578
struct omap_dss_driver {
579
struct device_driver driver;
581
int (*probe)(struct omap_dss_device *);
582
void (*remove)(struct omap_dss_device *);
584
int (*enable)(struct omap_dss_device *display);
585
void (*disable)(struct omap_dss_device *display);
586
int (*suspend)(struct omap_dss_device *display);
587
int (*resume)(struct omap_dss_device *display);
588
int (*run_test)(struct omap_dss_device *display, int test);
590
int (*update)(struct omap_dss_device *dssdev,
591
u16 x, u16 y, u16 w, u16 h);
592
int (*sync)(struct omap_dss_device *dssdev);
594
int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
595
int (*get_te)(struct omap_dss_device *dssdev);
597
u8 (*get_rotate)(struct omap_dss_device *dssdev);
598
int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
600
bool (*get_mirror)(struct omap_dss_device *dssdev);
601
int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
603
int (*memory_read)(struct omap_dss_device *dssdev,
604
void *buf, size_t size,
605
u16 x, u16 y, u16 w, u16 h);
607
void (*get_resolution)(struct omap_dss_device *dssdev,
608
u16 *xres, u16 *yres);
609
void (*get_dimensions)(struct omap_dss_device *dssdev,
610
u32 *width, u32 *height);
611
int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
613
int (*check_timings)(struct omap_dss_device *dssdev,
614
struct omap_video_timings *timings);
615
void (*set_timings)(struct omap_dss_device *dssdev,
616
struct omap_video_timings *timings);
617
void (*get_timings)(struct omap_dss_device *dssdev,
618
struct omap_video_timings *timings);
620
int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
621
u32 (*get_wss)(struct omap_dss_device *dssdev);
623
int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
624
bool (*detect)(struct omap_dss_device *dssdev);
627
int omap_dss_register_driver(struct omap_dss_driver *);
628
void omap_dss_unregister_driver(struct omap_dss_driver *);
630
void omap_dss_get_device(struct omap_dss_device *dssdev);
631
void omap_dss_put_device(struct omap_dss_device *dssdev);
632
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
633
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
634
struct omap_dss_device *omap_dss_find_device(void *data,
635
int (*match)(struct omap_dss_device *dssdev, void *data));
637
int omap_dss_start_device(struct omap_dss_device *dssdev);
638
void omap_dss_stop_device(struct omap_dss_device *dssdev);
640
int omap_dss_get_num_overlay_managers(void);
641
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
643
int omap_dss_get_num_overlays(void);
644
struct omap_overlay *omap_dss_get_overlay(int num);
646
void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
647
u16 *xres, u16 *yres);
648
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
650
typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
651
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
652
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
654
int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
655
int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
656
unsigned long timeout);
658
#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
659
#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
661
void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
663
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
665
int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
666
u16 *x, u16 *y, u16 *w, u16 *h,
667
bool enlarge_update_area);
668
int omap_dsi_update(struct omap_dss_device *dssdev,
670
u16 x, u16 y, u16 w, u16 h,
671
void (*callback)(int, void *), void *data);
672
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
673
int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
674
void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
676
int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
677
void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
678
bool disconnect_lanes, bool enter_ulps);
680
int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
681
void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
682
void dpi_set_timings(struct omap_dss_device *dssdev,
683
struct omap_video_timings *timings);
684
int dpi_check_timings(struct omap_dss_device *dssdev,
685
struct omap_video_timings *timings);
687
int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
688
void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
690
int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
691
void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
692
int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
693
u16 *x, u16 *y, u16 *w, u16 *h);
694
int omap_rfbi_update(struct omap_dss_device *dssdev,
695
u16 x, u16 y, u16 w, u16 h,
696
void (*callback)(void *), void *data);
697
int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,