2
* linux/arch/arm/mach-pxa/irq.c
4
* Generic PXA IRQ handling
6
* Author: Nicolas Pitre
7
* Created: Jun 15, 2001
8
* Copyright: MontaVista Software Inc.
10
* This program is free software; you can redistribute it and/or modify
11
* it under the terms of the GNU General Public License version 2 as
12
* published by the Free Software Foundation.
14
#include <linux/init.h>
15
#include <linux/module.h>
16
#include <linux/interrupt.h>
17
#include <linux/syscore_ops.h>
19
#include <linux/irq.h>
21
#include <asm/exception.h>
23
#include <mach/hardware.h>
24
#include <mach/irqs.h>
25
#include <mach/gpio-pxa.h>
29
#define IRQ_BASE io_p2v(0x40d00000)
38
#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
39
((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
40
(0x144 + (((i) - 64) << 2)))
41
#define ICHP_VAL_IRQ (1 << 31)
42
#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
43
#define IPR_VALID (1 << 31)
44
#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
46
#define MAX_INTERNAL_IRQS 128
49
* This is for peripheral IRQs internal to the PXA chip.
52
static int pxa_internal_irq_nr;
54
static inline int cpu_has_ipr(void)
56
return !cpu_is_pxa25x();
59
static inline void __iomem *irq_base(int i)
61
static unsigned long phys_base[] = {
67
return io_p2v(phys_base[i]);
70
void pxa_mask_irq(struct irq_data *d)
72
void __iomem *base = irq_data_get_irq_chip_data(d);
73
uint32_t icmr = __raw_readl(base + ICMR);
75
icmr &= ~(1 << IRQ_BIT(d->irq));
76
__raw_writel(icmr, base + ICMR);
79
void pxa_unmask_irq(struct irq_data *d)
81
void __iomem *base = irq_data_get_irq_chip_data(d);
82
uint32_t icmr = __raw_readl(base + ICMR);
84
icmr |= 1 << IRQ_BIT(d->irq);
85
__raw_writel(icmr, base + ICMR);
88
static struct irq_chip pxa_internal_irq_chip = {
90
.irq_ack = pxa_mask_irq,
91
.irq_mask = pxa_mask_irq,
92
.irq_unmask = pxa_unmask_irq,
96
* GPIO IRQs for GPIO 0 and 1
98
static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
100
int gpio = d->irq - IRQ_GPIO0;
102
if (__gpio_is_occupied(gpio)) {
103
pr_err("%s failed: GPIO is configured\n", __func__);
107
if (type & IRQ_TYPE_EDGE_RISING)
108
GRER0 |= GPIO_bit(gpio);
110
GRER0 &= ~GPIO_bit(gpio);
112
if (type & IRQ_TYPE_EDGE_FALLING)
113
GFER0 |= GPIO_bit(gpio);
115
GFER0 &= ~GPIO_bit(gpio);
120
static void pxa_ack_low_gpio(struct irq_data *d)
122
GEDR0 = (1 << (d->irq - IRQ_GPIO0));
125
static struct irq_chip pxa_low_gpio_chip = {
127
.irq_ack = pxa_ack_low_gpio,
128
.irq_mask = pxa_mask_irq,
129
.irq_unmask = pxa_unmask_irq,
130
.irq_set_type = pxa_set_low_gpio_type,
133
asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
135
uint32_t icip, icmr, mask;
138
icip = __raw_readl(IRQ_BASE + ICIP);
139
icmr = __raw_readl(IRQ_BASE + ICMR);
145
handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
149
asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
154
__asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
156
if ((ichp & ICHP_VAL_IRQ) == 0)
159
handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
163
static void __init pxa_init_low_gpio_irq(set_wake_t fn)
167
/* clear edge detection on GPIO 0 and 1 */
172
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
173
irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
175
irq_set_chip_data(irq, irq_base(0));
176
set_irq_flags(irq, IRQF_VALID);
179
pxa_low_gpio_chip.irq_set_wake = fn;
182
void __init pxa_init_irq(int irq_nr, set_wake_t fn)
186
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
188
pxa_internal_irq_nr = irq_nr;
190
for (n = 0; n < irq_nr; n += 32) {
191
void __iomem *base = irq_base(n >> 5);
193
__raw_writel(0, base + ICMR); /* disable all IRQs */
194
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
195
for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
196
/* initialize interrupt priority */
198
__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
201
irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
203
irq_set_chip_data(irq, base);
204
set_irq_flags(irq, IRQF_VALID);
208
/* only unmasked interrupts kick us out of idle */
209
__raw_writel(1, irq_base(0) + ICCR);
211
pxa_internal_irq_chip.irq_set_wake = fn;
212
pxa_init_low_gpio_irq(fn);
216
static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
217
static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
219
static int pxa_irq_suspend(void)
223
for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
224
void __iomem *base = irq_base(i);
226
saved_icmr[i] = __raw_readl(base + ICMR);
227
__raw_writel(0, base + ICMR);
231
for (i = 0; i < pxa_internal_irq_nr; i++)
232
saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
238
static void pxa_irq_resume(void)
242
for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
243
void __iomem *base = irq_base(i);
245
__raw_writel(saved_icmr[i], base + ICMR);
246
__raw_writel(0, base + ICLR);
250
for (i = 0; i < pxa_internal_irq_nr; i++)
251
__raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
253
__raw_writel(1, IRQ_BASE + ICCR);
256
#define pxa_irq_suspend NULL
257
#define pxa_irq_resume NULL
260
struct syscore_ops pxa_irq_syscore_ops = {
261
.suspend = pxa_irq_suspend,
262
.resume = pxa_irq_resume,