3
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
5
* (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
11
/* general, but fairly heavy, debugging */
14
/* heavy debugging: */
15
/* -- logs putc[s], so every time a char is displayed, it's logged */
16
#undef MATROXFB_DEBUG_HEAVY
18
/* This one _could_ cause infinite loops */
19
/* It _does_ cause lots and lots of messages during idle loops */
20
#undef MATROXFB_DEBUG_LOOP
22
/* Debug register calls, too? */
23
#undef MATROXFB_DEBUG_REG
25
/* Guard accelerator accesses with spin_lock_irqsave... */
26
#undef MATROXFB_USE_SPINLOCKS
28
#include <linux/module.h>
29
#include <linux/kernel.h>
30
#include <linux/errno.h>
31
#include <linux/string.h>
33
#include <linux/slab.h>
34
#include <linux/delay.h>
36
#include <linux/console.h>
37
#include <linux/selection.h>
38
#include <linux/ioport.h>
39
#include <linux/init.h>
40
#include <linux/timer.h>
41
#include <linux/pci.h>
42
#include <linux/spinlock.h>
46
#include <asm/unaligned.h>
51
#if defined(CONFIG_PPC_PMAC)
53
#include <asm/pci-bridge.h>
54
#include "../macmodes.h"
60
#define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
62
#ifdef MATROXFB_DEBUG_HEAVY
63
#define DBG_HEAVY(x) DBG(x)
64
#else /* MATROXFB_DEBUG_HEAVY */
65
#define DBG_HEAVY(x) /* DBG_HEAVY */
66
#endif /* MATROXFB_DEBUG_HEAVY */
68
#ifdef MATROXFB_DEBUG_LOOP
69
#define DBG_LOOP(x) DBG(x)
70
#else /* MATROXFB_DEBUG_LOOP */
71
#define DBG_LOOP(x) /* DBG_LOOP */
72
#endif /* MATROXFB_DEBUG_LOOP */
74
#ifdef MATROXFB_DEBUG_REG
75
#define DBG_REG(x) DBG(x)
76
#else /* MATROXFB_DEBUG_REG */
77
#define DBG_REG(x) /* DBG_REG */
78
#endif /* MATROXFB_DEBUG_REG */
80
#else /* MATROXFB_DEBUG */
82
#define DBG(x) /* DBG */
83
#define DBG_HEAVY(x) /* DBG_HEAVY */
84
#define DBG_REG(x) /* DBG_REG */
85
#define DBG_LOOP(x) /* DBG_LOOP */
87
#endif /* MATROXFB_DEBUG */
90
#define dprintk(X...) printk(X)
95
#ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
96
#define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
98
#ifndef PCI_SS_VENDOR_ID_MATROX
99
#define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
102
#ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
103
#define PCI_SS_ID_MATROX_GENERIC 0xFF00
104
#define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
105
#define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
106
#define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
107
#define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
108
#define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
109
#define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
110
#define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
111
#define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
112
#define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
115
#define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
116
#define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
117
#define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
119
#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
121
/* G-series and Mystique have (almost) same DAC */
123
#if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
124
#define NEED_DAC1064 1
131
static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
132
return readb(va.vaddr + offs);
135
static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
136
writeb(value, va.vaddr + offs);
139
static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
140
writew(value, va.vaddr + offs);
143
static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
144
return readl(va.vaddr + offs);
147
static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
148
writel(value, va.vaddr + offs);
151
static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
152
#if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
154
* iowrite32_rep works for us if:
155
* (1) Copies data as 32bit quantities, not byte after byte,
156
* (2) Performs LE ordered stores, and
157
* (3) It copes with unaligned source (destination is guaranteed to be page
158
* aligned and length is guaranteed to be multiple of 4).
160
iowrite32_rep(va.vaddr, src, len >> 2);
162
u_int32_t __iomem* addr = va.vaddr;
164
if ((unsigned long)src & 3) {
166
fb_writel(get_unaligned((u32 *)src), addr);
173
fb_writel(*(u32 *)src, addr);
182
static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
186
static inline void __iomem* vaddr_va(vaddr_t va) {
190
#define MGA_IOREMAP_NORMAL 0
191
#define MGA_IOREMAP_NOCACHE 1
193
#define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
194
#define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
195
static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
196
if (flags & MGA_IOREMAP_NOCACHE)
197
virt->vaddr = ioremap_nocache(phys, size);
199
virt->vaddr = ioremap(phys, size);
200
return (virt->vaddr == NULL); /* 0, !0... 0, error_code in future */
203
static inline void mga_iounmap(vaddr_t va) {
208
unsigned int pixclock;
211
unsigned int HDisplay;
212
unsigned int HSyncStart;
213
unsigned int HSyncEnd;
215
unsigned int VDisplay;
216
unsigned int VSyncStart;
217
unsigned int VSyncEnd;
222
unsigned int delay; /* CRTC delay */
225
enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
227
struct matrox_pll_cache {
230
unsigned int mnp_key;
231
unsigned int mnp_value;
235
struct matrox_pll_limits {
240
struct matrox_pll_features {
241
unsigned int vco_freq_min;
242
unsigned int ref_freq;
243
unsigned int feed_div_min;
244
unsigned int feed_div_max;
245
unsigned int in_div_min;
246
unsigned int in_div_max;
247
unsigned int post_shift_max;
252
unsigned int final_bppShift;
253
unsigned int cmap_len;
261
struct matrox_fb_info;
263
struct matrox_DAC1064_features {
268
/* current hardware status */
280
struct matrox_crtc2 {
284
struct matrox_hw_state {
285
u_int32_t MXoptionReg;
286
unsigned char DACclk[6];
287
unsigned char DACreg[80];
288
unsigned char MiscOutReg;
289
unsigned char DACpal[768];
290
unsigned char CRTC[25];
291
unsigned char CRTCEXT[9];
292
unsigned char SEQ[5];
293
/* unused for MGA mode, but who knows... */
294
unsigned char GCTL[9];
295
/* unused for MGA mode, but who knows... */
296
unsigned char ATTR[21];
299
struct mavenregs maven;
301
struct matrox_crtc2 crtc2;
304
struct matrox_accel_data {
305
#ifdef CONFIG_FB_MATROX_MILLENIUM
306
unsigned char ramdac_rev;
308
u_int32_t m_dwg_rect;
312
struct v4l2_queryctrl;
315
struct matrox_altout {
317
int (*compute)(void* altout_dev, struct my_timming* input);
318
int (*program)(void* altout_dev);
319
int (*start)(void* altout_dev);
320
int (*verifymode)(void* altout_dev, u_int32_t mode);
321
int (*getqueryctrl)(void* altout_dev,
322
struct v4l2_queryctrl* ctrl);
323
int (*getctrl)(void* altout_dev,
324
struct v4l2_control* ctrl);
325
int (*setctrl)(void* altout_dev,
326
struct v4l2_control* ctrl);
329
#define MATROXFB_SRC_NONE 0
330
#define MATROXFB_SRC_CRTC1 1
331
#define MATROXFB_SRC_CRTC2 2
333
enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
336
unsigned int bios_valid : 1;
337
unsigned int pins_len;
338
unsigned char pins[128];
340
unsigned char vMaj, vMin, vRev;
343
unsigned char state, tvout;
347
struct matrox_switch;
348
struct matroxfb_driver;
349
struct matroxfb_dh_fb_info;
351
struct matrox_vsync {
352
wait_queue_head_t wait;
356
struct matrox_fb_info {
357
struct fb_info fbcon;
359
struct list_head next_fb;
363
unsigned int usecount;
365
unsigned int userusecount;
366
unsigned long irq_flags;
368
struct matroxfb_par curr;
369
struct matrox_hw_state hw;
371
struct matrox_accel_data accel;
373
struct pci_dev* pcidev;
376
struct matrox_vsync vsync;
377
unsigned int pixclock;
382
struct matrox_vsync vsync;
383
unsigned int pixclock;
385
struct matroxfb_dh_fb_info* info;
386
struct rw_semaphore lock;
389
struct rw_semaphore lock;
391
int brightness, contrast, saturation, hue, gamma;
392
int testout, deflicker;
395
#define MATROXFB_MAX_OUTPUTS 3
398
struct matrox_altout* output;
401
unsigned int default_src;
402
} outputs[MATROXFB_MAX_OUTPUTS];
404
#define MATROXFB_MAX_FB_DRIVERS 5
405
struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
406
void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
407
unsigned int drivers_count;
410
unsigned long base; /* physical */
411
vaddr_t vbase; /* CPU view */
413
unsigned int len_usable;
414
unsigned int len_maximum;
418
unsigned long base; /* physical */
419
vaddr_t vbase; /* CPU view */
423
unsigned int max_pixel_clock;
424
unsigned int max_pixel_clock_panellink;
426
struct matrox_switch* hw_switch;
429
struct matrox_pll_features pll;
430
struct matrox_DAC1064_features DAC1064;
471
unsigned int vgastep;
472
unsigned int textmode;
473
unsigned int textstep;
474
unsigned int textvram; /* character cells */
475
unsigned int ydstorg; /* offset in bytes from video start to usable memory */
476
/* 0 except for 6MB Millenium */
480
int panellink; /* G400 DFP possible (not G450/G550) */
482
unsigned int fbResource;
485
struct matrox_bios bios;
487
struct matrox_pll_limits pixel;
488
struct matrox_pll_limits system;
489
struct matrox_pll_limits video;
492
struct matrox_pll_cache pixel;
493
struct matrox_pll_cache system;
494
struct matrox_pll_cache video;
506
u_int32_t mctlwtst_core;
520
#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
522
struct matrox_switch {
523
int (*preinit)(struct matrox_fb_info *minfo);
524
void (*reset)(struct matrox_fb_info *minfo);
525
int (*init)(struct matrox_fb_info *minfo, struct my_timming*);
526
void (*restore)(struct matrox_fb_info *minfo);
529
struct matroxfb_driver {
530
struct list_head node;
532
void* (*probe)(struct matrox_fb_info* info);
533
void (*remove)(struct matrox_fb_info* info, void* data);
536
int matroxfb_register_driver(struct matroxfb_driver* drv);
537
void matroxfb_unregister_driver(struct matroxfb_driver* drv);
539
#define PCI_OPTION_REG 0x40
540
#define PCI_OPTION_ENABLE_ROM 0x40000000
542
#define PCI_MGA_INDEX 0x44
543
#define PCI_MGA_DATA 0x48
544
#define PCI_OPTION2_REG 0x50
545
#define PCI_OPTION3_REG 0x54
546
#define PCI_MEMMISC_REG 0x58
548
#define M_DWGCTL 0x1C00
549
#define M_MACCESS 0x1C04
550
#define M_CTLWTST 0x1C08
552
#define M_PLNWT 0x1C1C
554
#define M_BCOL 0x1C20
555
#define M_FCOL 0x1C24
567
#define M_CXBNDRY 0x1C80
568
#define M_FXBNDRY 0x1C84
569
#define M_YDSTLEN 0x1C88
570
#define M_PITCH 0x1C8C
571
#define M_YDST 0x1C90
572
#define M_YDSTORG 0x1C94
573
#define M_YTOP 0x1C98
574
#define M_YBOT 0x1C9C
577
#define M_CACHEFLUSH 0x1FFF
579
#define M_EXEC 0x0100
581
#define M_DWG_TRAP 0x04
582
#define M_DWG_BITBLT 0x08
583
#define M_DWG_ILOAD 0x09
585
#define M_DWG_LINEAR 0x0080
586
#define M_DWG_SOLID 0x0800
587
#define M_DWG_ARZERO 0x1000
588
#define M_DWG_SGNZERO 0x2000
589
#define M_DWG_SHIFTZERO 0x4000
591
#define M_DWG_REPLACE 0x000C0000
592
#define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
593
#define M_DWG_XOR 0x00060010
595
#define M_DWG_BFCOL 0x04000000
596
#define M_DWG_BMONOWF 0x08000000
598
#define M_DWG_TRANSC 0x40000000
600
#define M_FIFOSTATUS 0x1E10
601
#define M_STATUS 0x1E14
602
#define M_ICLEAR 0x1E18
605
#define M_VCOUNT 0x1E20
607
#define M_RESET 0x1E40
608
#define M_MEMRDBK 0x1E44
610
#define M_AGP2PLL 0x1E4C
612
#define M_OPMODE 0x1E54
613
#define M_OPMODE_DMA_GEN_WRITE 0x00
614
#define M_OPMODE_DMA_BLIT 0x04
615
#define M_OPMODE_DMA_VECTOR_WRITE 0x08
616
#define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
617
#define M_OPMODE_DMA_BE_8BPP 0x0000
618
#define M_OPMODE_DMA_BE_16BPP 0x0100
619
#define M_OPMODE_DMA_BE_32BPP 0x0200
620
#define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
621
#define M_OPMODE_DIR_BE_8BPP 0x000000
622
#define M_OPMODE_DIR_BE_16BPP 0x010000
623
#define M_OPMODE_DIR_BE_32BPP 0x020000
625
#define M_ATTR_INDEX 0x1FC0
626
#define M_ATTR_DATA 0x1FC1
628
#define M_MISC_REG 0x1FC2
629
#define M_3C2_RD 0x1FC2
631
#define M_SEQ_INDEX 0x1FC4
632
#define M_SEQ_DATA 0x1FC5
634
#define M_SEQ1_SCROFF 0x20
636
#define M_MISC_REG_READ 0x1FCC
638
#define M_GRAPHICS_INDEX 0x1FCE
639
#define M_GRAPHICS_DATA 0x1FCF
641
#define M_CRTC_INDEX 0x1FD4
643
#define M_ATTR_RESET 0x1FDA
644
#define M_3DA_WR 0x1FDA
645
#define M_INSTS1 0x1FDA
647
#define M_EXTVGA_INDEX 0x1FDE
648
#define M_EXTVGA_DATA 0x1FDF
651
#define M_SRCORG 0x2CB4
652
#define M_DSTORG 0x2CB8
654
#define M_RAMDAC_BASE 0x3C00
656
/* fortunately, same on TVP3026 and MGA1064 */
657
#define M_DAC_REG (M_RAMDAC_BASE+0)
658
#define M_DAC_VAL (M_RAMDAC_BASE+1)
659
#define M_PALETTE_MASK (M_RAMDAC_BASE+2)
661
#define M_X_INDEX 0x00
662
#define M_X_DATAREG 0x0A
664
#define DAC_XGENIOCTRL 0x2A
665
#define DAC_XGENIODATA 0x2B
667
#define M_C2CTL 0x3C10
669
#define MX_OPTION_BSWAP 0x00000000
671
#ifdef __LITTLE_ENDIAN
672
#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
673
#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
674
#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
675
#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
676
#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
679
#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
680
#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
681
#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
682
#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
683
#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
685
#error "Byte ordering have to be defined. Cannot continue."
689
#define mga_inb(addr) mga_readb(minfo->mmio.vbase, (addr))
690
#define mga_inl(addr) mga_readl(minfo->mmio.vbase, (addr))
691
#define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val))
692
#define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val))
693
#define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val))
694
#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
695
#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
697
#define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
699
#define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
702
#ifdef CONFIG_FB_MATROX_MILLENIUM
703
#define isInterleave(x) (x->interleave)
704
#define isMillenium(x) (x->millenium)
705
#define isMilleniumII(x) (x->milleniumII)
707
#define isInterleave(x) (0)
708
#define isMillenium(x) (0)
709
#define isMilleniumII(x) (0)
712
#define matroxfb_DAC_lock() spin_lock(&minfo->lock.DAC)
713
#define matroxfb_DAC_unlock() spin_unlock(&minfo->lock.DAC)
714
#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&minfo->lock.DAC, flags)
715
#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags)
716
extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg,
718
extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg);
719
extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
720
extern int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc);
721
extern int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable);
723
#ifdef MATROXFB_USE_SPINLOCKS
724
#define CRITBEGIN spin_lock_irqsave(&minfo->lock.accel, critflags);
725
#define CRITEND spin_unlock_irqrestore(&minfo->lock.accel, critflags);
726
#define CRITFLAGS unsigned long critflags;
733
#endif /* __MATROXFB_H__ */