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#ifndef __iop_crc_par_defs_h
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#define __iop_crc_par_defs_h
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* This file is autogenerated from
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* file: ../../inst/io_proc/rtl/iop_crc_par.r
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* last modfied: Mon Apr 11 16:08:45 2005
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
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* id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
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* Any changes here will be lost.
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* -*- buffer-read-only: t -*-
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/* Main access macros */
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#define reg_page_size 8192
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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/* C-code for register scope iop_crc_par */
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/* Register rw_cfg, scope iop_crc_par, type rw */
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unsigned int mode : 1;
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unsigned int crc_out : 1;
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unsigned int rev_out : 1;
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unsigned int inv_out : 1;
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unsigned int trig : 2;
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unsigned int poly : 3;
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unsigned int dummy1 : 23;
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} reg_iop_crc_par_rw_cfg;
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#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
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#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
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/* Register rw_init_crc, scope iop_crc_par, type rw */
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typedef unsigned int reg_iop_crc_par_rw_init_crc;
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#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
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#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
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/* Register rw_correct_crc, scope iop_crc_par, type rw */
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typedef unsigned int reg_iop_crc_par_rw_correct_crc;
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#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
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#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
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/* Register rw_ctrl, scope iop_crc_par, type rw */
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unsigned int dummy1 : 31;
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} reg_iop_crc_par_rw_ctrl;
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#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
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#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
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/* Register rw_set_last, scope iop_crc_par, type rw */
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unsigned int tr_dif : 1;
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unsigned int dummy1 : 31;
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} reg_iop_crc_par_rw_set_last;
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#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
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#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
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/* Register rw_wr1byte, scope iop_crc_par, type rw */
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unsigned int data : 8;
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unsigned int dummy1 : 24;
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} reg_iop_crc_par_rw_wr1byte;
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#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
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#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
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/* Register rw_wr2byte, scope iop_crc_par, type rw */
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unsigned int data : 16;
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unsigned int dummy1 : 16;
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} reg_iop_crc_par_rw_wr2byte;
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#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
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#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
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/* Register rw_wr3byte, scope iop_crc_par, type rw */
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unsigned int data : 24;
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unsigned int dummy1 : 8;
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} reg_iop_crc_par_rw_wr3byte;
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#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
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#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
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/* Register rw_wr4byte, scope iop_crc_par, type rw */
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unsigned int data : 32;
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} reg_iop_crc_par_rw_wr4byte;
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#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
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#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
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/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
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unsigned int data : 8;
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unsigned int dummy1 : 24;
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} reg_iop_crc_par_rw_wr1byte_last;
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#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
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#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
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/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
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unsigned int data : 16;
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unsigned int dummy1 : 16;
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} reg_iop_crc_par_rw_wr2byte_last;
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#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
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#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
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/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
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unsigned int data : 24;
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unsigned int dummy1 : 8;
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} reg_iop_crc_par_rw_wr3byte_last;
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#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
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#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
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/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
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unsigned int data : 32;
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} reg_iop_crc_par_rw_wr4byte_last;
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#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
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#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
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/* Register r_stat, scope iop_crc_par, type r */
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unsigned int err : 1;
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unsigned int busy : 1;
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unsigned int dummy1 : 30;
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} reg_iop_crc_par_r_stat;
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#define REG_RD_ADDR_iop_crc_par_r_stat 52
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/* Register r_sh_reg, scope iop_crc_par, type r */
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typedef unsigned int reg_iop_crc_par_r_sh_reg;
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#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
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/* Register r_crc, scope iop_crc_par, type r */
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typedef unsigned int reg_iop_crc_par_r_crc;
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#define REG_RD_ADDR_iop_crc_par_r_crc 60
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/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
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unsigned int last : 2;
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unsigned int dummy1 : 30;
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} reg_iop_crc_par_rw_strb_rec_dif_in;
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#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
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#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
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regk_iop_crc_par_calc = 0x00000001,
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regk_iop_crc_par_ccitt = 0x00000002,
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regk_iop_crc_par_check = 0x00000000,
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regk_iop_crc_par_crc16 = 0x00000001,
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regk_iop_crc_par_crc32 = 0x00000000,
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regk_iop_crc_par_crc5 = 0x00000003,
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regk_iop_crc_par_crc5_11 = 0x00000004,
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regk_iop_crc_par_dif_in = 0x00000002,
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regk_iop_crc_par_hi = 0x00000000,
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regk_iop_crc_par_neg = 0x00000002,
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regk_iop_crc_par_no = 0x00000000,
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regk_iop_crc_par_pos = 0x00000001,
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regk_iop_crc_par_pos_neg = 0x00000003,
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regk_iop_crc_par_rw_cfg_default = 0x00000000,
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regk_iop_crc_par_rw_ctrl_default = 0x00000000,
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regk_iop_crc_par_yes = 0x00000001
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#endif /* __iop_crc_par_defs_h */