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* Copyright (c) 2010 Broadcom Corporation
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/kthread.h>
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#include <linux/printk.h>
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#include <linux/pci_ids.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/sdio_func.h>
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#include <linux/mmc/card.h>
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#include <linux/semaphore.h>
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <asm/unaligned.h>
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#include <brcmu_wifi.h>
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#include <brcmu_utils.h>
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#include <brcm_hw_ids.h>
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#include "sdio_host.h"
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#define DCMD_RESP_TIMEOUT 2000 /* In milli second */
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#define BRCMF_TRAP_INFO_SIZE 80
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#define CBUF_LEN (128)
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__le32 buf; /* Can't be pointer on (64-bit) hosts */
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char *_buf_compat; /* Redundant pointer for backward compat. */
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* When there is no UART (e.g. Quickturn),
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* the host should write a complete
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* input line directly into cbuf and then write
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* the length into vcons_in.
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* This may also be used when there is a real UART
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* (at risk of conflicting with
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* the real UART). vcons_out is currently unused.
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/* Output (logging) buffer
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* Console output is written to a ring buffer log_buf at index log_idx.
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* The host may read the output when it sees log_idx advance.
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* Output will be lost if the output wraps around faster than the host
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struct rte_log_le log_le;
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/* Console input line buffer
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* Characters are read one at a time into cbuf
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* until <CR> is received, then
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* the buffer is processed as a command line.
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* Also used for virtual UART.
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#include <chipcommon.h>
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#include "dhd_proto.h"
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#define TXQLEN 2048 /* bulk tx queue length */
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#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
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#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
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#define TXRETRIES 2 /* # of retries for tx frames */
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#define BRCMF_RXBOUND 50 /* Default for max rx frames in
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#define BRCMF_TXBOUND 20 /* Default for max tx frames in
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#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
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#define MEMBLOCK 2048 /* Block size used for downloading
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#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
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biggest possible glom */
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#define BRCMF_FIRSTREAD (1 << 6)
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/* SBSDIO_DEVICE_CTL */
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/* 1: device will assert busy signal when receiving CMD53 */
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#define SBSDIO_DEVCTL_SETBUSY 0x01
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/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
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#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
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/* 1: mask all interrupts to host except the chipActive (rev 8) */
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#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
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/* 1: isolate internal sdio signals, put external pads in tri-state; requires
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* sdio bus power cycle to clear (rev 9) */
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#define SBSDIO_DEVCTL_PADS_ISO 0x08
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/* Force SD->SB reset mapping (rev 11) */
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#define SBSDIO_DEVCTL_SB_RST_CTL 0x30
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/* Determined by CoreControl bit */
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#define SBSDIO_DEVCTL_RST_CORECTL 0x00
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/* Force backplane reset */
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#define SBSDIO_DEVCTL_RST_BPRESET 0x10
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/* Force no backplane reset */
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#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
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/* SBSDIO_FUNC1_CHIPCLKCSR */
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/* Force ALP request to backplane */
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#define SBSDIO_FORCE_ALP 0x01
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/* Force HT request to backplane */
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#define SBSDIO_FORCE_HT 0x02
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/* Force ILP request to backplane */
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#define SBSDIO_FORCE_ILP 0x04
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/* Make ALP ready (power up xtal) */
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#define SBSDIO_ALP_AVAIL_REQ 0x08
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/* Make HT ready (power up PLL) */
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#define SBSDIO_HT_AVAIL_REQ 0x10
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/* Squelch clock requests from HW */
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#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
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/* Status: ALP is ready */
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#define SBSDIO_ALP_AVAIL 0x40
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/* Status: HT is ready */
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#define SBSDIO_HT_AVAIL 0x80
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#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
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#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
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#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
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#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
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#define SBSDIO_CLKAV(regval, alponly) \
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(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
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/* direct(mapped) cis space */
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/* MAPPED common CIS address */
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#define SBSDIO_CIS_BASE_COMMON 0x1000
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/* maximum bytes in one CIS */
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#define SBSDIO_CIS_SIZE_LIMIT 0x200
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/* cis offset addr is < 17 bits */
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#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
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/* manfid tuple length, include tuple, link bytes */
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#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
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#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
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#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
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#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
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#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
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#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
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#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
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#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
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#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
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#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
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#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
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#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
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#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
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#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
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#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
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#define I_PC (1 << 10) /* descriptor error */
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#define I_PD (1 << 11) /* data error */
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#define I_DE (1 << 12) /* Descriptor protocol Error */
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#define I_RU (1 << 13) /* Receive descriptor Underflow */
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#define I_RO (1 << 14) /* Receive fifo Overflow */
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#define I_XU (1 << 15) /* Transmit fifo Underflow */
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#define I_RI (1 << 16) /* Receive Interrupt */
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#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
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#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
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#define I_XI (1 << 24) /* Transmit Interrupt */
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#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
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#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
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#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
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#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
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#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
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#define I_SRESET (1 << 30) /* CCCR RES interrupt */
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#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
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#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
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#define I_DMA (I_RI | I_XI | I_ERRORS)
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#define CC_CISRDY (1 << 0) /* CIS Ready */
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#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
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#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
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#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
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#define CC_XMTDATAAVAIL_MODE (1 << 4)
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#define CC_XMTDATAAVAIL_CTRL (1 << 5)
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#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
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#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
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#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
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#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
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#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
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/* Total length of frame header for dongle protocol */
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#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
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#define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
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* Software allocation of To SB Mailbox resources
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/* tosbmailbox bits corresponding to intstatus bits */
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#define SMB_NAK (1 << 0) /* Frame NAK */
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#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
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#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
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#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
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/* tosbmailboxdata */
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#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
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* Software allocation of To Host Mailbox resources
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#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
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#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
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#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
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#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
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/* tohostmailboxdata */
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#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
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#define HMB_DATA_DEVREADY 2 /* talk to host after enable */
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#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
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#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
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#define HMB_DATA_FCDATA_MASK 0xff000000
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#define HMB_DATA_FCDATA_SHIFT 24
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#define HMB_DATA_VERSION_MASK 0x00ff0000
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#define HMB_DATA_VERSION_SHIFT 16
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* Software-defined protocol header
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/* Current protocol version */
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#define SDPCM_PROT_VERSION 4
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/* SW frame header */
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#define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
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#define SDPCM_CHANNEL_MASK 0x00000f00
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#define SDPCM_CHANNEL_SHIFT 8
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#define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
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#define SDPCM_NEXTLEN_OFFSET 2
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/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
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#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
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#define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
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#define SDPCM_DOFFSET_MASK 0xff000000
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#define SDPCM_DOFFSET_SHIFT 24
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#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
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#define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
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#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
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#define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
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#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
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/* logical channel numbers */
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#define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
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#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
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#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
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#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
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#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
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#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
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#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
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* Shared structure between dongle and the host.
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* The structure contains pointers to trap or assert information.
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#define SDPCM_SHARED_VERSION 0x0002
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#define SDPCM_SHARED_VERSION_MASK 0x00FF
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#define SDPCM_SHARED_ASSERT_BUILT 0x0100
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#define SDPCM_SHARED_ASSERT 0x0200
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#define SDPCM_SHARED_TRAP 0x0400
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/* Space for header read, limit for data packets */
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#define MAX_HDR_READ (1 << 6)
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#define MAX_RX_DATASZ 2048
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/* Maximum milliseconds to wait for F2 to come up */
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#define BRCMF_WAIT_F2RDY 3000
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/* Bump up limit on waiting for HT to account for first startup;
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* if the image is doing a CRC calculation before programming the PMU
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* for HT availability, it could take a couple hundred ms more, so
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* max out at a 1 second (1000000us).
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#undef PMU_MAX_TRANSITION_DLY
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#define PMU_MAX_TRANSITION_DLY 1000000
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/* Value for ChipClockCSR during initial setup */
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#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
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SBSDIO_ALP_AVAIL_REQ)
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/* Flags for SDH calls */
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#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
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#define SBIM_IBE 0x20000 /* inbanderror */
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#define SBIM_TO 0x40000 /* timeout */
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#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
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#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
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#define SBTML_RESET 0x0001
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#define SBTML_REJ_MASK 0x0006
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#define SBTML_REJ 0x0002
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/* temporary reject, for error recovery */
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#define SBTML_TMPREJ 0x0004
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/* Shift to locate the SI control flags in sbtml */
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#define SBTML_SICF_SHIFT 16
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#define SBTMH_SERR 0x0001 /* serror */
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#define SBTMH_INT 0x0002 /* interrupt */
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#define SBTMH_BUSY 0x0004 /* busy */
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#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
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/* Shift to locate the SI status flags in sbtmh */
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#define SBTMH_SISF_SHIFT 16
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#define SBIDL_INIT 0x80 /* initiator */
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#define SBIDH_RC_MASK 0x000f /* revision code */
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#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
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#define SBIDH_RCE_SHIFT 8
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#define SBCOREREV(sbidh) \
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((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
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((sbidh) & SBIDH_RC_MASK))
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#define SBIDH_CC_MASK 0x8ff0 /* core code */
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#define SBIDH_CC_SHIFT 4
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#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
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#define SBIDH_VC_SHIFT 16
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* Conversion of 802.1D priority to precedence level
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static uint prio2prec(u32 prio)
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return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
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* Core reg address translation.
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* Both macro's returns a 32 bits byte address on the backplane bus.
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#define CORE_CC_REG(base, field) \
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(base + offsetof(struct chipcregs, field))
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#define CORE_BUS_REG(base, field) \
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(base + offsetof(struct sdpcmd_regs, field))
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#define CORE_SB(base, field) \
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(base + SBCONFIGOFF + offsetof(struct sbconfig, field))
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u32 corecontrol; /* 0x00, rev8 */
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u32 corestatus; /* rev8 */
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u32 biststatus; /* rev8 */
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u16 pcmciamesportaladdr; /* 0x010, rev8 */
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u16 pcmciamesportalmask; /* rev8 */
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u16 pcmciawrframebc; /* rev8 */
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u16 pcmciaunderflowtimer; /* rev8 */
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u32 intstatus; /* 0x020, rev8 */
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u32 hostintmask; /* rev8 */
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u32 intmask; /* rev8 */
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u32 sbintstatus; /* rev8 */
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u32 sbintmask; /* rev8 */
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u32 funcintmask; /* rev4 */
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u32 tosbmailbox; /* 0x040, rev8 */
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u32 tohostmailbox; /* rev8 */
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u32 tosbmailboxdata; /* rev8 */
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u32 tohostmailboxdata; /* rev8 */
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/* synchronized access to registers in SDIO clock domain */
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u32 sdioaccess; /* 0x050, rev8 */
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/* PCMCIA frame control */
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u8 pcmciaframectrl; /* 0x060, rev8 */
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u8 pcmciawatermark; /* rev8 */
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/* interrupt batching control */
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u32 intrcvlazy; /* 0x100, rev8 */
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u32 cmd52rd; /* 0x110, rev8 */
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u32 cmd52wr; /* rev8 */
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u32 cmd53rd; /* rev8 */
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u32 cmd53wr; /* rev8 */
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u32 abort; /* rev8 */
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u32 datacrcerror; /* rev8 */
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u32 rdoutofsync; /* rev8 */
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u32 wroutofsync; /* rev8 */
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u32 writebusy; /* rev8 */
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u32 readwait; /* rev8 */
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u32 readterm; /* rev8 */
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u32 writeterm; /* rev8 */
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u32 clockctlstatus; /* rev8 */
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u32 PAD[128]; /* DMA engines */
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/* SDIO/PCMCIA CIS region */
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char cis[512]; /* 0x400-0x5ff, rev6 */
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/* PCMCIA function control registers */
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char pcmciafcr[256]; /* 0x600-6ff, rev6 */
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/* PCMCIA backplane access */
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u16 backplanecsr; /* 0x76E, rev6 */
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u16 backplaneaddr0; /* rev6 */
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u16 backplaneaddr1; /* rev6 */
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u16 backplaneaddr2; /* rev6 */
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u16 backplaneaddr3; /* rev6 */
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u16 backplanedata0; /* rev6 */
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u16 backplanedata1; /* rev6 */
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u16 backplanedata2; /* rev6 */
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u16 backplanedata3; /* rev6 */
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/* sprom "size" & "blank" info */
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u16 spromstatus; /* 0x7BE, rev2 */
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/* Device console log buffer state */
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struct brcmf_console {
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uint count; /* Poll interval msec counter */
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uint log_addr; /* Log struct address (fixed) */
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struct rte_log_le log_le; /* Log struct (host copy) */
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uint bufsize; /* Size of log buffer */
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u8 *buf; /* Log buffer (host copy) */
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uint last; /* Last buffer read index */
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struct sdpcm_shared {
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u32 assert_file_addr;
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u32 console_addr; /* Address of struct rte_console */
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struct sdpcm_shared_le {
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__le32 assert_exp_addr;
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__le32 assert_file_addr;
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__le32 console_addr; /* Address of struct rte_console */
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__le32 msgtrace_addr;
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/* misc chip info needed by some of the routines */
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u32 buscorebase; /* 32 bits backplane bus address */
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/* Private data for SDIO bus interaction */
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struct brcmf_pub *drvr;
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struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
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struct chip_info *ci; /* Chip info struct */
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char *vars; /* Variables (from CIS and/or other) */
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uint varsz; /* Size of variables buffer */
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u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
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u32 hostintmask; /* Copy of Host Interrupt Mask */
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u32 intstatus; /* Intstatus bits (events) pending */
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bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
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bool fcstate; /* State of dongle flow-control */
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uint blocksize; /* Block size of SDIO transfers */
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uint roundup; /* Max roundup limit */
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struct pktq txq; /* Queue length used for flow-control */
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u8 flowcontrol; /* per prio flow control bitmask */
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u8 tx_seq; /* Transmit sequence number (next) */
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u8 tx_max; /* Maximum transmit sequence allowed */
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u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
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u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
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u16 nextlen; /* Next Read Len from last header */
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u8 rx_seq; /* Receive sequence number (expected) */
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bool rxskip; /* Skip receive (awaiting NAK ACK) */
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uint rxbound; /* Rx frames to read before resched */
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uint txbound; /* Tx frames to send before resched */
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struct sk_buff *glomd; /* Packet containing glomming descriptor */
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struct sk_buff *glom; /* Packet chain for glommed superframe */
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uint glomerr; /* Glom packet read errors */
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u8 *rxbuf; /* Buffer for receiving control packets */
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uint rxblen; /* Allocated length of rxbuf */
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u8 *rxctl; /* Aligned pointer into rxbuf */
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u8 *databuf; /* Buffer for receiving big glom packet */
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u8 *dataptr; /* Aligned pointer into databuf */
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uint rxlen; /* Length of valid data in buffer */
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u8 sdpcm_ver; /* Bus protocol reported by dongle */
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bool intr; /* Use interrupts */
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bool poll; /* Use polling */
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bool ipend; /* Device interrupt is pending */
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uint intrcount; /* Count of device interrupt callbacks */
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uint lastintrs; /* Count as of last watchdog timer */
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uint spurious; /* Count of spurious interrupts */
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uint pollrate; /* Ticks between device polls */
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uint polltick; /* Tick counter */
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uint pollcnt; /* Count of active polls */
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uint console_interval;
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struct brcmf_console console; /* Console output polling support */
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uint console_addr; /* Console address from shared struct */
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uint regfails; /* Count of R_REG failures */
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uint clkstate; /* State of sd and backplane clock(s) */
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bool activity; /* Activity flag for clock down */
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s32 idletime; /* Control for activity timeout */
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s32 idlecount; /* Activity timeout counter */
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s32 idleclock; /* How to set bus driver when idle */
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bool use_rxchain; /* If brcmf should use PKT chains */
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bool sleeping; /* Is SDIO bus sleeping? */
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bool rxflow_mode; /* Rx flow control mode */
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bool rxflow; /* Is rx flow control on */
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bool alp_only; /* Don't use HT clock (ALP only) */
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/* Field to decide if rx of control frames happen in rxbuf or lb-pool */
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/* Some additional counters */
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uint tx_sderrs; /* Count of tx attempts with sd errors */
623
uint fcqueued; /* Tx packets that got queued */
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uint rxrtx; /* Count of rtx requests (NAK to dongle) */
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uint rx_toolong; /* Receive frames too long to receive */
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uint rxc_errors; /* SDIO errors when reading control frames */
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uint rx_hdrfail; /* SDIO errors on header reads */
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uint rx_badhdr; /* Bad received headers (roosync?) */
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uint rx_badseq; /* Mismatched rx sequence number */
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uint fc_rcvd; /* Number of flow-control events received */
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uint fc_xoff; /* Number which turned on flow-control */
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uint fc_xon; /* Number which turned off flow-control */
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uint rxglomfail; /* Failed deglom attempts */
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uint rxglomframes; /* Number of glom frames (superframes) */
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uint rxglompkts; /* Number of packets from glom frames */
636
uint f2rxhdrs; /* Number of header reads */
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uint f2rxdata; /* Number of frame data reads */
638
uint f2txdata; /* Number of f2 frame writes */
639
uint f1regdata; /* Number of f1 register accesses */
643
bool ctrl_frame_stat;
646
wait_queue_head_t ctrl_wait;
647
wait_queue_head_t dcmd_resp_wait;
649
struct timer_list timer;
650
struct completion watchdog_wait;
651
struct task_struct *watchdog_tsk;
655
struct task_struct *dpc_tsk;
656
struct completion dpc_wait;
658
struct semaphore sdsem;
661
const struct firmware *firmware;
668
u32 sbipsflag; /* initiator port ocp slave flag */
670
u32 sbtpsflag; /* target port ocp slave flag */
672
u32 sbtmerrloga; /* (sonics >= 2.3) */
674
u32 sbtmerrlog; /* (sonics >= 2.3) */
676
u32 sbadmatch3; /* address match3 */
678
u32 sbadmatch2; /* address match2 */
680
u32 sbadmatch1; /* address match1 */
682
u32 sbimstate; /* initiator agent state */
683
u32 sbintvec; /* interrupt mask */
684
u32 sbtmstatelow; /* target state */
685
u32 sbtmstatehigh; /* target state */
686
u32 sbbwa0; /* bandwidth allocation table0 */
688
u32 sbimconfiglow; /* initiator configuration */
689
u32 sbimconfighigh; /* initiator configuration */
690
u32 sbadmatch0; /* address match0 */
692
u32 sbtmconfiglow; /* target configuration */
693
u32 sbtmconfighigh; /* target configuration */
694
u32 sbbconfig; /* broadcast configuration */
696
u32 sbbstate; /* broadcast state */
698
u32 sbactcnfg; /* activate configuration */
700
u32 sbflagst; /* current sbflags */
702
u32 sbidlow; /* identification */
703
u32 sbidhigh; /* identification */
709
#define CLK_PENDING 2 /* Not used yet */
713
static int qcount[NUMPRIO];
714
static int tx_packets[NUMPRIO];
717
#define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
719
#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
721
/* Retry count for register access failures */
722
static const uint retry_limit = 2;
724
/* Limit on rounding up frames */
725
static const uint max_roundup = 512;
729
static void pkt_align(struct sk_buff *p, int len, int align)
732
datalign = (unsigned long)(p->data);
733
datalign = roundup(datalign, (align)) - datalign;
735
skb_pull(p, datalign);
739
/* To check if there's window offered */
740
static bool data_ok(struct brcmf_bus *bus)
742
return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
743
((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
747
* Reads a register in the SDIO hardware block. This block occupies a series of
748
* adresses on the 32 bit backplane bus.
751
r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
755
*regvar = brcmf_sdcard_reg_read(bus->sdiodev,
756
bus->ci->buscorebase + reg_offset, sizeof(u32));
757
} while (brcmf_sdcard_regfail(bus->sdiodev) &&
758
(++(*retryvar) <= retry_limit));
760
bus->regfails += (*retryvar-1);
761
if (*retryvar > retry_limit) {
762
brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
769
w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
773
brcmf_sdcard_reg_write(bus->sdiodev,
774
bus->ci->buscorebase + reg_offset,
775
sizeof(u32), regval);
776
} while (brcmf_sdcard_regfail(bus->sdiodev) &&
777
(++(*retryvar) <= retry_limit));
779
bus->regfails += (*retryvar-1);
780
if (*retryvar > retry_limit)
781
brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
786
#define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
788
#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
790
/* Packet free applicable unconditionally for sdio and sdspi.
791
* Conditional if bufpool was present for gspi bus.
793
static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
796
brcmu_pkt_buf_free_skb(pkt);
799
/* Turn backplane clock on or off */
800
static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
803
u8 clkctl, clkreq, devctl;
804
unsigned long timeout;
806
brcmf_dbg(TRACE, "Enter\n");
811
/* Request HT Avail */
813
bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
815
if ((bus->ci->chip == BCM4329_CHIP_ID)
816
&& (bus->ci->chiprev == 0))
817
clkreq |= SBSDIO_FORCE_ALP;
819
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
820
SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
822
brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
826
if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
827
&& (bus->ci->buscorerev == 9))) {
829
r_sdreg32(bus, &dummy,
830
offsetof(struct sdpcmd_regs, clockctlstatus),
834
/* Check current status */
835
clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
836
SBSDIO_FUNC1_CHIPCLKCSR, &err);
838
brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
842
/* Go to pending and await interrupt if appropriate */
843
if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
844
/* Allow only clock-available interrupt */
845
devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
847
SBSDIO_DEVICE_CTL, &err);
849
brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
854
devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
855
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
856
SBSDIO_DEVICE_CTL, devctl, &err);
857
brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
858
bus->clkstate = CLK_PENDING;
861
} else if (bus->clkstate == CLK_PENDING) {
862
/* Cancel CA-only interrupt filter */
864
brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
865
SBSDIO_DEVICE_CTL, &err);
866
devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
867
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
868
SBSDIO_DEVICE_CTL, devctl, &err);
871
/* Otherwise, wait here (polling) for HT Avail */
873
msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
874
while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
875
clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
877
SBSDIO_FUNC1_CHIPCLKCSR,
879
if (time_after(jiffies, timeout))
882
usleep_range(5000, 10000);
885
brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
888
if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
889
brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
890
PMU_MAX_TRANSITION_DLY, clkctl);
894
/* Mark clock available */
895
bus->clkstate = CLK_AVAIL;
896
brcmf_dbg(INFO, "CLKCTL: turned ON\n");
899
if (bus->alp_only != true) {
900
if (SBSDIO_ALPONLY(clkctl))
901
brcmf_dbg(ERROR, "HT Clock should be on\n");
903
#endif /* defined (BCMDBG) */
905
bus->activity = true;
909
if (bus->clkstate == CLK_PENDING) {
910
/* Cancel CA-only interrupt filter */
911
devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
913
SBSDIO_DEVICE_CTL, &err);
914
devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
915
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
916
SBSDIO_DEVICE_CTL, devctl, &err);
919
bus->clkstate = CLK_SDONLY;
920
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
921
SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
922
brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
924
brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
932
/* Change idle/active SD state */
933
static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
935
brcmf_dbg(TRACE, "Enter\n");
938
bus->clkstate = CLK_SDONLY;
940
bus->clkstate = CLK_NONE;
945
/* Transition SD and backplane clock readiness */
946
static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
949
uint oldstate = bus->clkstate;
952
brcmf_dbg(TRACE, "Enter\n");
954
/* Early exit if we're already there */
955
if (bus->clkstate == target) {
956
if (target == CLK_AVAIL) {
957
brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
958
bus->activity = true;
965
/* Make sure SD clock is available */
966
if (bus->clkstate == CLK_NONE)
967
brcmf_sdbrcm_sdclk(bus, true);
968
/* Now request HT Avail on the backplane */
969
brcmf_sdbrcm_htclk(bus, true, pendok);
970
brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
971
bus->activity = true;
975
/* Remove HT request, or bring up SD clock */
976
if (bus->clkstate == CLK_NONE)
977
brcmf_sdbrcm_sdclk(bus, true);
978
else if (bus->clkstate == CLK_AVAIL)
979
brcmf_sdbrcm_htclk(bus, false, false);
981
brcmf_dbg(ERROR, "request for %d -> %d\n",
982
bus->clkstate, target);
983
brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
987
/* Make sure to remove HT request */
988
if (bus->clkstate == CLK_AVAIL)
989
brcmf_sdbrcm_htclk(bus, false, false);
990
/* Now remove the SD clock */
991
brcmf_sdbrcm_sdclk(bus, false);
992
brcmf_sdbrcm_wd_timer(bus, 0);
996
brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
1002
static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1006
brcmf_dbg(INFO, "request %s (currently %s)\n",
1007
sleep ? "SLEEP" : "WAKE",
1008
bus->sleeping ? "SLEEP" : "WAKE");
1010
/* Done if we're already in the requested state */
1011
if (sleep == bus->sleeping)
1014
/* Going to sleep: set the alarm and turn off the lights... */
1016
/* Don't sleep if something is pending */
1017
if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1020
/* Make sure the controller has the bus up */
1021
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1023
/* Tell device to start using OOB wakeup */
1024
w_sdreg32(bus, SMB_USE_OOB,
1025
offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1026
if (retries > retry_limit)
1027
brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1029
/* Turn off our contribution to the HT clock request */
1030
brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1032
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1033
SBSDIO_FUNC1_CHIPCLKCSR,
1034
SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1036
/* Isolate the bus */
1037
if (bus->ci->chip != BCM4329_CHIP_ID) {
1038
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1040
SBSDIO_DEVCTL_PADS_ISO, NULL);
1044
bus->sleeping = true;
1047
/* Waking up: bus power up is ok, set local state */
1049
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1050
SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1052
/* Force pad isolation off if possible
1053
(in case power never toggled) */
1054
if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1055
&& (bus->ci->buscorerev >= 10))
1056
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1057
SBSDIO_DEVICE_CTL, 0, NULL);
1059
/* Make sure the controller has the bus up */
1060
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1062
/* Send misc interrupt to indicate OOB not needed */
1063
w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1065
if (retries <= retry_limit)
1066
w_sdreg32(bus, SMB_DEV_INT,
1067
offsetof(struct sdpcmd_regs, tosbmailbox),
1070
if (retries > retry_limit)
1071
brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1073
/* Make sure we have SD bus access */
1074
brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1077
bus->sleeping = false;
1083
static void bus_wake(struct brcmf_bus *bus)
1086
brcmf_sdbrcm_bussleep(bus, false);
1089
static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
1096
brcmf_dbg(TRACE, "Enter\n");
1098
/* Read mailbox data and ack that we did so */
1099
r_sdreg32(bus, &hmb_data,
1100
offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
1102
if (retries <= retry_limit)
1103
w_sdreg32(bus, SMB_INT_ACK,
1104
offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1105
bus->f1regdata += 2;
1107
/* Dongle recomposed rx frames, accept them again */
1108
if (hmb_data & HMB_DATA_NAKHANDLED) {
1109
brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
1112
brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
1114
bus->rxskip = false;
1115
intstatus |= I_HMB_FRAME_IND;
1119
* DEVREADY does not occur with gSPI.
1121
if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1123
(hmb_data & HMB_DATA_VERSION_MASK) >>
1124
HMB_DATA_VERSION_SHIFT;
1125
if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1126
brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
1128
bus->sdpcm_ver, SDPCM_PROT_VERSION);
1130
brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
1135
* Flow Control has been moved into the RX headers and this out of band
1136
* method isn't used any more.
1137
* remaining backward compatible with older dongles.
1139
if (hmb_data & HMB_DATA_FC) {
1140
fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1141
HMB_DATA_FCDATA_SHIFT;
1143
if (fcbits & ~bus->flowcontrol)
1146
if (bus->flowcontrol & ~fcbits)
1150
bus->flowcontrol = fcbits;
1153
/* Shouldn't be any others */
1154
if (hmb_data & ~(HMB_DATA_DEVREADY |
1155
HMB_DATA_NAKHANDLED |
1158
HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1159
brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1165
static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1172
brcmf_dbg(ERROR, "%sterminate frame%s\n",
1173
abort ? "abort command, " : "",
1174
rtx ? ", send NAK" : "");
1177
brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1179
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1180
SBSDIO_FUNC1_FRAMECTRL,
1184
/* Wait until the packet has been flushed (device/FIFO stable) */
1185
for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1186
hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1187
SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1188
lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1189
SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1190
bus->f1regdata += 2;
1192
if ((hi == 0) && (lo == 0))
1195
if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1196
brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1197
lastrbc, (hi << 8) + lo);
1199
lastrbc = (hi << 8) + lo;
1203
brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1205
brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1209
w_sdreg32(bus, SMB_NAK,
1210
offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1213
if (retries <= retry_limit)
1217
/* Clear partial in any case */
1220
/* If we can't reach the device, signal failure */
1221
if (err || brcmf_sdcard_regfail(bus->sdiodev))
1222
bus->drvr->busstate = BRCMF_BUS_DOWN;
1225
static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1231
struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
1234
u8 chan, seq, doff, sfdoff;
1238
bool usechain = bus->use_rxchain;
1240
/* If packets, issue read(s) and send up packet chain */
1241
/* Return sequence numbers consumed? */
1243
brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom);
1245
/* If there's a descriptor, generate the packet chain */
1247
pfirst = plast = pnext = NULL;
1248
dlen = (u16) (bus->glomd->len);
1249
dptr = bus->glomd->data;
1250
if (!dlen || (dlen & 1)) {
1251
brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1256
for (totlen = num = 0; dlen; num++) {
1257
/* Get (and move past) next length */
1258
sublen = get_unaligned_le16(dptr);
1259
dlen -= sizeof(u16);
1260
dptr += sizeof(u16);
1261
if ((sublen < SDPCM_HDRLEN) ||
1262
((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1263
brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1268
if (sublen % BRCMF_SDALIGN) {
1269
brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1270
sublen, BRCMF_SDALIGN);
1275
/* For last frame, adjust read len so total
1276
is a block multiple */
1279
(roundup(totlen, bus->blocksize) - totlen);
1280
totlen = roundup(totlen, bus->blocksize);
1283
/* Allocate/chain packet for next subframe */
1284
pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1285
if (pnext == NULL) {
1286
brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1291
pfirst = plast = pnext;
1293
plast->next = pnext;
1297
/* Adhere to start alignment requirements */
1298
pkt_align(pnext, sublen, BRCMF_SDALIGN);
1301
/* If all allocations succeeded, save packet chain
1304
brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1306
if (BRCMF_GLOM_ON() && bus->nextlen &&
1307
totlen != bus->nextlen) {
1308
brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1309
bus->nextlen, totlen, rxseq);
1312
pfirst = pnext = NULL;
1315
brcmu_pkt_buf_free_skb(pfirst);
1320
/* Done with descriptor packet */
1321
brcmu_pkt_buf_free_skb(bus->glomd);
1326
/* Ok -- either we just generated a packet chain,
1327
or had one from before */
1329
if (BRCMF_GLOM_ON()) {
1330
brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1331
for (pnext = bus->glom; pnext; pnext = pnext->next) {
1332
brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1333
pnext, (u8 *) (pnext->data),
1334
pnext->len, pnext->len);
1339
dlen = (u16) brcmu_pkttotlen(pfirst);
1341
/* Do an SDIO read for the superframe. Configurable iovar to
1342
* read directly into the chained packet, or allocate a large
1343
* packet and and copy into the chain.
1346
errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1347
bus->sdiodev->sbwad,
1349
F2SYNC, (u8 *) pfirst->data, dlen,
1351
} else if (bus->dataptr) {
1352
errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1353
bus->sdiodev->sbwad,
1355
F2SYNC, bus->dataptr, dlen,
1357
sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
1359
if (sublen != dlen) {
1360
brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1366
brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1372
/* On failure, kill the superframe, allow a couple retries */
1374
brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1376
bus->drvr->rx_errors++;
1378
if (bus->glomerr++ < 3) {
1379
brcmf_sdbrcm_rxfail(bus, true, true);
1382
brcmf_sdbrcm_rxfail(bus, true, false);
1383
brcmu_pkt_buf_free_skb(bus->glom);
1390
if (BRCMF_GLOM_ON()) {
1391
printk(KERN_DEBUG "SUPERFRAME:\n");
1392
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1393
pfirst->data, min_t(int, pfirst->len, 48));
1397
/* Validate the superframe header */
1398
dptr = (u8 *) (pfirst->data);
1399
sublen = get_unaligned_le16(dptr);
1400
check = get_unaligned_le16(dptr + sizeof(u16));
1402
chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1403
seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1404
bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1405
if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1406
brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1410
doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1411
txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1414
if ((u16)~(sublen ^ check)) {
1415
brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1418
} else if (roundup(sublen, bus->blocksize) != dlen) {
1419
brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1420
sublen, roundup(sublen, bus->blocksize),
1423
} else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1424
SDPCM_GLOM_CHANNEL) {
1425
brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1426
SDPCM_PACKET_CHANNEL(
1427
&dptr[SDPCM_FRAMETAG_LEN]));
1429
} else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1430
brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1432
} else if ((doff < SDPCM_HDRLEN) ||
1433
(doff > (pfirst->len - SDPCM_HDRLEN))) {
1434
brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1435
doff, sublen, pfirst->len, SDPCM_HDRLEN);
1439
/* Check sequence number of superframe SW header */
1441
brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1447
/* Check window for sanity */
1448
if ((u8) (txmax - bus->tx_seq) > 0x40) {
1449
brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1450
txmax, bus->tx_seq);
1451
txmax = bus->tx_seq + 2;
1453
bus->tx_max = txmax;
1455
/* Remove superframe header, remember offset */
1456
skb_pull(pfirst, doff);
1459
/* Validate all the subframe headers */
1460
for (num = 0, pnext = pfirst; pnext && !errcode;
1461
num++, pnext = pnext->next) {
1462
dptr = (u8 *) (pnext->data);
1463
dlen = (u16) (pnext->len);
1464
sublen = get_unaligned_le16(dptr);
1465
check = get_unaligned_le16(dptr + sizeof(u16));
1466
chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1467
doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1469
if (BRCMF_GLOM_ON()) {
1470
printk(KERN_DEBUG "subframe:\n");
1471
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1476
if ((u16)~(sublen ^ check)) {
1477
brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1478
num, sublen, check);
1480
} else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1481
brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1484
} else if ((chan != SDPCM_DATA_CHANNEL) &&
1485
(chan != SDPCM_EVENT_CHANNEL)) {
1486
brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1489
} else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1490
brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1491
num, doff, sublen, SDPCM_HDRLEN);
1497
/* Terminate frame on error, request
1499
if (bus->glomerr++ < 3) {
1500
/* Restore superframe header space */
1501
skb_push(pfirst, sfdoff);
1502
brcmf_sdbrcm_rxfail(bus, true, true);
1505
brcmf_sdbrcm_rxfail(bus, true, false);
1506
brcmu_pkt_buf_free_skb(bus->glom);
1514
/* Basic SD framing looks ok - process each packet (header) */
1515
save_pfirst = pfirst;
1519
for (num = 0; pfirst; rxseq++, pfirst = pnext) {
1520
pnext = pfirst->next;
1521
pfirst->next = NULL;
1523
dptr = (u8 *) (pfirst->data);
1524
sublen = get_unaligned_le16(dptr);
1525
chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1526
seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1527
doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1529
brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1530
num, pfirst, pfirst->data,
1531
pfirst->len, sublen, chan, seq);
1533
/* precondition: chan == SDPCM_DATA_CHANNEL ||
1534
chan == SDPCM_EVENT_CHANNEL */
1537
brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1543
if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1544
printk(KERN_DEBUG "Rx Subframe Data:\n");
1545
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1550
__skb_trim(pfirst, sublen);
1551
skb_pull(pfirst, doff);
1553
if (pfirst->len == 0) {
1554
brcmu_pkt_buf_free_skb(pfirst);
1556
plast->next = pnext;
1558
save_pfirst = pnext;
1561
} else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1563
brcmf_dbg(ERROR, "rx protocol error\n");
1564
bus->drvr->rx_errors++;
1565
brcmu_pkt_buf_free_skb(pfirst);
1567
plast->next = pnext;
1569
save_pfirst = pnext;
1574
/* this packet will go up, link back into
1575
chain and count it */
1576
pfirst->next = pnext;
1581
if (BRCMF_GLOM_ON()) {
1582
brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1583
num, pfirst, pfirst->data,
1584
pfirst->len, pfirst->next,
1586
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1588
min_t(int, pfirst->len, 32));
1594
brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
1598
bus->rxglomframes++;
1599
bus->rxglompkts += num;
1604
static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1607
DECLARE_WAITQUEUE(wait, current);
1608
int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1610
/* Wait until control frame is available */
1611
add_wait_queue(&bus->dcmd_resp_wait, &wait);
1612
set_current_state(TASK_INTERRUPTIBLE);
1614
while (!(*condition) && (!signal_pending(current) && timeout))
1615
timeout = schedule_timeout(timeout);
1617
if (signal_pending(current))
1620
set_current_state(TASK_RUNNING);
1621
remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1626
static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1628
if (waitqueue_active(&bus->dcmd_resp_wait))
1629
wake_up_interruptible(&bus->dcmd_resp_wait);
1634
brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1640
brcmf_dbg(TRACE, "Enter\n");
1642
/* Set rxctl for frame (w/optional alignment) */
1643
bus->rxctl = bus->rxbuf;
1644
bus->rxctl += BRCMF_FIRSTREAD;
1645
pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1647
bus->rxctl += (BRCMF_SDALIGN - pad);
1648
bus->rxctl -= BRCMF_FIRSTREAD;
1650
/* Copy the already-read portion over */
1651
memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1652
if (len <= BRCMF_FIRSTREAD)
1655
/* Raise rdlen to next SDIO block to avoid tail command */
1656
rdlen = len - BRCMF_FIRSTREAD;
1657
if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1658
pad = bus->blocksize - (rdlen % bus->blocksize);
1659
if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1660
((len + pad) < bus->drvr->maxctl))
1662
} else if (rdlen % BRCMF_SDALIGN) {
1663
rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1666
/* Satisfy length-alignment requirements */
1667
if (rdlen & (ALIGNMENT - 1))
1668
rdlen = roundup(rdlen, ALIGNMENT);
1670
/* Drop if the read is too big or it exceeds our maximum */
1671
if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1672
brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1673
rdlen, bus->drvr->maxctl);
1674
bus->drvr->rx_errors++;
1675
brcmf_sdbrcm_rxfail(bus, false, false);
1679
if ((len - doff) > bus->drvr->maxctl) {
1680
brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1681
len, len - doff, bus->drvr->maxctl);
1682
bus->drvr->rx_errors++;
1684
brcmf_sdbrcm_rxfail(bus, false, false);
1688
/* Read remainder of frame body into the rxctl buffer */
1689
sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1690
bus->sdiodev->sbwad,
1692
F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
1696
/* Control frame failures need retransmission */
1698
brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1701
brcmf_sdbrcm_rxfail(bus, true, true);
1708
if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1709
printk(KERN_DEBUG "RxCtrl:\n");
1710
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1714
/* Point to valid data and indicate its length */
1716
bus->rxlen = len - doff;
1719
/* Awake any waiters */
1720
brcmf_sdbrcm_dcmd_resp_wake(bus);
1723
/* Pad read to blocksize for efficiency */
1724
static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1726
if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1727
*pad = bus->blocksize - (*rdlen % bus->blocksize);
1728
if (*pad <= bus->roundup && *pad < bus->blocksize &&
1729
*rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1731
} else if (*rdlen % BRCMF_SDALIGN) {
1732
*rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1737
brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1738
struct sk_buff **pkt, u8 **rxbuf)
1740
int sdret; /* Return code from calls */
1742
*pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1746
pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1747
*rxbuf = (u8 *) ((*pkt)->data);
1748
/* Read the entire frame */
1749
sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1750
SDIO_FUNC_2, F2SYNC,
1751
*rxbuf, rdlen, *pkt);
1755
brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1757
brcmu_pkt_buf_free_skb(*pkt);
1758
bus->drvr->rx_errors++;
1759
/* Force retry w/normal header read.
1760
* Don't attempt NAK for
1763
brcmf_sdbrcm_rxfail(bus, true, true);
1768
/* Checks the header */
1770
brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1771
u8 rxseq, u16 nextlen, u16 *len)
1774
bool len_consistent; /* Result of comparing readahead len and
1777
memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1779
/* Extract hardware header fields */
1780
*len = get_unaligned_le16(bus->rxhdr);
1781
check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1783
/* All zeros means readahead info was bad */
1784
if (!(*len | check)) {
1785
brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1789
/* Validate check bytes */
1790
if ((u16)~(*len ^ check)) {
1791
brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1792
nextlen, *len, check);
1794
brcmf_sdbrcm_rxfail(bus, false, false);
1798
/* Validate frame length */
1799
if (*len < SDPCM_HDRLEN) {
1800
brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1805
/* Check for consistency with readahead info */
1806
len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1807
if (len_consistent) {
1808
/* Mismatch, force retry w/normal
1809
header (may be >4K) */
1810
brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1811
nextlen, *len, roundup(*len, 16),
1813
brcmf_sdbrcm_rxfail(bus, true, true);
1820
brcmf_sdbrcm_pktfree2(bus, pkt);
1824
/* Return true if there may be more frames to read */
1826
brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1828
u16 len, check; /* Extracted hardware header fields */
1829
u8 chan, seq, doff; /* Extracted software header fields */
1830
u8 fcbits; /* Extracted fcbits from software header */
1832
struct sk_buff *pkt; /* Packet for event or data frames */
1833
u16 pad; /* Number of pad bytes to read */
1834
u16 rdlen; /* Total number of bytes to read */
1835
u8 rxseq; /* Next sequence number to expect */
1836
uint rxleft = 0; /* Remaining number of frames allowed */
1837
int sdret; /* Return code from calls */
1838
u8 txmax; /* Maximum tx sequence offered */
1841
uint rxcount = 0; /* Total frames read */
1843
brcmf_dbg(TRACE, "Enter\n");
1845
/* Not finished unless we encounter no more frames indication */
1848
for (rxseq = bus->rx_seq, rxleft = maxframes;
1849
!bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1850
rxseq++, rxleft--) {
1852
/* Handle glomming separately */
1853
if (bus->glom || bus->glomd) {
1855
brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1856
bus->glomd, bus->glom);
1857
cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1858
brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1860
rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1864
/* Try doing single read if we can */
1866
u16 nextlen = bus->nextlen;
1869
rdlen = len = nextlen << 4;
1870
brcmf_pad(bus, &pad, &rdlen);
1873
* After the frame is received we have to
1874
* distinguish whether it is data
1875
* or non-data frame.
1877
brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1879
/* Give up on data, request rtx of events */
1880
brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1885
if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1889
/* Extract software header fields */
1890
chan = SDPCM_PACKET_CHANNEL(
1891
&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1892
seq = SDPCM_PACKET_SEQUENCE(
1893
&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1894
doff = SDPCM_DOFFSET_VALUE(
1895
&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1896
txmax = SDPCM_WINDOW_VALUE(
1897
&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1900
bus->rxhdr[SDPCM_FRAMETAG_LEN +
1901
SDPCM_NEXTLEN_OFFSET];
1902
if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1903
brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1908
bus->drvr->rx_readahead_cnt++;
1910
/* Handle Flow Control */
1911
fcbits = SDPCM_FCMASK_VALUE(
1912
&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1914
if (bus->flowcontrol != fcbits) {
1915
if (~bus->flowcontrol & fcbits)
1918
if (bus->flowcontrol & ~fcbits)
1922
bus->flowcontrol = fcbits;
1925
/* Check and update sequence number */
1927
brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1933
/* Check window for sanity */
1934
if ((u8) (txmax - bus->tx_seq) > 0x40) {
1935
brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1936
txmax, bus->tx_seq);
1937
txmax = bus->tx_seq + 2;
1939
bus->tx_max = txmax;
1942
if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1943
printk(KERN_DEBUG "Rx Data:\n");
1944
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1946
} else if (BRCMF_HDRS_ON()) {
1947
printk(KERN_DEBUG "RxHdr:\n");
1948
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1949
bus->rxhdr, SDPCM_HDRLEN);
1953
if (chan == SDPCM_CONTROL_CHANNEL) {
1954
brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1956
/* Force retry w/normal header read */
1958
brcmf_sdbrcm_rxfail(bus, false, true);
1959
brcmf_sdbrcm_pktfree2(bus, pkt);
1963
/* Validate data offset */
1964
if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1965
brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1966
doff, len, SDPCM_HDRLEN);
1967
brcmf_sdbrcm_rxfail(bus, false, false);
1968
brcmf_sdbrcm_pktfree2(bus, pkt);
1972
/* All done with this one -- now deliver the packet */
1976
/* Read frame header (hardware and software) */
1977
sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1978
SDIO_FUNC_2, F2SYNC, bus->rxhdr,
1979
BRCMF_FIRSTREAD, NULL);
1983
brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
1985
brcmf_sdbrcm_rxfail(bus, true, true);
1989
if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1990
printk(KERN_DEBUG "RxHdr:\n");
1991
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1992
bus->rxhdr, SDPCM_HDRLEN);
1996
/* Extract hardware header fields */
1997
len = get_unaligned_le16(bus->rxhdr);
1998
check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
2000
/* All zeros means no more frames */
2001
if (!(len | check)) {
2006
/* Validate check bytes */
2007
if ((u16) ~(len ^ check)) {
2008
brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
2011
brcmf_sdbrcm_rxfail(bus, false, false);
2015
/* Validate frame length */
2016
if (len < SDPCM_HDRLEN) {
2017
brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
2021
/* Extract software header fields */
2022
chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2023
seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2024
doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2025
txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2027
/* Validate data offset */
2028
if ((doff < SDPCM_HDRLEN) || (doff > len)) {
2029
brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
2030
doff, len, SDPCM_HDRLEN, seq);
2032
brcmf_sdbrcm_rxfail(bus, false, false);
2036
/* Save the readahead length if there is one */
2038
bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2039
if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2040
brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
2045
/* Handle Flow Control */
2046
fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2048
if (bus->flowcontrol != fcbits) {
2049
if (~bus->flowcontrol & fcbits)
2052
if (bus->flowcontrol & ~fcbits)
2056
bus->flowcontrol = fcbits;
2059
/* Check and update sequence number */
2061
brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
2066
/* Check window for sanity */
2067
if ((u8) (txmax - bus->tx_seq) > 0x40) {
2068
brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2069
txmax, bus->tx_seq);
2070
txmax = bus->tx_seq + 2;
2072
bus->tx_max = txmax;
2074
/* Call a separate function for control frames */
2075
if (chan == SDPCM_CONTROL_CHANNEL) {
2076
brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
2080
/* precondition: chan is either SDPCM_DATA_CHANNEL,
2081
SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
2082
SDPCM_GLOM_CHANNEL */
2084
/* Length to read */
2085
rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
2087
/* May pad read to blocksize for efficiency */
2088
if (bus->roundup && bus->blocksize &&
2089
(rdlen > bus->blocksize)) {
2090
pad = bus->blocksize - (rdlen % bus->blocksize);
2091
if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2092
((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
2094
} else if (rdlen % BRCMF_SDALIGN) {
2095
rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2098
/* Satisfy length-alignment requirements */
2099
if (rdlen & (ALIGNMENT - 1))
2100
rdlen = roundup(rdlen, ALIGNMENT);
2102
if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
2103
/* Too long -- skip this frame */
2104
brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
2106
bus->drvr->rx_errors++;
2108
brcmf_sdbrcm_rxfail(bus, false, false);
2112
pkt = brcmu_pkt_buf_get_skb(rdlen +
2113
BRCMF_FIRSTREAD + BRCMF_SDALIGN);
2115
/* Give up on data, request rtx of events */
2116
brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
2118
bus->drvr->rx_dropped++;
2119
brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
2123
/* Leave room for what we already read, and align remainder */
2124
skb_pull(pkt, BRCMF_FIRSTREAD);
2125
pkt_align(pkt, rdlen, BRCMF_SDALIGN);
2127
/* Read the remaining frame data */
2128
sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2129
SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
2134
brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2135
((chan == SDPCM_EVENT_CHANNEL) ? "event"
2136
: ((chan == SDPCM_DATA_CHANNEL) ? "data"
2138
brcmu_pkt_buf_free_skb(pkt);
2139
bus->drvr->rx_errors++;
2140
brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2144
/* Copy the already-read portion */
2145
skb_push(pkt, BRCMF_FIRSTREAD);
2146
memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2149
if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2150
printk(KERN_DEBUG "Rx Data:\n");
2151
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2157
/* Save superframe descriptor and allocate packet frame */
2158
if (chan == SDPCM_GLOM_CHANNEL) {
2159
if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2160
brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2163
if (BRCMF_GLOM_ON()) {
2164
printk(KERN_DEBUG "Glom Data:\n");
2165
print_hex_dump_bytes("",
2170
__skb_trim(pkt, len);
2171
skb_pull(pkt, SDPCM_HDRLEN);
2174
brcmf_dbg(ERROR, "%s: glom superframe w/o "
2175
"descriptor!\n", __func__);
2176
brcmf_sdbrcm_rxfail(bus, false, false);
2181
/* Fill in packet len and prio, deliver upward */
2182
__skb_trim(pkt, len);
2183
skb_pull(pkt, doff);
2185
if (pkt->len == 0) {
2186
brcmu_pkt_buf_free_skb(pkt);
2188
} else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2189
brcmf_dbg(ERROR, "rx protocol error\n");
2190
brcmu_pkt_buf_free_skb(pkt);
2191
bus->drvr->rx_errors++;
2195
/* Unlock during rx call */
2197
brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
2200
rxcount = maxframes - rxleft;
2202
/* Message if we hit the limit */
2204
brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2208
brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2209
/* Back off rxseq if awaiting rtx, update rx_seq */
2212
bus->rx_seq = rxseq;
2218
brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
2219
u8 *buf, uint nbytes, struct sk_buff *pkt)
2221
return brcmf_sdcard_send_buf
2222
(bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
2226
brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2229
wait_event_interruptible_timeout(bus->ctrl_wait,
2230
(*lockvar == false), HZ * 2);
2236
brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2238
if (waitqueue_active(&bus->ctrl_wait))
2239
wake_up_interruptible(&bus->ctrl_wait);
2243
/* Writes a HW/SW header into the packet and sends it. */
2244
/* Assumes: (a) header space already there, (b) caller holds lock */
2245
static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2246
uint chan, bool free_pkt)
2252
struct sk_buff *new;
2255
brcmf_dbg(TRACE, "Enter\n");
2257
frame = (u8 *) (pkt->data);
2259
/* Add alignment padding, allocate new packet if needed */
2260
pad = ((unsigned long)frame % BRCMF_SDALIGN);
2262
if (skb_headroom(pkt) < pad) {
2263
brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2264
skb_headroom(pkt), pad);
2265
bus->drvr->tx_realloc++;
2266
new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2268
brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2269
pkt->len + BRCMF_SDALIGN);
2274
pkt_align(new, pkt->len, BRCMF_SDALIGN);
2275
memcpy(new->data, pkt->data, pkt->len);
2277
brcmu_pkt_buf_free_skb(pkt);
2278
/* free the pkt if canned one is not used */
2281
frame = (u8 *) (pkt->data);
2282
/* precondition: (frame % BRCMF_SDALIGN) == 0) */
2286
frame = (u8 *) (pkt->data);
2287
/* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2288
memset(frame, 0, pad + SDPCM_HDRLEN);
2291
/* precondition: pad < BRCMF_SDALIGN */
2293
/* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2294
len = (u16) (pkt->len);
2295
*(__le16 *) frame = cpu_to_le16(len);
2296
*(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2298
/* Software tag: channel, sequence number, data offset */
2300
((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2302
SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2304
put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2305
put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2308
tx_packets[pkt->priority]++;
2309
if (BRCMF_BYTES_ON() &&
2310
(((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2311
(BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2312
printk(KERN_DEBUG "Tx Frame:\n");
2313
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2314
} else if (BRCMF_HDRS_ON()) {
2315
printk(KERN_DEBUG "TxHdr:\n");
2316
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2317
frame, min_t(u16, len, 16));
2321
/* Raise len to next SDIO block to eliminate tail command */
2322
if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2323
u16 pad = bus->blocksize - (len % bus->blocksize);
2324
if ((pad <= bus->roundup) && (pad < bus->blocksize))
2326
} else if (len % BRCMF_SDALIGN) {
2327
len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2330
/* Some controllers have trouble with odd bytes -- round to even */
2331
if (len & (ALIGNMENT - 1))
2332
len = roundup(len, ALIGNMENT);
2334
ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2335
SDIO_FUNC_2, F2SYNC, frame,
2340
/* On failure, abort the command and terminate the frame */
2341
brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2345
brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2346
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2347
SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2351
for (i = 0; i < 3; i++) {
2353
hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2355
SBSDIO_FUNC1_WFRAMEBCHI,
2357
lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2359
SBSDIO_FUNC1_WFRAMEBCLO,
2361
bus->f1regdata += 2;
2362
if ((hi == 0) && (lo == 0))
2368
bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2371
/* restore pkt buffer pointer before calling tx complete routine */
2372
skb_pull(pkt, SDPCM_HDRLEN + pad);
2374
brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2378
brcmu_pkt_buf_free_skb(pkt);
2383
static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2385
struct sk_buff *pkt;
2388
int ret = 0, prec_out;
2393
struct brcmf_pub *drvr = bus->drvr;
2395
brcmf_dbg(TRACE, "Enter\n");
2397
tx_prec_map = ~bus->flowcontrol;
2399
/* Send frames until the limit or some other event */
2400
for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2401
spin_lock_bh(&bus->txqlock);
2402
pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2404
spin_unlock_bh(&bus->txqlock);
2407
spin_unlock_bh(&bus->txqlock);
2408
datalen = pkt->len - SDPCM_HDRLEN;
2410
ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2412
bus->drvr->tx_errors++;
2414
bus->drvr->dstats.tx_bytes += datalen;
2416
/* In poll mode, need to check for other events */
2417
if (!bus->intr && cnt) {
2418
/* Check device status, signal pending interrupt */
2419
r_sdreg32(bus, &intstatus,
2420
offsetof(struct sdpcmd_regs, intstatus),
2423
if (brcmf_sdcard_regfail(bus->sdiodev))
2425
if (intstatus & bus->hostintmask)
2430
/* Deflow-control stack if needed */
2431
if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2432
drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2433
brcmf_txflowcontrol(drvr, 0, OFF);
2438
static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2440
u32 intstatus, newstatus = 0;
2442
uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2443
uint txlimit = bus->txbound; /* Tx frames to send before resched */
2444
uint framecnt = 0; /* Temporary counter of tx/rx frames */
2445
bool rxdone = true; /* Flag for no more read data */
2446
bool resched = false; /* Flag indicating resched wanted */
2448
brcmf_dbg(TRACE, "Enter\n");
2450
/* Start with leftover status bits */
2451
intstatus = bus->intstatus;
2455
/* If waiting for HTAVAIL, check status */
2456
if (bus->clkstate == CLK_PENDING) {
2458
u8 clkctl, devctl = 0;
2461
/* Check for inconsistent device control */
2462
devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2463
SBSDIO_DEVICE_CTL, &err);
2465
brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2466
bus->drvr->busstate = BRCMF_BUS_DOWN;
2470
/* Read CSR, if clock on switch to AVAIL, else ignore */
2471
clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2472
SBSDIO_FUNC1_CHIPCLKCSR, &err);
2474
brcmf_dbg(ERROR, "error reading CSR: %d\n",
2476
bus->drvr->busstate = BRCMF_BUS_DOWN;
2479
brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2482
if (SBSDIO_HTAV(clkctl)) {
2483
devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2485
SBSDIO_DEVICE_CTL, &err);
2487
brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2489
bus->drvr->busstate = BRCMF_BUS_DOWN;
2491
devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2492
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2493
SBSDIO_DEVICE_CTL, devctl, &err);
2495
brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2497
bus->drvr->busstate = BRCMF_BUS_DOWN;
2499
bus->clkstate = CLK_AVAIL;
2507
/* Make sure backplane clock is on */
2508
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2509
if (bus->clkstate == CLK_PENDING)
2512
/* Pending interrupt indicates new device status */
2515
r_sdreg32(bus, &newstatus,
2516
offsetof(struct sdpcmd_regs, intstatus), &retries);
2518
if (brcmf_sdcard_regfail(bus->sdiodev))
2520
newstatus &= bus->hostintmask;
2521
bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2523
w_sdreg32(bus, newstatus,
2524
offsetof(struct sdpcmd_regs, intstatus),
2530
/* Merge new bits with previous */
2531
intstatus |= newstatus;
2534
/* Handle flow-control change: read new state in case our ack
2535
* crossed another change interrupt. If change still set, assume
2536
* FC ON for safety, let next loop through do the debounce.
2538
if (intstatus & I_HMB_FC_CHANGE) {
2539
intstatus &= ~I_HMB_FC_CHANGE;
2540
w_sdreg32(bus, I_HMB_FC_CHANGE,
2541
offsetof(struct sdpcmd_regs, intstatus), &retries);
2543
r_sdreg32(bus, &newstatus,
2544
offsetof(struct sdpcmd_regs, intstatus), &retries);
2545
bus->f1regdata += 2;
2547
!!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2548
intstatus |= (newstatus & bus->hostintmask);
2551
/* Handle host mailbox indication */
2552
if (intstatus & I_HMB_HOST_INT) {
2553
intstatus &= ~I_HMB_HOST_INT;
2554
intstatus |= brcmf_sdbrcm_hostmail(bus);
2557
/* Generally don't ask for these, can get CRC errors... */
2558
if (intstatus & I_WR_OOSYNC) {
2559
brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2560
intstatus &= ~I_WR_OOSYNC;
2563
if (intstatus & I_RD_OOSYNC) {
2564
brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2565
intstatus &= ~I_RD_OOSYNC;
2568
if (intstatus & I_SBINT) {
2569
brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2570
intstatus &= ~I_SBINT;
2573
/* Would be active due to wake-wlan in gSPI */
2574
if (intstatus & I_CHIPACTIVE) {
2575
brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2576
intstatus &= ~I_CHIPACTIVE;
2579
/* Ignore frame indications if rxskip is set */
2581
intstatus &= ~I_HMB_FRAME_IND;
2583
/* On frame indication, read available frames */
2584
if (PKT_AVAILABLE()) {
2585
framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2586
if (rxdone || bus->rxskip)
2587
intstatus &= ~I_HMB_FRAME_IND;
2588
rxlimit -= min(framecnt, rxlimit);
2591
/* Keep still-pending events for next scheduling */
2592
bus->intstatus = intstatus;
2595
if (data_ok(bus) && bus->ctrl_frame_stat &&
2596
(bus->clkstate == CLK_AVAIL)) {
2599
ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2600
SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2601
(u32) bus->ctrl_frame_len, NULL);
2604
/* On failure, abort the command and
2605
terminate the frame */
2606
brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2610
brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2612
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2613
SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2617
for (i = 0; i < 3; i++) {
2619
hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2621
SBSDIO_FUNC1_WFRAMEBCHI,
2623
lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2625
SBSDIO_FUNC1_WFRAMEBCLO,
2627
bus->f1regdata += 2;
2628
if ((hi == 0) && (lo == 0))
2634
bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2636
brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2637
bus->ctrl_frame_stat = false;
2638
brcmf_sdbrcm_wait_event_wakeup(bus);
2640
/* Send queued frames (limit 1 if rx may still be pending) */
2641
else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2642
brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2644
framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2645
framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2646
txlimit -= framecnt;
2649
/* Resched if events or tx frames are pending,
2650
else await next interrupt */
2651
/* On failed register access, all bets are off:
2652
no resched or interrupts */
2653
if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2654
brcmf_sdcard_regfail(bus->sdiodev)) {
2655
brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2656
brcmf_sdcard_regfail(bus->sdiodev));
2657
bus->drvr->busstate = BRCMF_BUS_DOWN;
2659
} else if (bus->clkstate == CLK_PENDING) {
2660
brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2662
} else if (bus->intstatus || bus->ipend ||
2663
(!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2664
&& data_ok(bus)) || PKT_AVAILABLE()) {
2668
bus->dpc_sched = resched;
2670
/* If we're done for now, turn off clock request. */
2671
if ((bus->clkstate != CLK_PENDING)
2672
&& bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2673
bus->activity = false;
2674
brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2682
static int brcmf_sdbrcm_dpc_thread(void *data)
2684
struct brcmf_bus *bus = (struct brcmf_bus *) data;
2686
allow_signal(SIGTERM);
2687
/* Run until signal received */
2689
if (kthread_should_stop())
2691
if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2692
/* Call bus dpc unless it indicated down
2693
(then clean stop) */
2694
if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2695
if (brcmf_sdbrcm_dpc(bus))
2696
complete(&bus->dpc_wait);
2698
/* after stopping the bus, exit thread */
2699
brcmf_sdbrcm_bus_stop(bus);
2700
bus->dpc_tsk = NULL;
2709
int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2714
brcmf_dbg(TRACE, "Enter\n");
2718
/* Add space for the header */
2719
skb_push(pkt, SDPCM_HDRLEN);
2720
/* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2722
prec = prio2prec((pkt->priority & PRIOMASK));
2724
/* Check for existing queue, current flow-control,
2725
pending event, or pending clock */
2726
brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2729
/* Priority based enq */
2730
spin_lock_bh(&bus->txqlock);
2731
if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2732
skb_pull(pkt, SDPCM_HDRLEN);
2733
brcmf_txcomplete(bus->drvr, pkt, false);
2734
brcmu_pkt_buf_free_skb(pkt);
2735
brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2740
spin_unlock_bh(&bus->txqlock);
2742
if (pktq_len(&bus->txq) >= TXHI)
2743
brcmf_txflowcontrol(bus->drvr, 0, ON);
2746
if (pktq_plen(&bus->txq, prec) > qcount[prec])
2747
qcount[prec] = pktq_plen(&bus->txq, prec);
2749
/* Schedule DPC if needed to send queued packet(s) */
2750
if (!bus->dpc_sched) {
2751
bus->dpc_sched = true;
2753
complete(&bus->dpc_wait);
2760
brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2767
/* Determine initial transfer parameters */
2768
sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2769
if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2770
dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2774
/* Set the backplane window to include the start address */
2775
bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2777
brcmf_dbg(ERROR, "window change failed\n");
2781
/* Do the transfer(s) */
2783
brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2784
write ? "write" : "read", dsize,
2785
sdaddr, address & SBSDIO_SBWINDOW_MASK);
2786
bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2787
sdaddr, data, dsize);
2789
brcmf_dbg(ERROR, "membytes transfer failed\n");
2793
/* Adjust for next transfer (if any) */
2798
bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2801
brcmf_dbg(ERROR, "window change failed\n");
2805
dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2810
/* Return the window to backplane enumeration space for core access */
2811
if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2812
brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2813
bus->sdiodev->sbwad);
2819
#define CONSOLE_LINE_MAX 192
2821
static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2823
struct brcmf_console *c = &bus->console;
2824
u8 line[CONSOLE_LINE_MAX], ch;
2828
/* Don't do anything until FWREADY updates console address */
2829
if (bus->console_addr == 0)
2832
/* Read console log struct */
2833
addr = bus->console_addr + offsetof(struct rte_console, log_le);
2834
rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2839
/* Allocate console buffer (one time only) */
2840
if (c->buf == NULL) {
2841
c->bufsize = le32_to_cpu(c->log_le.buf_size);
2842
c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2847
idx = le32_to_cpu(c->log_le.idx);
2849
/* Protect against corrupt value */
2850
if (idx > c->bufsize)
2853
/* Skip reading the console buffer if the index pointer
2858
/* Read the console buffer */
2859
addr = le32_to_cpu(c->log_le.buf);
2860
rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2864
while (c->last != idx) {
2865
for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2866
if (c->last == idx) {
2867
/* This would output a partial line.
2869
* the buffer pointer and output this
2870
* line next time around.
2875
c->last = c->bufsize - n;
2878
ch = c->buf[c->last];
2879
c->last = (c->last + 1) % c->bufsize;
2886
if (line[n - 1] == '\r')
2889
printk(KERN_DEBUG "CONSOLE: %s\n", line);
2898
static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2903
bus->ctrl_frame_stat = false;
2904
ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2905
SDIO_FUNC_2, F2SYNC, frame, len, NULL);
2908
/* On failure, abort the command and terminate the frame */
2909
brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2913
brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2915
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2916
SBSDIO_FUNC1_FRAMECTRL,
2920
for (i = 0; i < 3; i++) {
2922
hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2923
SBSDIO_FUNC1_WFRAMEBCHI,
2925
lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2926
SBSDIO_FUNC1_WFRAMEBCLO,
2928
bus->f1regdata += 2;
2929
if (hi == 0 && lo == 0)
2935
bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2941
brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2950
brcmf_dbg(TRACE, "Enter\n");
2952
/* Back the pointer to make a room for bus header */
2953
frame = msg - SDPCM_HDRLEN;
2954
len = (msglen += SDPCM_HDRLEN);
2956
/* Add alignment padding (optional for ctl frames) */
2957
doff = ((unsigned long)frame % BRCMF_SDALIGN);
2962
memset(frame, 0, doff + SDPCM_HDRLEN);
2964
/* precondition: doff < BRCMF_SDALIGN */
2965
doff += SDPCM_HDRLEN;
2967
/* Round send length to next SDIO block */
2968
if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2969
u16 pad = bus->blocksize - (len % bus->blocksize);
2970
if ((pad <= bus->roundup) && (pad < bus->blocksize))
2972
} else if (len % BRCMF_SDALIGN) {
2973
len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2976
/* Satisfy length-alignment requirements */
2977
if (len & (ALIGNMENT - 1))
2978
len = roundup(len, ALIGNMENT);
2980
/* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2982
/* Need to lock here to protect txseq and SDIO tx calls */
2987
/* Make sure backplane clock is on */
2988
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2990
/* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2991
*(__le16 *) frame = cpu_to_le16((u16) msglen);
2992
*(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2994
/* Software tag: channel, sequence number, data offset */
2996
((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2998
| bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2999
SDPCM_DOFFSET_MASK);
3000
put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
3001
put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
3003
if (!data_ok(bus)) {
3004
brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
3005
bus->tx_max, bus->tx_seq);
3006
bus->ctrl_frame_stat = true;
3008
bus->ctrl_frame_buf = frame;
3009
bus->ctrl_frame_len = len;
3011
brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
3013
if (bus->ctrl_frame_stat == false) {
3014
brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
3017
brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
3024
if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3025
printk(KERN_DEBUG "Tx Frame:\n");
3026
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3028
} else if (BRCMF_HDRS_ON()) {
3029
printk(KERN_DEBUG "TxHdr:\n");
3030
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3031
frame, min_t(u16, len, 16));
3036
ret = brcmf_tx_frame(bus, frame, len);
3037
} while (ret < 0 && retries++ < TXRETRIES);
3040
if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
3041
bus->activity = false;
3042
brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3048
bus->drvr->tx_ctlerrs++;
3050
bus->drvr->tx_ctlpkts++;
3052
return ret ? -EIO : 0;
3056
brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
3062
brcmf_dbg(TRACE, "Enter\n");
3064
/* Wait until control frame is available */
3065
timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3069
memcpy(msg, bus->rxctl, min(msglen, rxlen));
3074
brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3076
} else if (timeleft == 0) {
3077
brcmf_dbg(ERROR, "resumed on timeout\n");
3078
} else if (pending == true) {
3079
brcmf_dbg(CTL, "cancelled\n");
3080
return -ERESTARTSYS;
3082
brcmf_dbg(CTL, "resumed for unknown reason?\n");
3086
bus->drvr->rx_ctlpkts++;
3088
bus->drvr->rx_ctlerrs++;
3090
return rxlen ? (int)rxlen : -ETIMEDOUT;
3093
static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
3097
brcmf_dbg(TRACE, "Enter\n");
3099
/* Basic sanity checks */
3100
if (bus->drvr->up) {
3101
bcmerror = -EISCONN;
3105
bcmerror = -EOVERFLOW;
3109
/* Free the old ones and replace with passed variables */
3112
bus->vars = kmalloc(len, GFP_ATOMIC);
3113
bus->varsz = bus->vars ? len : 0;
3114
if (bus->vars == NULL) {
3119
/* Copy the passed variables, which should include the
3120
terminating double-null */
3121
memcpy(bus->vars, arg, bus->varsz);
3126
static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3135
char *nvram_ularray;
3138
/* Even if there are no vars are to be written, we still
3139
need to set the ramsize. */
3140
varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3141
varaddr = (bus->ramsize - 4) - varsize;
3144
vbuffer = kzalloc(varsize, GFP_ATOMIC);
3148
memcpy(vbuffer, bus->vars, bus->varsz);
3150
/* Write the vars list */
3152
brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3154
/* Verify NVRAM bytes */
3155
brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3156
nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3160
/* Upload image to verify downloaded contents. */
3161
memset(nvram_ularray, 0xaa, varsize);
3163
/* Read the vars list to temp buffer for comparison */
3165
brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3168
brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3169
bcmerror, varsize, varaddr);
3171
/* Compare the org NVRAM with the one read from RAM */
3172
if (memcmp(vbuffer, nvram_ularray, varsize))
3173
brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3175
brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3177
kfree(nvram_ularray);
3183
/* adjust to the user specified RAM */
3184
brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3185
brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3187
varsize = ((bus->ramsize - 4) - varaddr);
3190
* Determine the length token:
3191
* Varsize, converted to words, in lower 16-bits, checksum
3196
varsizew_le = cpu_to_le32(0);
3198
varsizew = varsize / 4;
3199
varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3200
varsizew_le = cpu_to_le32(varsizew);
3203
brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3206
/* Write the length token to the last word */
3207
bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3208
(u8 *)&varsizew_le, 4);
3214
brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3218
regdata = brcmf_sdcard_reg_read(sdiodev,
3219
CORE_SB(corebase, sbtmstatelow), 4);
3220
if (regdata & SBTML_RESET)
3223
regdata = brcmf_sdcard_reg_read(sdiodev,
3224
CORE_SB(corebase, sbtmstatelow), 4);
3225
if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3227
* set target reject and spin until busy is clear
3228
* (preserve core-specific bits)
3230
regdata = brcmf_sdcard_reg_read(sdiodev,
3231
CORE_SB(corebase, sbtmstatelow), 4);
3232
brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3233
4, regdata | SBTML_REJ);
3235
regdata = brcmf_sdcard_reg_read(sdiodev,
3236
CORE_SB(corebase, sbtmstatelow), 4);
3238
SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3239
CORE_SB(corebase, sbtmstatehigh), 4) &
3240
SBTMH_BUSY), 100000);
3242
regdata = brcmf_sdcard_reg_read(sdiodev,
3243
CORE_SB(corebase, sbtmstatehigh), 4);
3244
if (regdata & SBTMH_BUSY)
3245
brcmf_dbg(ERROR, "ARM core still busy\n");
3247
regdata = brcmf_sdcard_reg_read(sdiodev,
3248
CORE_SB(corebase, sbidlow), 4);
3249
if (regdata & SBIDL_INIT) {
3250
regdata = brcmf_sdcard_reg_read(sdiodev,
3251
CORE_SB(corebase, sbimstate), 4) |
3253
brcmf_sdcard_reg_write(sdiodev,
3254
CORE_SB(corebase, sbimstate), 4,
3256
regdata = brcmf_sdcard_reg_read(sdiodev,
3257
CORE_SB(corebase, sbimstate), 4);
3259
SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3260
CORE_SB(corebase, sbimstate), 4) &
3264
/* set reset and reject while enabling the clocks */
3265
brcmf_sdcard_reg_write(sdiodev,
3266
CORE_SB(corebase, sbtmstatelow), 4,
3267
(((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3268
SBTML_REJ | SBTML_RESET));
3269
regdata = brcmf_sdcard_reg_read(sdiodev,
3270
CORE_SB(corebase, sbtmstatelow), 4);
3273
/* clear the initiator reject bit */
3274
regdata = brcmf_sdcard_reg_read(sdiodev,
3275
CORE_SB(corebase, sbidlow), 4);
3276
if (regdata & SBIDL_INIT) {
3277
regdata = brcmf_sdcard_reg_read(sdiodev,
3278
CORE_SB(corebase, sbimstate), 4) &
3280
brcmf_sdcard_reg_write(sdiodev,
3281
CORE_SB(corebase, sbimstate), 4,
3286
/* leave reset and reject asserted */
3287
brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3288
(SBTML_REJ | SBTML_RESET));
3293
brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3298
* Must do the disable sequence first to work for
3299
* arbitrary current core state.
3301
brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3304
* Now do the initialization sequence.
3305
* set reset while enabling the clock and
3306
* forcing them on throughout the core
3308
brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3309
((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3313
regdata = brcmf_sdcard_reg_read(sdiodev,
3314
CORE_SB(corebase, sbtmstatehigh), 4);
3315
if (regdata & SBTMH_SERR)
3316
brcmf_sdcard_reg_write(sdiodev,
3317
CORE_SB(corebase, sbtmstatehigh), 4, 0);
3319
regdata = brcmf_sdcard_reg_read(sdiodev,
3320
CORE_SB(corebase, sbimstate), 4);
3321
if (regdata & (SBIM_IBE | SBIM_TO))
3322
brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3323
regdata & ~(SBIM_IBE | SBIM_TO));
3325
/* clear reset and allow it to propagate throughout the core */
3326
brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3327
(SICF_FGC << SBTML_SICF_SHIFT) |
3328
(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3331
/* leave clock enabled */
3332
brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3333
(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3337
static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3343
/* To enter download state, disable ARM and reset SOCRAM.
3344
* To exit download state, simply reset ARM (default is RAM boot).
3347
bus->alp_only = true;
3349
brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
3350
bus->ci->armcorebase);
3352
brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
3354
/* Clear the top bit of memory */
3357
brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3361
regdata = brcmf_sdcard_reg_read(bus->sdiodev,
3362
CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3363
regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3364
(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3365
if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3366
brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3371
bcmerror = brcmf_sdbrcm_write_vars(bus);
3373
brcmf_dbg(ERROR, "no vars written to RAM\n");
3377
w_sdreg32(bus, 0xFFFFFFFF,
3378
offsetof(struct sdpcmd_regs, intstatus), &retries);
3380
brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
3382
/* Allow HT Clock now that the ARM is running. */
3383
bus->alp_only = false;
3385
bus->drvr->busstate = BRCMF_BUS_LOAD;
3391
static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3393
if (bus->firmware->size < bus->fw_ptr + len)
3394
len = bus->firmware->size - bus->fw_ptr;
3396
memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3401
MODULE_FIRMWARE(BCM4329_FW_NAME);
3402
MODULE_FIRMWARE(BCM4329_NV_NAME);
3404
static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3408
u8 *memblock = NULL, *memptr;
3411
brcmf_dbg(INFO, "Enter\n");
3413
bus->fw_name = BCM4329_FW_NAME;
3414
ret = request_firmware(&bus->firmware, bus->fw_name,
3415
&bus->sdiodev->func[2]->dev);
3417
brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3422
memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3423
if (memblock == NULL) {
3427
if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3428
memptr += (BRCMF_SDALIGN -
3429
((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3431
/* Download image */
3433
brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3434
ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3436
brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3437
ret, MEMBLOCK, offset);
3447
release_firmware(bus->firmware);
3454
* ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3455
* and ending in a NUL.
3456
* Removes carriage returns, empty lines, comment lines, and converts
3458
* Shortens buffer as needed and pads with NULs. End of buffer is marked
3462
static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3471
findNewline = false;
3474
for (n = 0; n < len; n++) {
3477
if (varbuf[n] == '\r')
3479
if (findNewline && varbuf[n] != '\n')
3481
findNewline = false;
3482
if (varbuf[n] == '#') {
3486
if (varbuf[n] == '\n') {
3496
buf_len = dp - varbuf;
3498
while (dp < varbuf + n)
3504
static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3507
char *memblock = NULL;
3511
bus->nv_name = BCM4329_NV_NAME;
3512
ret = request_firmware(&bus->firmware, bus->nv_name,
3513
&bus->sdiodev->func[2]->dev);
3515
brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3520
memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3521
if (memblock == NULL) {
3526
len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3528
if (len > 0 && len < MEMBLOCK) {
3529
bufp = (char *)memblock;
3531
len = brcmf_process_nvram_vars(bufp, len);
3535
ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3537
brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3539
brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3546
release_firmware(bus->firmware);
3552
static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3556
/* Keep arm in reset */
3557
if (brcmf_sdbrcm_download_state(bus, true)) {
3558
brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3562
/* External image takes precedence if specified */
3563
if (brcmf_sdbrcm_download_code_file(bus)) {
3564
brcmf_dbg(ERROR, "dongle image file download failed\n");
3568
/* External nvram takes precedence if specified */
3569
if (brcmf_sdbrcm_download_nvram(bus))
3570
brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3572
/* Take arm out of reset */
3573
if (brcmf_sdbrcm_download_state(bus, false)) {
3574
brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3585
brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3589
/* Download the firmware */
3590
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3592
ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3594
brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3599
void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3601
u32 local_hostintmask;
3606
brcmf_dbg(TRACE, "Enter\n");
3608
if (bus->watchdog_tsk) {
3609
send_sig(SIGTERM, bus->watchdog_tsk, 1);
3610
kthread_stop(bus->watchdog_tsk);
3611
bus->watchdog_tsk = NULL;
3614
if (bus->dpc_tsk && bus->dpc_tsk != current) {
3615
send_sig(SIGTERM, bus->dpc_tsk, 1);
3616
kthread_stop(bus->dpc_tsk);
3617
bus->dpc_tsk = NULL;
3624
/* Enable clock for device interrupts */
3625
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3627
/* Disable and clear interrupts at the chip level also */
3628
w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3629
local_hostintmask = bus->hostintmask;
3630
bus->hostintmask = 0;
3632
/* Change our idea of bus state */
3633
bus->drvr->busstate = BRCMF_BUS_DOWN;
3635
/* Force clocks on backplane to be sure F2 interrupt propagates */
3636
saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3637
SBSDIO_FUNC1_CHIPCLKCSR, &err);
3639
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3640
SBSDIO_FUNC1_CHIPCLKCSR,
3641
(saveclk | SBSDIO_FORCE_HT), &err);
3644
brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3646
/* Turn off the bus (F2), free any pending packets */
3647
brcmf_dbg(INTR, "disable SDIO interrupts\n");
3648
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3649
SDIO_FUNC_ENABLE_1, NULL);
3651
/* Clear any pending interrupts now that F2 is disabled */
3652
w_sdreg32(bus, local_hostintmask,
3653
offsetof(struct sdpcmd_regs, intstatus), &retries);
3655
/* Turn off the backplane clock (only) */
3656
brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3658
/* Clear the data packet queues */
3659
brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3661
/* Clear any held glomming stuff */
3663
brcmu_pkt_buf_free_skb(bus->glomd);
3666
brcmu_pkt_buf_free_skb(bus->glom);
3668
bus->glom = bus->glomd = NULL;
3670
/* Clear rx control and wake any waiters */
3672
brcmf_sdbrcm_dcmd_resp_wake(bus);
3674
/* Reset some F2 state stuff */
3675
bus->rxskip = false;
3676
bus->tx_seq = bus->rx_seq = 0;
3681
int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3683
struct brcmf_bus *bus = drvr->bus;
3684
unsigned long timeout;
3690
brcmf_dbg(TRACE, "Enter\n");
3692
/* try to download image and nvram to the dongle */
3693
if (drvr->busstate == BRCMF_BUS_DOWN) {
3694
if (!(brcmf_sdbrcm_download_firmware(bus)))
3701
/* Start the watchdog timer */
3702
bus->drvr->tickcnt = 0;
3703
brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3707
/* Make sure backplane clock is on, needed to generate F2 interrupt */
3708
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3709
if (bus->clkstate != CLK_AVAIL)
3712
/* Force clocks on backplane to be sure F2 interrupt propagates */
3714
brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3715
SBSDIO_FUNC1_CHIPCLKCSR, &err);
3717
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3718
SBSDIO_FUNC1_CHIPCLKCSR,
3719
(saveclk | SBSDIO_FORCE_HT), &err);
3722
brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3726
/* Enable function 2 (frame transfers) */
3727
w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3728
offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3729
enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3731
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3734
timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3736
while (enable != ready) {
3737
ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3738
SDIO_CCCR_IORx, NULL);
3739
if (time_after(jiffies, timeout))
3741
else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3742
/* prevent busy waiting if it takes too long */
3743
msleep_interruptible(20);
3746
brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3748
/* If F2 successfully enabled, set core and enable interrupts */
3749
if (ready == enable) {
3750
/* Set up the interrupt mask and enable interrupts */
3751
bus->hostintmask = HOSTINTMASK;
3752
w_sdreg32(bus, bus->hostintmask,
3753
offsetof(struct sdpcmd_regs, hostintmask), &retries);
3755
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3756
SBSDIO_WATERMARK, 8, &err);
3758
/* Set bus state according to enable result */
3759
drvr->busstate = BRCMF_BUS_DATA;
3763
/* Disable F2 again */
3764
enable = SDIO_FUNC_ENABLE_1;
3765
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3766
SDIO_CCCR_IOEx, enable, NULL);
3769
/* Restore previous clock setting */
3770
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3771
SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3773
/* If we didn't come up, turn off backplane clock */
3774
if (drvr->busstate != BRCMF_BUS_DATA)
3775
brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3783
void brcmf_sdbrcm_isr(void *arg)
3785
struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3787
brcmf_dbg(TRACE, "Enter\n");
3790
brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3794
if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3795
brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3798
/* Count the interrupt call */
3802
/* Shouldn't get this interrupt if we're sleeping? */
3803
if (bus->sleeping) {
3804
brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3808
/* Disable additional interrupts (is this needed now)? */
3810
brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3812
bus->dpc_sched = true;
3814
complete(&bus->dpc_wait);
3817
static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3819
struct brcmf_bus *bus;
3821
brcmf_dbg(TIMER, "Enter\n");
3825
/* Ignore the timer if simulating bus down */
3831
/* Poll period: check device if appropriate. */
3832
if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3835
/* Reset poll tick */
3838
/* Check device if no interrupts */
3839
if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3841
if (!bus->dpc_sched) {
3843
devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3844
SDIO_FUNC_0, SDIO_CCCR_INTx,
3847
devpend & (INTR_STATUS_FUNC1 |
3851
/* If there is something, make like the ISR and
3857
bus->dpc_sched = true;
3859
complete(&bus->dpc_wait);
3863
/* Update interrupt tracking */
3864
bus->lastintrs = bus->intrcount;
3867
/* Poll for console output periodically */
3868
if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3869
bus->console.count += BRCMF_WD_POLL_MS;
3870
if (bus->console.count >= bus->console_interval) {
3871
bus->console.count -= bus->console_interval;
3872
/* Make sure backplane clock is on */
3873
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3874
if (brcmf_sdbrcm_readconsole(bus) < 0)
3876
bus->console_interval = 0;
3881
/* On idle timeout clear activity flag and/or turn off clock */
3882
if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3883
if (++bus->idlecount >= bus->idletime) {
3885
if (bus->activity) {
3886
bus->activity = false;
3887
brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3889
brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3899
static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3901
if (chipid == BCM4329_CHIP_ID)
3906
static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3908
brcmf_dbg(TRACE, "Enter\n");
3911
bus->rxctl = bus->rxbuf = NULL;
3914
kfree(bus->databuf);
3915
bus->databuf = NULL;
3918
static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3920
brcmf_dbg(TRACE, "Enter\n");
3922
if (bus->drvr->maxctl) {
3924
roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3925
ALIGNMENT) + BRCMF_SDALIGN;
3926
bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3931
/* Allocate buffer to receive glomed packet */
3932
bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3933
if (!(bus->databuf)) {
3934
/* release rxbuf which was already located as above */
3940
/* Align the buffer */
3941
if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3942
bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3943
((unsigned long)bus->databuf % BRCMF_SDALIGN));
3945
bus->dataptr = bus->databuf;
3953
/* SDIO Pad drive strength to select value mappings */
3954
struct sdiod_drive_str {
3955
u8 strength; /* Pad Drive Strength in mA */
3956
u8 sel; /* Chip-specific select value */
3959
/* SDIO Drive Strength to sel value table for PMU Rev 1 */
3960
static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3968
/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3969
static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3980
/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3981
static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
3993
#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
3995
static char *brcmf_chipname(uint chipid, char *buf, uint len)
3999
fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
4000
snprintf(buf, len, fmt, chipid);
4004
static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
4005
u32 drivestrength) {
4006
struct sdiod_drive_str *str_tab = NULL;
4011
if (!(bus->ci->cccaps & CC_CAP_PMU))
4014
switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4015
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4016
str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4017
str_mask = 0x30000000;
4020
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4021
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4022
str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4023
str_mask = 0x00003800;
4026
case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4027
str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4028
str_mask = 0x00003800;
4032
brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4033
brcmf_chipname(bus->ci->chip, chn, 8),
4034
bus->ci->chiprev, bus->ci->pmurev);
4038
if (str_tab != NULL) {
4039
u32 drivestrength_sel = 0;
4043
for (i = 0; str_tab[i].strength != 0; i++) {
4044
if (drivestrength >= str_tab[i].strength) {
4045
drivestrength_sel = str_tab[i].sel;
4050
brcmf_sdcard_reg_write(bus->sdiodev,
4051
CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4053
cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4054
CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4055
cc_data_temp &= ~str_mask;
4056
drivestrength_sel <<= str_shift;
4057
cc_data_temp |= drivestrength_sel;
4058
brcmf_sdcard_reg_write(bus->sdiodev,
4059
CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4062
brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4063
drivestrength, cc_data_temp);
4068
brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4069
struct chip_info *ci, u32 regs)
4075
* Chipid is assume to be at offset 0 from regs arg
4076
* For different chiptypes or old sdio hosts w/o chipcommon,
4077
* other ways of recognition should be added here.
4079
ci->cccorebase = regs;
4080
regdata = brcmf_sdcard_reg_read(sdiodev,
4081
CORE_CC_REG(ci->cccorebase, chipid), 4);
4082
ci->chip = regdata & CID_ID_MASK;
4083
ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4085
brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4087
/* Address of cores for new chips should be added here */
4089
case BCM4329_CHIP_ID:
4090
ci->buscorebase = BCM4329_CORE_BUS_BASE;
4091
ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4092
ci->armcorebase = BCM4329_CORE_ARM_BASE;
4093
ci->ramsize = BCM4329_RAMSIZE;
4096
brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4100
regdata = brcmf_sdcard_reg_read(sdiodev,
4101
CORE_SB(ci->cccorebase, sbidhigh), 4);
4102
ci->ccrev = SBCOREREV(regdata);
4104
regdata = brcmf_sdcard_reg_read(sdiodev,
4105
CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4106
ci->pmurev = regdata & PCAP_REV_MASK;
4108
regdata = brcmf_sdcard_reg_read(sdiodev,
4109
CORE_SB(ci->buscorebase, sbidhigh), 4);
4110
ci->buscorerev = SBCOREREV(regdata);
4111
ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4113
brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4114
ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4116
/* get chipcommon capabilites */
4117
ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4118
CORE_CC_REG(ci->cccorebase, capabilities), 4);
4124
brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4126
struct chip_info *ci;
4130
brcmf_dbg(TRACE, "Enter\n");
4132
/* alloc chip_info_t */
4133
ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4137
/* bus/core/clk setup for register access */
4138
/* Try forcing SDIO core to do ALPAvail request only */
4139
clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4140
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4141
SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4143
brcmf_dbg(ERROR, "error writing for HT off\n");
4147
/* If register supported, wait for ALPAvail and then force ALP */
4148
/* This may take up to 15 milliseconds */
4149
clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4150
SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4151
if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4153
brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4154
SBSDIO_FUNC1_CHIPCLKCSR,
4156
!SBSDIO_ALPAV(clkval)),
4157
PMU_MAX_TRANSITION_DLY);
4158
if (!SBSDIO_ALPAV(clkval)) {
4159
brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4164
clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4166
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4167
SBSDIO_FUNC1_CHIPCLKCSR,
4171
brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4177
/* Also, disable the extra SDIO pull-ups */
4178
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4179
SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4181
err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4186
* Make sure any on-chip ARM is off (in case strapping is wrong),
4187
* or downloaded code was already running.
4189
brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4191
brcmf_sdcard_reg_write(bus->sdiodev,
4192
CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4193
brcmf_sdcard_reg_write(bus->sdiodev,
4194
CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4196
/* Disable F2 to clear any intermediate frame state on the dongle */
4197
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4198
SDIO_FUNC_ENABLE_1, NULL);
4200
/* WAR: cmd52 backplane read so core HW will drop ALPReq */
4201
clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4204
/* Done with backplane-dependent accesses, can drop clock... */
4205
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4206
SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4217
brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4224
bus->alp_only = true;
4226
/* Return the window to backplane enumeration space for core access */
4227
if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4228
brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4231
printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4232
brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4237
* Force PLL off until brcmf_sdbrcm_chip_attach()
4238
* programs PLL control regs
4241
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4242
SBSDIO_FUNC1_CHIPCLKCSR,
4243
BRCMF_INIT_CLKCTL1, &err);
4246
brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4247
SBSDIO_FUNC1_CHIPCLKCSR, &err);
4249
if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4250
brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4251
err, BRCMF_INIT_CLKCTL1, clkctl);
4255
if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4256
brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4260
if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4261
brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4265
brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
4267
/* Get info on the ARM and SOCRAM cores... */
4268
brcmf_sdcard_reg_read(bus->sdiodev,
4269
CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4270
bus->ramsize = bus->ci->ramsize;
4271
if (!(bus->ramsize)) {
4272
brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4276
/* Set core control so an SDIO reset does a backplane reset */
4277
reg_addr = bus->ci->buscorebase +
4278
offsetof(struct sdpcmd_regs, corecontrol);
4279
reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4280
brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4281
reg_val | CC_BPRESEN);
4283
brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4285
/* Locate an appropriately-aligned portion of hdrbuf */
4286
bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4289
/* Set the poll and/or interrupt flags */
4301
static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4303
brcmf_dbg(TRACE, "Enter\n");
4305
/* Disable F2 to clear any intermediate frame state on the dongle */
4306
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4307
SDIO_FUNC_ENABLE_1, NULL);
4309
bus->drvr->busstate = BRCMF_BUS_DOWN;
4310
bus->sleeping = false;
4311
bus->rxflow = false;
4313
/* Done with backplane-dependent accesses, can drop clock... */
4314
brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4315
SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4317
/* ...and initialize clock/power states */
4318
bus->clkstate = CLK_SDONLY;
4319
bus->idletime = BRCMF_IDLE_INTERVAL;
4320
bus->idleclock = BRCMF_IDLE_ACTIVE;
4322
/* Query the F2 block size, set roundup accordingly */
4323
bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4324
bus->roundup = min(max_roundup, bus->blocksize);
4326
/* bus module does not support packet chaining */
4327
bus->use_rxchain = false;
4328
bus->sd_rxchain = false;
4334
brcmf_sdbrcm_watchdog_thread(void *data)
4336
struct brcmf_bus *bus = (struct brcmf_bus *)data;
4338
allow_signal(SIGTERM);
4339
/* Run until signal received */
4341
if (kthread_should_stop())
4343
if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4344
brcmf_sdbrcm_bus_watchdog(bus->drvr);
4345
/* Count the tick for reference */
4346
bus->drvr->tickcnt++;
4354
brcmf_sdbrcm_watchdog(unsigned long data)
4356
struct brcmf_bus *bus = (struct brcmf_bus *)data;
4358
if (bus->watchdog_tsk) {
4359
complete(&bus->watchdog_wait);
4360
/* Reschedule the watchdog */
4361
if (bus->wd_timer_valid)
4362
mod_timer(&bus->timer,
4363
jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4368
brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4370
brcmf_dbg(TRACE, "Enter\n");
4376
static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4378
brcmf_dbg(TRACE, "Enter\n");
4381
brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4382
brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4383
brcmf_sdbrcm_chip_detach(bus);
4384
if (bus->vars && bus->varsz)
4389
brcmf_dbg(TRACE, "Disconnected\n");
4392
/* Detach and free everything */
4393
static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4395
brcmf_dbg(TRACE, "Enter\n");
4398
/* De-register interrupt handler */
4399
brcmf_sdcard_intr_dereg(bus->sdiodev);
4402
brcmf_detach(bus->drvr);
4403
brcmf_sdbrcm_release_dongle(bus);
4407
brcmf_sdbrcm_release_malloc(bus);
4412
brcmf_dbg(TRACE, "Disconnected\n");
4415
void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4416
u32 regsva, struct brcmf_sdio_dev *sdiodev)
4419
struct brcmf_bus *bus;
4421
/* Init global variables at run-time, not as part of the declaration.
4422
* This is required to support init/de-init of the driver.
4424
* of globals as part of the declaration results in non-deterministic
4425
* behavior since the value of the globals may be different on the
4426
* first time that the driver is initialized vs subsequent
4431
brcmf_dbg(TRACE, "Enter\n");
4433
/* We make an assumption about address window mappings:
4434
* regsva == SI_ENUM_BASE*/
4436
/* Allocate private bus interface state */
4437
bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4441
bus->sdiodev = sdiodev;
4443
bus->txbound = BRCMF_TXBOUND;
4444
bus->rxbound = BRCMF_RXBOUND;
4445
bus->txminmax = BRCMF_TXMINMAX;
4446
bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4447
bus->usebufpool = false; /* Use bufpool if allocated,
4448
else use locally malloced rxbuf */
4450
/* attempt to attach to the dongle */
4451
if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4452
brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4456
spin_lock_init(&bus->txqlock);
4457
init_waitqueue_head(&bus->ctrl_wait);
4458
init_waitqueue_head(&bus->dcmd_resp_wait);
4460
/* Set up the watchdog timer */
4461
init_timer(&bus->timer);
4462
bus->timer.data = (unsigned long)bus;
4463
bus->timer.function = brcmf_sdbrcm_watchdog;
4465
/* Initialize thread based operation and lock */
4466
sema_init(&bus->sdsem, 1);
4468
/* Initialize watchdog thread */
4469
init_completion(&bus->watchdog_wait);
4470
bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4471
bus, "brcmf_watchdog");
4472
if (IS_ERR(bus->watchdog_tsk)) {
4474
"brcmf_watchdog thread failed to start\n");
4475
bus->watchdog_tsk = NULL;
4477
/* Initialize DPC thread */
4478
init_completion(&bus->dpc_wait);
4479
bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4481
if (IS_ERR(bus->dpc_tsk)) {
4483
"brcmf_dpc thread failed to start\n");
4484
bus->dpc_tsk = NULL;
4487
/* Attach to the brcmf/OS/network interface */
4488
bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4490
brcmf_dbg(ERROR, "brcmf_attach failed\n");
4494
/* Allocate buffers */
4495
if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4496
brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4500
if (!(brcmf_sdbrcm_probe_init(bus))) {
4501
brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4505
/* Register interrupt callback, but mask it (not operational yet). */
4506
brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4507
ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4509
brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4512
brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4514
brcmf_dbg(INFO, "completed!!\n");
4516
/* if firmware path present try to download and bring up bus */
4517
ret = brcmf_bus_start(bus->drvr);
4519
if (ret == -ENOLINK) {
4520
brcmf_dbg(ERROR, "dongle is not responding\n");
4524
/* Ok, have the per-port tell the stack we're open for business */
4525
if (brcmf_net_attach(bus->drvr, 0) != 0) {
4526
brcmf_dbg(ERROR, "Net attach failed!!\n");
4533
brcmf_sdbrcm_release(bus);
4537
void brcmf_sdbrcm_disconnect(void *ptr)
4539
struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4541
brcmf_dbg(TRACE, "Enter\n");
4544
brcmf_sdbrcm_release(bus);
4546
brcmf_dbg(TRACE, "Disconnected\n");
4549
struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4551
return &bus->sdiodev->func[2]->dev;
4555
brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4557
/* don't start the wd until fw is loaded */
4558
if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4561
/* Totally stop the timer */
4562
if (!wdtick && bus->wd_timer_valid == true) {
4563
del_timer_sync(&bus->timer);
4564
bus->wd_timer_valid = false;
4565
bus->save_ms = wdtick;
4570
if (bus->save_ms != BRCMF_WD_POLL_MS) {
4571
if (bus->wd_timer_valid == true)
4572
/* Stop timer and restart at new value */
4573
del_timer_sync(&bus->timer);
4575
/* Create timer again when watchdog period is
4576
dynamically changed or in the first instance
4578
bus->timer.expires =
4579
jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4580
add_timer(&bus->timer);
4583
/* Re arm the timer, at last watchdog period */
4584
mod_timer(&bus->timer,
4585
jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4588
bus->wd_timer_valid = true;
4589
bus->save_ms = wdtick;