2
* Copyright (c) 2010-2011 Atheros Communications Inc.
4
* Permission to use, copy, modify, and/or distribute this software for any
5
* purpose with or without fee is hereby granted, provided that the above
6
* copyright notice and this permission notice appear in all copies.
8
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19
MODULE_AUTHOR("Atheros Communications");
20
MODULE_LICENSE("Dual BSD/GPL");
21
MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
23
static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
24
module_param_named(debug, ath9k_debug, uint, 0);
25
MODULE_PARM_DESC(debug, "Debugging mask");
27
int htc_modparam_nohwcrypt;
28
module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
29
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
#define CHAN2G(_freq, _idx) { \
32
.center_freq = (_freq), \
37
#define CHAN5G(_freq, _idx) { \
38
.band = IEEE80211_BAND_5GHZ, \
39
.center_freq = (_freq), \
44
#define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
46
static struct ieee80211_channel ath9k_2ghz_channels[] = {
47
CHAN2G(2412, 0), /* Channel 1 */
48
CHAN2G(2417, 1), /* Channel 2 */
49
CHAN2G(2422, 2), /* Channel 3 */
50
CHAN2G(2427, 3), /* Channel 4 */
51
CHAN2G(2432, 4), /* Channel 5 */
52
CHAN2G(2437, 5), /* Channel 6 */
53
CHAN2G(2442, 6), /* Channel 7 */
54
CHAN2G(2447, 7), /* Channel 8 */
55
CHAN2G(2452, 8), /* Channel 9 */
56
CHAN2G(2457, 9), /* Channel 10 */
57
CHAN2G(2462, 10), /* Channel 11 */
58
CHAN2G(2467, 11), /* Channel 12 */
59
CHAN2G(2472, 12), /* Channel 13 */
60
CHAN2G(2484, 13), /* Channel 14 */
63
static struct ieee80211_channel ath9k_5ghz_channels[] = {
64
/* _We_ call this UNII 1 */
65
CHAN5G(5180, 14), /* Channel 36 */
66
CHAN5G(5200, 15), /* Channel 40 */
67
CHAN5G(5220, 16), /* Channel 44 */
68
CHAN5G(5240, 17), /* Channel 48 */
69
/* _We_ call this UNII 2 */
70
CHAN5G(5260, 18), /* Channel 52 */
71
CHAN5G(5280, 19), /* Channel 56 */
72
CHAN5G(5300, 20), /* Channel 60 */
73
CHAN5G(5320, 21), /* Channel 64 */
74
/* _We_ call this "Middle band" */
75
CHAN5G(5500, 22), /* Channel 100 */
76
CHAN5G(5520, 23), /* Channel 104 */
77
CHAN5G(5540, 24), /* Channel 108 */
78
CHAN5G(5560, 25), /* Channel 112 */
79
CHAN5G(5580, 26), /* Channel 116 */
80
CHAN5G(5600, 27), /* Channel 120 */
81
CHAN5G(5620, 28), /* Channel 124 */
82
CHAN5G(5640, 29), /* Channel 128 */
83
CHAN5G(5660, 30), /* Channel 132 */
84
CHAN5G(5680, 31), /* Channel 136 */
85
CHAN5G(5700, 32), /* Channel 140 */
86
/* _We_ call this UNII 3 */
87
CHAN5G(5745, 33), /* Channel 149 */
88
CHAN5G(5765, 34), /* Channel 153 */
89
CHAN5G(5785, 35), /* Channel 157 */
90
CHAN5G(5805, 36), /* Channel 161 */
91
CHAN5G(5825, 37), /* Channel 165 */
94
/* Atheros hardware rate code addition for short premble */
95
#define SHPCHECK(__hw_rate, __flags) \
96
((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
98
#define RATE(_bitrate, _hw_rate, _flags) { \
99
.bitrate = (_bitrate), \
101
.hw_value = (_hw_rate), \
102
.hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
105
static struct ieee80211_rate ath9k_legacy_rates[] = {
107
RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
108
RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
109
RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
120
#ifdef CONFIG_MAC80211_LEDS
121
static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
122
{ .throughput = 0 * 1024, .blink_time = 334 },
123
{ .throughput = 1 * 1024, .blink_time = 260 },
124
{ .throughput = 5 * 1024, .blink_time = 220 },
125
{ .throughput = 10 * 1024, .blink_time = 190 },
126
{ .throughput = 20 * 1024, .blink_time = 170 },
127
{ .throughput = 50 * 1024, .blink_time = 150 },
128
{ .throughput = 70 * 1024, .blink_time = 130 },
129
{ .throughput = 100 * 1024, .blink_time = 110 },
130
{ .throughput = 200 * 1024, .blink_time = 80 },
131
{ .throughput = 300 * 1024, .blink_time = 50 },
135
static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
139
if (atomic_read(&priv->htc->tgt_ready) > 0) {
140
atomic_dec(&priv->htc->tgt_ready);
144
/* Firmware can take up to 50ms to get ready, to be safe use 1 second */
145
time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
147
dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
151
atomic_dec(&priv->htc->tgt_ready);
156
static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
158
ath9k_hw_deinit(priv->ah);
163
static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
165
struct ieee80211_hw *hw = priv->hw;
167
wiphy_rfkill_stop_polling(hw->wiphy);
168
ath9k_deinit_leds(priv);
169
ieee80211_unregister_hw(hw);
170
ath9k_rx_cleanup(priv);
171
ath9k_tx_cleanup(priv);
172
ath9k_deinit_priv(priv);
175
static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
179
enum htc_endpoint_id,
181
enum htc_endpoint_id *ep_id)
183
struct htc_service_connreq req;
185
memset(&req, 0, sizeof(struct htc_service_connreq));
187
req.service_id = service_id;
188
req.ep_callbacks.priv = priv;
189
req.ep_callbacks.rx = ath9k_htc_rxep;
190
req.ep_callbacks.tx = tx;
192
return htc_connect_service(priv->htc, &req, ep_id);
195
static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
201
ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
206
ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
212
ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
219
ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
225
ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
231
ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
237
ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
243
ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
249
ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
255
* Setup required credits before initializing HTC.
256
* This is a bit hacky, but, since queuing is done in
257
* the HIF layer, shouldn't matter much.
260
if (IS_AR7010_DEVICE(drv_info))
261
priv->htc->credits = 45;
263
priv->htc->credits = 33;
265
ret = htc_init(priv->htc);
269
dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
275
dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
279
static int ath9k_reg_notifier(struct wiphy *wiphy,
280
struct regulatory_request *request)
282
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
283
struct ath9k_htc_priv *priv = hw->priv;
285
return ath_reg_notifier_apply(wiphy, request,
286
ath9k_hw_regulatory(priv->ah));
289
static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
291
struct ath_hw *ah = (struct ath_hw *) hw_priv;
292
struct ath_common *common = ath9k_hw_common(ah);
293
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
294
__be32 val, reg = cpu_to_be32(reg_offset);
297
r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
298
(u8 *) ®, sizeof(reg),
299
(u8 *) &val, sizeof(val),
302
ath_dbg(common, ATH_DBG_WMI,
303
"REGISTER READ FAILED: (0x%04x, %d)\n",
308
return be32_to_cpu(val);
311
static void ath9k_multi_regread(void *hw_priv, u32 *addr,
314
struct ath_hw *ah = (struct ath_hw *) hw_priv;
315
struct ath_common *common = ath9k_hw_common(ah);
316
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
321
for (i = 0; i < count; i++) {
322
tmpaddr[i] = cpu_to_be32(addr[i]);
325
ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
326
(u8 *)tmpaddr , sizeof(u32) * count,
327
(u8 *)tmpval, sizeof(u32) * count,
330
ath_dbg(common, ATH_DBG_WMI,
331
"Multiple REGISTER READ FAILED (count: %d)\n", count);
334
for (i = 0; i < count; i++) {
335
val[i] = be32_to_cpu(tmpval[i]);
339
static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
341
struct ath_hw *ah = (struct ath_hw *) hw_priv;
342
struct ath_common *common = ath9k_hw_common(ah);
343
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
344
const __be32 buf[2] = {
345
cpu_to_be32(reg_offset),
350
r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
351
(u8 *) &buf, sizeof(buf),
352
(u8 *) &val, sizeof(val),
355
ath_dbg(common, ATH_DBG_WMI,
356
"REGISTER WRITE FAILED:(0x%04x, %d)\n",
361
static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
363
struct ath_hw *ah = (struct ath_hw *) hw_priv;
364
struct ath_common *common = ath9k_hw_common(ah);
365
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
369
mutex_lock(&priv->wmi->multi_write_mutex);
371
/* Store the register/value */
372
priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
373
cpu_to_be32(reg_offset);
374
priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
377
priv->wmi->multi_write_idx++;
379
/* If the buffer is full, send it out. */
380
if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
381
r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
382
(u8 *) &priv->wmi->multi_write,
383
sizeof(struct register_write) * priv->wmi->multi_write_idx,
384
(u8 *) &rsp_status, sizeof(rsp_status),
387
ath_dbg(common, ATH_DBG_WMI,
388
"REGISTER WRITE FAILED, multi len: %d\n",
389
priv->wmi->multi_write_idx);
391
priv->wmi->multi_write_idx = 0;
394
mutex_unlock(&priv->wmi->multi_write_mutex);
397
static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
399
struct ath_hw *ah = (struct ath_hw *) hw_priv;
400
struct ath_common *common = ath9k_hw_common(ah);
401
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
403
if (atomic_read(&priv->wmi->mwrite_cnt))
404
ath9k_regwrite_buffer(hw_priv, val, reg_offset);
406
ath9k_regwrite_single(hw_priv, val, reg_offset);
409
static void ath9k_enable_regwrite_buffer(void *hw_priv)
411
struct ath_hw *ah = (struct ath_hw *) hw_priv;
412
struct ath_common *common = ath9k_hw_common(ah);
413
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
415
atomic_inc(&priv->wmi->mwrite_cnt);
418
static void ath9k_regwrite_flush(void *hw_priv)
420
struct ath_hw *ah = (struct ath_hw *) hw_priv;
421
struct ath_common *common = ath9k_hw_common(ah);
422
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
426
atomic_dec(&priv->wmi->mwrite_cnt);
428
mutex_lock(&priv->wmi->multi_write_mutex);
430
if (priv->wmi->multi_write_idx) {
431
r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
432
(u8 *) &priv->wmi->multi_write,
433
sizeof(struct register_write) * priv->wmi->multi_write_idx,
434
(u8 *) &rsp_status, sizeof(rsp_status),
437
ath_dbg(common, ATH_DBG_WMI,
438
"REGISTER WRITE FAILED, multi len: %d\n",
439
priv->wmi->multi_write_idx);
441
priv->wmi->multi_write_idx = 0;
444
mutex_unlock(&priv->wmi->multi_write_mutex);
447
static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
451
val = ath9k_regread(hw_priv, reg_offset);
454
ath9k_regwrite(hw_priv, val, reg_offset);
458
static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
460
*csz = L1_CACHE_BYTES >> 2;
463
static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
465
struct ath_hw *ah = (struct ath_hw *) common->ah;
467
(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
469
if (!ath9k_hw_wait(ah,
470
AR_EEPROM_STATUS_DATA,
471
AR_EEPROM_STATUS_DATA_BUSY |
472
AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
476
*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
477
AR_EEPROM_STATUS_DATA_VAL);
482
static const struct ath_bus_ops ath9k_usb_bus_ops = {
483
.ath_bus_type = ATH_USB,
484
.read_cachesize = ath_usb_read_cachesize,
485
.eeprom_read = ath_usb_eeprom_read,
488
static void setup_ht_cap(struct ath9k_htc_priv *priv,
489
struct ieee80211_sta_ht_cap *ht_info)
491
struct ath_common *common = ath9k_hw_common(priv->ah);
492
u8 tx_streams, rx_streams;
495
ht_info->ht_supported = true;
496
ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
497
IEEE80211_HT_CAP_SM_PS |
498
IEEE80211_HT_CAP_SGI_40 |
499
IEEE80211_HT_CAP_DSSSCCK40;
501
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
502
ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
504
ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
506
ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
507
ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
509
memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
511
/* ath9k_htc supports only 1 or 2 stream devices */
512
tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2);
513
rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2);
515
ath_dbg(common, ATH_DBG_CONFIG,
516
"TX streams %d, RX streams: %d\n",
517
tx_streams, rx_streams);
519
if (tx_streams != rx_streams) {
520
ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
521
ht_info->mcs.tx_params |= ((tx_streams - 1) <<
522
IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
525
for (i = 0; i < rx_streams; i++)
526
ht_info->mcs.rx_mask[i] = 0xff;
528
ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
531
static int ath9k_init_queues(struct ath9k_htc_priv *priv)
533
struct ath_common *common = ath9k_hw_common(priv->ah);
536
for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
537
priv->hwq_map[i] = -1;
539
priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
540
if (priv->beaconq == -1) {
541
ath_err(common, "Unable to setup BEACON xmit queue\n");
545
priv->cabq = ath9k_htc_cabq_setup(priv);
546
if (priv->cabq == -1) {
547
ath_err(common, "Unable to setup CAB xmit queue\n");
551
if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
552
ath_err(common, "Unable to setup xmit queue for BE traffic\n");
556
if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
557
ath_err(common, "Unable to setup xmit queue for BK traffic\n");
560
if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
561
ath_err(common, "Unable to setup xmit queue for VI traffic\n");
564
if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
565
ath_err(common, "Unable to setup xmit queue for VO traffic\n");
575
static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
577
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
578
priv->sbands[IEEE80211_BAND_2GHZ].channels =
580
priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
581
priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
582
ARRAY_SIZE(ath9k_2ghz_channels);
583
priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
584
priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
585
ARRAY_SIZE(ath9k_legacy_rates);
588
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
589
priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
590
priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
591
priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
592
ARRAY_SIZE(ath9k_5ghz_channels);
593
priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
594
ath9k_legacy_rates + 4;
595
priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
596
ARRAY_SIZE(ath9k_legacy_rates) - 4;
600
static void ath9k_init_misc(struct ath9k_htc_priv *priv)
602
struct ath_common *common = ath9k_hw_common(priv->ah);
604
memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
606
priv->ah->opmode = NL80211_IFTYPE_STATION;
609
static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
613
switch (priv->ah->btcoex_hw.scheme) {
614
case ATH_BTCOEX_CFG_NONE:
616
case ATH_BTCOEX_CFG_3WIRE:
617
priv->ah->btcoex_hw.btactive_gpio = 7;
618
priv->ah->btcoex_hw.btpriority_gpio = 6;
619
priv->ah->btcoex_hw.wlanactive_gpio = 8;
620
priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
621
ath9k_hw_btcoex_init_3wire(priv->ah);
622
ath_htc_init_btcoex_work(priv);
623
qnum = priv->hwq_map[WME_AC_BE];
624
ath9k_hw_init_btcoex_hw(priv->ah, qnum);
632
static int ath9k_init_priv(struct ath9k_htc_priv *priv,
633
u16 devid, char *product,
636
struct ath_hw *ah = NULL;
637
struct ath_common *common;
638
int i, ret = 0, csz = 0;
640
priv->op_flags |= OP_INVALID;
642
ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
646
ah->hw_version.devid = devid;
647
ah->hw_version.usbdev = drv_info;
648
ah->ah_flags |= AH_USE_EEPROM;
649
ah->reg_ops.read = ath9k_regread;
650
ah->reg_ops.multi_read = ath9k_multi_regread;
651
ah->reg_ops.write = ath9k_regwrite;
652
ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
653
ah->reg_ops.write_flush = ath9k_regwrite_flush;
654
ah->reg_ops.rmw = ath9k_reg_rmw;
657
common = ath9k_hw_common(ah);
658
common->ops = &ah->reg_ops;
659
common->bus_ops = &ath9k_usb_bus_ops;
661
common->hw = priv->hw;
663
common->debug_mask = ath9k_debug;
665
spin_lock_init(&priv->beacon_lock);
666
spin_lock_init(&priv->tx.tx_lock);
667
mutex_init(&priv->mutex);
668
mutex_init(&priv->htc_pm_lock);
669
tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
670
(unsigned long)priv);
671
tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
672
(unsigned long)priv);
673
INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
674
INIT_WORK(&priv->ps_work, ath9k_ps_work);
675
INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
676
setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
677
(unsigned long)priv);
680
* Cache line size is used to size and align various
681
* structures used to communicate with the hardware.
683
ath_read_cachesize(common, &csz);
684
common->cachelsz = csz << 2; /* convert to bytes */
686
ret = ath9k_hw_init(ah);
689
"Unable to initialize hardware; initialization status: %d\n",
694
ret = ath9k_init_queues(priv);
698
for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
699
priv->cur_beacon_conf.bslot[i] = NULL;
701
ath9k_cmn_init_crypto(ah);
702
ath9k_init_channels_rates(priv);
703
ath9k_init_misc(priv);
705
if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
706
ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
707
ath9k_init_btcoex(priv);
722
static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
723
struct ieee80211_hw *hw)
725
struct ath_common *common = ath9k_hw_common(priv->ah);
727
hw->flags = IEEE80211_HW_SIGNAL_DBM |
728
IEEE80211_HW_AMPDU_AGGREGATION |
729
IEEE80211_HW_SPECTRUM_MGMT |
730
IEEE80211_HW_HAS_RATE_CONTROL |
731
IEEE80211_HW_RX_INCLUDES_FCS |
732
IEEE80211_HW_SUPPORTS_PS |
733
IEEE80211_HW_PS_NULLFUNC_STACK |
734
IEEE80211_HW_REPORTS_TX_ACK_STATUS |
735
IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
737
hw->wiphy->interface_modes =
738
BIT(NL80211_IFTYPE_STATION) |
739
BIT(NL80211_IFTYPE_ADHOC) |
740
BIT(NL80211_IFTYPE_AP) |
741
BIT(NL80211_IFTYPE_P2P_GO) |
742
BIT(NL80211_IFTYPE_P2P_CLIENT);
744
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
747
hw->channel_change_time = 5000;
748
hw->max_listen_interval = 10;
750
hw->vif_data_size = sizeof(struct ath9k_htc_vif);
751
hw->sta_data_size = sizeof(struct ath9k_htc_sta);
753
/* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
754
hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
755
sizeof(struct htc_frame_hdr) + 4;
757
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
758
hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
759
&priv->sbands[IEEE80211_BAND_2GHZ];
760
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
761
hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
762
&priv->sbands[IEEE80211_BAND_5GHZ];
764
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
765
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
767
&priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
768
if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
770
&priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
773
SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
776
static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
778
struct ieee80211_hw *hw = priv->hw;
779
struct wmi_fw_version cmd_rsp;
782
memset(&cmd_rsp, 0, sizeof(cmd_rsp));
784
WMI_CMD(WMI_GET_FW_VERSION);
788
priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
789
priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
791
snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
792
priv->fw_version_major,
793
priv->fw_version_minor);
795
dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
796
priv->fw_version_major,
797
priv->fw_version_minor);
800
* Check if the available FW matches the driver's
803
if (priv->fw_version_major != MAJOR_VERSION_REQ ||
804
priv->fw_version_minor != MINOR_VERSION_REQ) {
805
dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
806
MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
813
static int ath9k_init_device(struct ath9k_htc_priv *priv,
814
u16 devid, char *product, u32 drv_info)
816
struct ieee80211_hw *hw = priv->hw;
817
struct ath_common *common;
820
struct ath_regulatory *reg;
823
/* Bring up device */
824
error = ath9k_init_priv(priv, devid, product, drv_info);
829
common = ath9k_hw_common(ah);
830
ath9k_set_hw_capab(priv, hw);
832
error = ath9k_init_firmware_version(priv);
836
/* Initialize regulatory */
837
error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
842
reg = &common->regulatory;
845
error = ath9k_tx_init(priv);
850
error = ath9k_rx_init(priv);
854
#ifdef CONFIG_MAC80211_LEDS
855
/* must be initialized before ieee80211_register_hw */
856
priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
857
IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
858
ARRAY_SIZE(ath9k_htc_tpt_blink));
861
/* Register with mac80211 */
862
error = ieee80211_register_hw(hw);
866
/* Handle world regulatory */
867
if (!ath_is_world_regd(reg)) {
868
error = regulatory_hint(hw->wiphy, reg->alpha2);
873
error = ath9k_htc_init_debug(priv->ah);
875
ath_err(common, "Unable to create debugfs files\n");
879
ath_dbg(common, ATH_DBG_CONFIG,
880
"WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, "
881
"BE:%d, BK:%d, VI:%d, VO:%d\n",
892
ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
893
wiphy_info(hw->wiphy, "%s\n", hw_name);
895
ath9k_init_leds(priv);
896
ath9k_start_rfkill_poll(priv);
901
ieee80211_unregister_hw(hw);
903
ath9k_rx_cleanup(priv);
905
ath9k_tx_cleanup(priv);
911
ath9k_deinit_priv(priv);
916
int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
917
u16 devid, char *product, u32 drv_info)
919
struct ieee80211_hw *hw;
920
struct ath9k_htc_priv *priv;
923
hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
929
priv->htc = htc_handle;
931
htc_handle->drv_priv = priv;
932
SET_IEEE80211_DEV(hw, priv->dev);
934
ret = ath9k_htc_wait_for_target(priv);
938
priv->wmi = ath9k_init_wmi(priv);
944
ret = ath9k_init_htc_services(priv, devid, drv_info);
948
ret = ath9k_init_device(priv, devid, product, drv_info);
955
ath9k_deinit_wmi(priv);
957
ieee80211_free_hw(hw);
961
void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
963
if (htc_handle->drv_priv) {
965
/* Check if the device has been yanked out. */
967
htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
969
ath9k_deinit_device(htc_handle->drv_priv);
970
ath9k_deinit_wmi(htc_handle->drv_priv);
971
ieee80211_free_hw(htc_handle->drv_priv->hw);
977
void ath9k_htc_suspend(struct htc_target *htc_handle)
979
ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
982
int ath9k_htc_resume(struct htc_target *htc_handle)
984
struct ath9k_htc_priv *priv = htc_handle->drv_priv;
987
ret = ath9k_htc_wait_for_target(priv);
991
ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
992
priv->ah->hw_version.usbdev);
997
static int __init ath9k_htc_init(void)
999
if (ath9k_hif_usb_init() < 0) {
1001
"ath9k_htc: No USB devices found,"
1002
" driver not installed.\n");
1008
module_init(ath9k_htc_init);
1010
static void __exit ath9k_htc_exit(void)
1012
ath9k_hif_usb_exit();
1013
printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
1015
module_exit(ath9k_htc_exit);