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  • Committer: Package Import Robot
  • Author(s): Alessio Igor Bogani
  • Date: 2011-10-26 11:13:05 UTC
  • Revision ID: package-import@ubuntu.com-20111026111305-tz023xykf0i6eosh
Tags: upstream-3.2.0
Import upstream version 3.2.0

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arch/powerpc/boot/dts/p2041si.dtsi
 
1
/*
 
2
 * P2041 Silicon Device Tree Source
 
3
 *
 
4
 * Copyright 2011 Freescale Semiconductor Inc.
 
5
 *
 
6
 * Redistribution and use in source and binary forms, with or without
 
7
 * modification, are permitted provided that the following conditions are met:
 
8
 *     * Redistributions of source code must retain the above copyright
 
9
 *       notice, this list of conditions and the following disclaimer.
 
10
 *     * Redistributions in binary form must reproduce the above copyright
 
11
 *       notice, this list of conditions and the following disclaimer in the
 
12
 *       documentation and/or other materials provided with the distribution.
 
13
 *     * Neither the name of Freescale Semiconductor nor the
 
14
 *       names of its contributors may be used to endorse or promote products
 
15
 *       derived from this software without specific prior written permission.
 
16
 *
 
17
 *
 
18
 * ALTERNATIVELY, this software may be distributed under the terms of the
 
19
 * GNU General Public License ("GPL") as published by the Free Software
 
20
 * Foundation, either version 2 of that License or (at your option) any
 
21
 * later version.
 
22
 *
 
23
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 
24
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 
25
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 
26
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 
27
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 
28
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 
29
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 
30
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
31
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
32
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
33
 */
 
34
 
 
35
/dts-v1/;
 
36
 
 
37
/ {
 
38
        compatible = "fsl,P2041";
 
39
        #address-cells = <2>;
 
40
        #size-cells = <2>;
 
41
        interrupt-parent = <&mpic>;
 
42
 
 
43
        aliases {
 
44
                ccsr = &soc;
 
45
                dcsr = &dcsr;
 
46
 
 
47
                serial0 = &serial0;
 
48
                serial1 = &serial1;
 
49
                serial2 = &serial2;
 
50
                serial3 = &serial3;
 
51
                pci0 = &pci0;
 
52
                pci1 = &pci1;
 
53
                pci2 = &pci2;
 
54
                usb0 = &usb0;
 
55
                usb1 = &usb1;
 
56
                dma0 = &dma0;
 
57
                dma1 = &dma1;
 
58
                sdhc = &sdhc;
 
59
                msi0 = &msi0;
 
60
                msi1 = &msi1;
 
61
                msi2 = &msi2;
 
62
 
 
63
                crypto = &crypto;
 
64
                sec_jr0 = &sec_jr0;
 
65
                sec_jr1 = &sec_jr1;
 
66
                sec_jr2 = &sec_jr2;
 
67
                sec_jr3 = &sec_jr3;
 
68
                rtic_a = &rtic_a;
 
69
                rtic_b = &rtic_b;
 
70
                rtic_c = &rtic_c;
 
71
                rtic_d = &rtic_d;
 
72
                sec_mon = &sec_mon;
 
73
        };
 
74
 
 
75
        cpus {
 
76
                #address-cells = <1>;
 
77
                #size-cells = <0>;
 
78
 
 
79
                cpu0: PowerPC,e500mc@0 {
 
80
                        device_type = "cpu";
 
81
                        reg = <0>;
 
82
                        next-level-cache = <&L2_0>;
 
83
                        L2_0: l2-cache {
 
84
                                next-level-cache = <&cpc>;
 
85
                        };
 
86
                };
 
87
                cpu1: PowerPC,e500mc@1 {
 
88
                        device_type = "cpu";
 
89
                        reg = <1>;
 
90
                        next-level-cache = <&L2_1>;
 
91
                        L2_1: l2-cache {
 
92
                                next-level-cache = <&cpc>;
 
93
                        };
 
94
                };
 
95
                cpu2: PowerPC,e500mc@2 {
 
96
                        device_type = "cpu";
 
97
                        reg = <2>;
 
98
                        next-level-cache = <&L2_2>;
 
99
                        L2_2: l2-cache {
 
100
                                next-level-cache = <&cpc>;
 
101
                        };
 
102
                };
 
103
                cpu3: PowerPC,e500mc@3 {
 
104
                        device_type = "cpu";
 
105
                        reg = <3>;
 
106
                        next-level-cache = <&L2_3>;
 
107
                        L2_3: l2-cache {
 
108
                                next-level-cache = <&cpc>;
 
109
                        };
 
110
                };
 
111
        };
 
112
 
 
113
        dcsr: dcsr@f00000000 {
 
114
                #address-cells = <1>;
 
115
                #size-cells = <1>;
 
116
                compatible = "fsl,dcsr", "simple-bus";
 
117
 
 
118
                dcsr-epu@0 {
 
119
                        compatible = "fsl,dcsr-epu";
 
120
                        interrupts = <52 2 0 0
 
121
                                      84 2 0 0
 
122
                                      85 2 0 0>;
 
123
                        interrupt-parent = <&mpic>;
 
124
                        reg = <0x0 0x1000>;
 
125
                };
 
126
                dcsr-npc {
 
127
                        compatible = "fsl,dcsr-npc";
 
128
                        reg = <0x1000 0x1000 0x1000000 0x8000>;
 
129
                };
 
130
                dcsr-nxc@2000 {
 
131
                        compatible = "fsl,dcsr-nxc";
 
132
                        reg = <0x2000 0x1000>;
 
133
                };
 
134
                dcsr-corenet {
 
135
                        compatible = "fsl,dcsr-corenet";
 
136
                        reg = <0x8000 0x1000 0xB0000 0x1000>;
 
137
                };
 
138
                dcsr-dpaa@9000 {
 
139
                        compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
 
140
                        reg = <0x9000 0x1000>;
 
141
                };
 
142
                dcsr-ocn@11000 {
 
143
                        compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
 
144
                        reg = <0x11000 0x1000>;
 
145
                };
 
146
                dcsr-ddr@12000 {
 
147
                        compatible = "fsl,dcsr-ddr";
 
148
                        dev-handle = <&ddr>;
 
149
                        reg = <0x12000 0x1000>;
 
150
                };
 
151
                dcsr-nal@18000 {
 
152
                        compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
 
153
                        reg = <0x18000 0x1000>;
 
154
                };
 
155
                dcsr-rcpm@22000 {
 
156
                        compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
 
157
                        reg = <0x22000 0x1000>;
 
158
                };
 
159
                dcsr-cpu-sb-proxy@40000 {
 
160
                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 
161
                        cpu-handle = <&cpu0>;
 
162
                        reg = <0x40000 0x1000>;
 
163
                };
 
164
                dcsr-cpu-sb-proxy@41000 {
 
165
                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 
166
                        cpu-handle = <&cpu1>;
 
167
                        reg = <0x41000 0x1000>;
 
168
                };
 
169
                dcsr-cpu-sb-proxy@42000 {
 
170
                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 
171
                        cpu-handle = <&cpu2>;
 
172
                        reg = <0x42000 0x1000>;
 
173
                };
 
174
                dcsr-cpu-sb-proxy@43000 {
 
175
                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 
176
                        cpu-handle = <&cpu3>;
 
177
                        reg = <0x43000 0x1000>;
 
178
                };
 
179
        };
 
180
 
 
181
        soc: soc@ffe000000 {
 
182
                #address-cells = <1>;
 
183
                #size-cells = <1>;
 
184
                device_type = "soc";
 
185
                compatible = "simple-bus";
 
186
                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 
187
                reg = <0xf 0xfe000000 0 0x00001000>;
 
188
 
 
189
                soc-sram-error {
 
190
                        compatible = "fsl,soc-sram-error";
 
191
                        interrupts = <16 2 1 29>;
 
192
                };
 
193
 
 
194
                corenet-law@0 {
 
195
                        compatible = "fsl,corenet-law";
 
196
                        reg = <0x0 0x1000>;
 
197
                        fsl,num-laws = <32>;
 
198
                };
 
199
 
 
200
                ddr: memory-controller@8000 {
 
201
                        compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 
202
                        reg = <0x8000 0x1000>;
 
203
                        interrupts = <16 2 1 23>;
 
204
                };
 
205
 
 
206
                cpc: l3-cache-controller@10000 {
 
207
                        compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
 
208
                        reg = <0x10000 0x1000>;
 
209
                        interrupts = <16 2 1 27>;
 
210
                };
 
211
 
 
212
                corenet-cf@18000 {
 
213
                        compatible = "fsl,corenet-cf";
 
214
                        reg = <0x18000 0x1000>;
 
215
                        interrupts = <16 2 1 31>;
 
216
                        fsl,ccf-num-csdids = <32>;
 
217
                        fsl,ccf-num-snoopids = <32>;
 
218
                };
 
219
 
 
220
                iommu@20000 {
 
221
                        compatible = "fsl,pamu-v1.0", "fsl,pamu";
 
222
                        reg = <0x20000 0x4000>;
 
223
                        interrupts = <
 
224
                                24 2 0 0
 
225
                                16 2 1 30>;
 
226
                };
 
227
 
 
228
                mpic: pic@40000 {
 
229
                        clock-frequency = <0>;
 
230
                        interrupt-controller;
 
231
                        #address-cells = <0>;
 
232
                        #interrupt-cells = <4>;
 
233
                        reg = <0x40000 0x40000>;
 
234
                        compatible = "fsl,mpic", "chrp,open-pic";
 
235
                        device_type = "open-pic";
 
236
                };
 
237
 
 
238
                msi0: msi@41600 {
 
239
                        compatible = "fsl,mpic-msi";
 
240
                        reg = <0x41600 0x200>;
 
241
                        msi-available-ranges = <0 0x100>;
 
242
                        interrupts = <
 
243
                                0xe0 0 0 0
 
244
                                0xe1 0 0 0
 
245
                                0xe2 0 0 0
 
246
                                0xe3 0 0 0
 
247
                                0xe4 0 0 0
 
248
                                0xe5 0 0 0
 
249
                                0xe6 0 0 0
 
250
                                0xe7 0 0 0>;
 
251
                };
 
252
 
 
253
                msi1: msi@41800 {
 
254
                        compatible = "fsl,mpic-msi";
 
255
                        reg = <0x41800 0x200>;
 
256
                        msi-available-ranges = <0 0x100>;
 
257
                        interrupts = <
 
258
                                0xe8 0 0 0
 
259
                                0xe9 0 0 0
 
260
                                0xea 0 0 0
 
261
                                0xeb 0 0 0
 
262
                                0xec 0 0 0
 
263
                                0xed 0 0 0
 
264
                                0xee 0 0 0
 
265
                                0xef 0 0 0>;
 
266
                };
 
267
 
 
268
                msi2: msi@41a00 {
 
269
                        compatible = "fsl,mpic-msi";
 
270
                        reg = <0x41a00 0x200>;
 
271
                        msi-available-ranges = <0 0x100>;
 
272
                        interrupts = <
 
273
                                0xf0 0 0 0
 
274
                                0xf1 0 0 0
 
275
                                0xf2 0 0 0
 
276
                                0xf3 0 0 0
 
277
                                0xf4 0 0 0
 
278
                                0xf5 0 0 0
 
279
                                0xf6 0 0 0
 
280
                                0xf7 0 0 0>;
 
281
                };
 
282
 
 
283
                guts: global-utilities@e0000 {
 
284
                        compatible = "fsl,qoriq-device-config-1.0";
 
285
                        reg = <0xe0000 0xe00>;
 
286
                        fsl,has-rstcr;
 
287
                        #sleep-cells = <1>;
 
288
                        fsl,liodn-bits = <12>;
 
289
                };
 
290
 
 
291
                pins: global-utilities@e0e00 {
 
292
                        compatible = "fsl,qoriq-pin-control-1.0";
 
293
                        reg = <0xe0e00 0x200>;
 
294
                        #sleep-cells = <2>;
 
295
                };
 
296
 
 
297
                clockgen: global-utilities@e1000 {
 
298
                        compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
 
299
                        reg = <0xe1000 0x1000>;
 
300
                        clock-frequency = <0>;
 
301
                };
 
302
 
 
303
                rcpm: global-utilities@e2000 {
 
304
                        compatible = "fsl,qoriq-rcpm-1.0";
 
305
                        reg = <0xe2000 0x1000>;
 
306
                        #sleep-cells = <1>;
 
307
                };
 
308
 
 
309
                sfp: sfp@e8000 {
 
310
                        compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
 
311
                        reg        = <0xe8000 0x1000>;
 
312
                };
 
313
 
 
314
                serdes: serdes@ea000 {
 
315
                        compatible = "fsl,p2041-serdes";
 
316
                        reg        = <0xea000 0x1000>;
 
317
                };
 
318
 
 
319
                dma0: dma@100300 {
 
320
                        #address-cells = <1>;
 
321
                        #size-cells = <1>;
 
322
                        compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
 
323
                        reg = <0x100300 0x4>;
 
324
                        ranges = <0x0 0x100100 0x200>;
 
325
                        cell-index = <0>;
 
326
                        dma-channel@0 {
 
327
                                compatible = "fsl,p2041-dma-channel",
 
328
                                                "fsl,eloplus-dma-channel";
 
329
                                reg = <0x0 0x80>;
 
330
                                cell-index = <0>;
 
331
                                interrupts = <28 2 0 0>;
 
332
                        };
 
333
                        dma-channel@80 {
 
334
                                compatible = "fsl,p2041-dma-channel",
 
335
                                                "fsl,eloplus-dma-channel";
 
336
                                reg = <0x80 0x80>;
 
337
                                cell-index = <1>;
 
338
                                interrupts = <29 2 0 0>;
 
339
                        };
 
340
                        dma-channel@100 {
 
341
                                compatible = "fsl,p2041-dma-channel",
 
342
                                                "fsl,eloplus-dma-channel";
 
343
                                reg = <0x100 0x80>;
 
344
                                cell-index = <2>;
 
345
                                interrupts = <30 2 0 0>;
 
346
                        };
 
347
                        dma-channel@180 {
 
348
                                compatible = "fsl,p2041-dma-channel",
 
349
                                                "fsl,eloplus-dma-channel";
 
350
                                reg = <0x180 0x80>;
 
351
                                cell-index = <3>;
 
352
                                interrupts = <31 2 0 0>;
 
353
                        };
 
354
                };
 
355
 
 
356
                dma1: dma@101300 {
 
357
                        #address-cells = <1>;
 
358
                        #size-cells = <1>;
 
359
                        compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
 
360
                        reg = <0x101300 0x4>;
 
361
                        ranges = <0x0 0x101100 0x200>;
 
362
                        cell-index = <1>;
 
363
                        dma-channel@0 {
 
364
                                compatible = "fsl,p2041-dma-channel",
 
365
                                                "fsl,eloplus-dma-channel";
 
366
                                reg = <0x0 0x80>;
 
367
                                cell-index = <0>;
 
368
                                interrupts = <32 2 0 0>;
 
369
                        };
 
370
                        dma-channel@80 {
 
371
                                compatible = "fsl,p2041-dma-channel",
 
372
                                                "fsl,eloplus-dma-channel";
 
373
                                reg = <0x80 0x80>;
 
374
                                cell-index = <1>;
 
375
                                interrupts = <33 2 0 0>;
 
376
                        };
 
377
                        dma-channel@100 {
 
378
                                compatible = "fsl,p2041-dma-channel",
 
379
                                                "fsl,eloplus-dma-channel";
 
380
                                reg = <0x100 0x80>;
 
381
                                cell-index = <2>;
 
382
                                interrupts = <34 2 0 0>;
 
383
                        };
 
384
                        dma-channel@180 {
 
385
                                compatible = "fsl,p2041-dma-channel",
 
386
                                                "fsl,eloplus-dma-channel";
 
387
                                reg = <0x180 0x80>;
 
388
                                cell-index = <3>;
 
389
                                interrupts = <35 2 0 0>;
 
390
                        };
 
391
                };
 
392
 
 
393
                spi@110000 {
 
394
                        #address-cells = <1>;
 
395
                        #size-cells = <0>;
 
396
                        compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
 
397
                        reg = <0x110000 0x1000>;
 
398
                        interrupts = <53 0x2 0 0>;
 
399
                        fsl,espi-num-chipselects = <4>;
 
400
                };
 
401
 
 
402
                sdhc: sdhc@114000 {
 
403
                        compatible = "fsl,p2041-esdhc", "fsl,esdhc";
 
404
                        reg = <0x114000 0x1000>;
 
405
                        interrupts = <48 2 0 0>;
 
406
                        sdhci,auto-cmd12;
 
407
                        clock-frequency = <0>;
 
408
                };
 
409
 
 
410
                i2c@118000 {
 
411
                        #address-cells = <1>;
 
412
                        #size-cells = <0>;
 
413
                        cell-index = <0>;
 
414
                        compatible = "fsl-i2c";
 
415
                        reg = <0x118000 0x100>;
 
416
                        interrupts = <38 2 0 0>;
 
417
                        dfsrr;
 
418
                };
 
419
 
 
420
                i2c@118100 {
 
421
                        #address-cells = <1>;
 
422
                        #size-cells = <0>;
 
423
                        cell-index = <1>;
 
424
                        compatible = "fsl-i2c";
 
425
                        reg = <0x118100 0x100>;
 
426
                        interrupts = <38 2 0 0>;
 
427
                        dfsrr;
 
428
                };
 
429
 
 
430
                i2c@119000 {
 
431
                        #address-cells = <1>;
 
432
                        #size-cells = <0>;
 
433
                        cell-index = <2>;
 
434
                        compatible = "fsl-i2c";
 
435
                        reg = <0x119000 0x100>;
 
436
                        interrupts = <39 2 0 0>;
 
437
                        dfsrr;
 
438
                };
 
439
 
 
440
                i2c@119100 {
 
441
                        #address-cells = <1>;
 
442
                        #size-cells = <0>;
 
443
                        cell-index = <3>;
 
444
                        compatible = "fsl-i2c";
 
445
                        reg = <0x119100 0x100>;
 
446
                        interrupts = <39 2 0 0>;
 
447
                        dfsrr;
 
448
                };
 
449
 
 
450
                serial0: serial@11c500 {
 
451
                        cell-index = <0>;
 
452
                        device_type = "serial";
 
453
                        compatible = "ns16550";
 
454
                        reg = <0x11c500 0x100>;
 
455
                        clock-frequency = <0>;
 
456
                        interrupts = <36 2 0 0>;
 
457
                };
 
458
 
 
459
                serial1: serial@11c600 {
 
460
                        cell-index = <1>;
 
461
                        device_type = "serial";
 
462
                        compatible = "ns16550";
 
463
                        reg = <0x11c600 0x100>;
 
464
                        clock-frequency = <0>;
 
465
                        interrupts = <36 2 0 0>;
 
466
                };
 
467
 
 
468
                serial2: serial@11d500 {
 
469
                        cell-index = <2>;
 
470
                        device_type = "serial";
 
471
                        compatible = "ns16550";
 
472
                        reg = <0x11d500 0x100>;
 
473
                        clock-frequency = <0>;
 
474
                        interrupts = <37 2 0 0>;
 
475
                };
 
476
 
 
477
                serial3: serial@11d600 {
 
478
                        cell-index = <3>;
 
479
                        device_type = "serial";
 
480
                        compatible = "ns16550";
 
481
                        reg = <0x11d600 0x100>;
 
482
                        clock-frequency = <0>;
 
483
                        interrupts = <37 2 0 0>;
 
484
                };
 
485
 
 
486
                gpio0: gpio@130000 {
 
487
                        compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
 
488
                        reg = <0x130000 0x1000>;
 
489
                        interrupts = <55 2 0 0>;
 
490
                        #gpio-cells = <2>;
 
491
                        gpio-controller;
 
492
                };
 
493
 
 
494
                usb0: usb@210000 {
 
495
                        compatible = "fsl,p2041-usb2-mph",
 
496
                                        "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 
497
                        reg = <0x210000 0x1000>;
 
498
                        #address-cells = <1>;
 
499
                        #size-cells = <0>;
 
500
                        interrupts = <44 0x2 0 0>;
 
501
                        phy_type = "utmi";
 
502
                        port0;
 
503
                };
 
504
 
 
505
                usb1: usb@211000 {
 
506
                        compatible = "fsl,p2041-usb2-dr",
 
507
                                        "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 
508
                        reg = <0x211000 0x1000>;
 
509
                        #address-cells = <1>;
 
510
                        #size-cells = <0>;
 
511
                        interrupts = <45 0x2 0 0>;
 
512
                        phy_type = "utmi";
 
513
                };
 
514
 
 
515
                sata@220000 {
 
516
                        compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
 
517
                        reg = <0x220000 0x1000>;
 
518
                        interrupts = <68 0x2 0 0>;
 
519
                };
 
520
 
 
521
                sata@221000 {
 
522
                        compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
 
523
                        reg = <0x221000 0x1000>;
 
524
                        interrupts = <69 0x2 0 0>;
 
525
                };
 
526
 
 
527
                crypto: crypto@300000 {
 
528
                        compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
 
529
                        #address-cells = <1>;
 
530
                        #size-cells = <1>;
 
531
                        reg = <0x300000 0x10000>;
 
532
                        ranges = <0 0x300000 0x10000>;
 
533
                        interrupts = <92 2 0 0>;
 
534
 
 
535
                        sec_jr0: jr@1000 {
 
536
                                compatible = "fsl,sec-v4.2-job-ring",
 
537
                                             "fsl,sec-v4.0-job-ring";
 
538
                                reg = <0x1000 0x1000>;
 
539
                                interrupts = <88 2 0 0>;
 
540
                        };
 
541
 
 
542
                        sec_jr1: jr@2000 {
 
543
                                compatible = "fsl,sec-v4.2-job-ring",
 
544
                                             "fsl,sec-v4.0-job-ring";
 
545
                                reg = <0x2000 0x1000>;
 
546
                                interrupts = <89 2 0 0>;
 
547
                        };
 
548
 
 
549
                        sec_jr2: jr@3000 {
 
550
                                compatible = "fsl,sec-v4.2-job-ring",
 
551
                                             "fsl,sec-v4.0-job-ring";
 
552
                                reg = <0x3000 0x1000>;
 
553
                                interrupts = <90 2 0 0>;
 
554
                        };
 
555
 
 
556
                        sec_jr3: jr@4000 {
 
557
                                compatible = "fsl,sec-v4.2-job-ring",
 
558
                                             "fsl,sec-v4.0-job-ring";
 
559
                                reg = <0x4000 0x1000>;
 
560
                                interrupts = <91 2 0 0>;
 
561
                        };
 
562
 
 
563
                        rtic@6000 {
 
564
                                compatible = "fsl,sec-v4.2-rtic",
 
565
                                             "fsl,sec-v4.0-rtic";
 
566
                                #address-cells = <1>;
 
567
                                #size-cells = <1>;
 
568
                                reg = <0x6000 0x100>;
 
569
                                ranges = <0x0 0x6100 0xe00>;
 
570
 
 
571
                                rtic_a: rtic-a@0 {
 
572
                                        compatible = "fsl,sec-v4.2-rtic-memory",
 
573
                                                     "fsl,sec-v4.0-rtic-memory";
 
574
                                        reg = <0x00 0x20 0x100 0x80>;
 
575
                                };
 
576
 
 
577
                                rtic_b: rtic-b@20 {
 
578
                                        compatible = "fsl,sec-v4.2-rtic-memory",
 
579
                                                     "fsl,sec-v4.0-rtic-memory";
 
580
                                        reg = <0x20 0x20 0x200 0x80>;
 
581
                                };
 
582
 
 
583
                                rtic_c: rtic-c@40 {
 
584
                                        compatible = "fsl,sec-v4.2-rtic-memory",
 
585
                                                     "fsl,sec-v4.0-rtic-memory";
 
586
                                        reg = <0x40 0x20 0x300 0x80>;
 
587
                                };
 
588
 
 
589
                                rtic_d: rtic-d@60 {
 
590
                                        compatible = "fsl,sec-v4.2-rtic-memory",
 
591
                                                     "fsl,sec-v4.0-rtic-memory";
 
592
                                        reg = <0x60 0x20 0x500 0x80>;
 
593
                                };
 
594
                        };
 
595
                };
 
596
 
 
597
                sec_mon: sec_mon@314000 {
 
598
                        compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
 
599
                        reg = <0x314000 0x1000>;
 
600
                        interrupts = <93 2 0 0>;
 
601
                };
 
602
 
 
603
        };
 
604
 
 
605
        localbus@ffe124000 {
 
606
                compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
 
607
                interrupts = <25 2 0 0>;
 
608
                #address-cells = <2>;
 
609
                #size-cells = <1>;
 
610
        };
 
611
 
 
612
        pci0: pcie@ffe200000 {
 
613
                compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
 
614
                device_type = "pci";
 
615
                #size-cells = <2>;
 
616
                #address-cells = <3>;
 
617
                bus-range = <0x0 0xff>;
 
618
                clock-frequency = <33333333>;
 
619
                fsl,msi = <&msi0>;
 
620
                interrupts = <16 2 1 15>;
 
621
                pcie@0 {
 
622
                        reg = <0 0 0 0 0>;
 
623
                        #interrupt-cells = <1>;
 
624
                        #size-cells = <2>;
 
625
                        #address-cells = <3>;
 
626
                        device_type = "pci";
 
627
                        interrupts = <16 2 1 15>;
 
628
                        interrupt-map-mask = <0xf800 0 0 7>;
 
629
                        interrupt-map = <
 
630
                                /* IDSEL 0x0 */
 
631
                                0000 0 0 1 &mpic 40 1 0 0
 
632
                                0000 0 0 2 &mpic 1 1 0 0
 
633
                                0000 0 0 3 &mpic 2 1 0 0
 
634
                                0000 0 0 4 &mpic 3 1 0 0
 
635
                                >;
 
636
                };
 
637
        };
 
638
 
 
639
        pci1: pcie@ffe201000 {
 
640
                compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
 
641
                device_type = "pci";
 
642
                #size-cells = <2>;
 
643
                #address-cells = <3>;
 
644
                bus-range = <0 0xff>;
 
645
                clock-frequency = <33333333>;
 
646
                fsl,msi = <&msi1>;
 
647
                interrupts = <16 2 1 14>;
 
648
                pcie@0 {
 
649
                        reg = <0 0 0 0 0>;
 
650
                        #interrupt-cells = <1>;
 
651
                        #size-cells = <2>;
 
652
                        #address-cells = <3>;
 
653
                        device_type = "pci";
 
654
                        interrupts = <16 2 1 14>;
 
655
                        interrupt-map-mask = <0xf800 0 0 7>;
 
656
                        interrupt-map = <
 
657
                                /* IDSEL 0x0 */
 
658
                                0000 0 0 1 &mpic 41 1 0 0
 
659
                                0000 0 0 2 &mpic 5 1 0 0
 
660
                                0000 0 0 3 &mpic 6 1 0 0
 
661
                                0000 0 0 4 &mpic 7 1 0 0
 
662
                                >;
 
663
                };
 
664
        };
 
665
 
 
666
        pci2: pcie@ffe202000 {
 
667
                compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
 
668
                device_type = "pci";
 
669
                #size-cells = <2>;
 
670
                #address-cells = <3>;
 
671
                bus-range = <0x0 0xff>;
 
672
                clock-frequency = <33333333>;
 
673
                fsl,msi = <&msi2>;
 
674
                interrupts = <16 2 1 13>;
 
675
                pcie@0 {
 
676
                        reg = <0 0 0 0 0>;
 
677
                        #interrupt-cells = <1>;
 
678
                        #size-cells = <2>;
 
679
                        #address-cells = <3>;
 
680
                        device_type = "pci";
 
681
                        interrupts = <16 2 1 13>;
 
682
                        interrupt-map-mask = <0xf800 0 0 7>;
 
683
                        interrupt-map = <
 
684
                                /* IDSEL 0x0 */
 
685
                                0000 0 0 1 &mpic 42 1 0 0
 
686
                                0000 0 0 2 &mpic 9 1 0 0
 
687
                                0000 0 0 3 &mpic 10 1 0 0
 
688
                                0000 0 0 4 &mpic 11 1 0 0
 
689
                                >;
 
690
                };
 
691
        };
 
692
};