2
* drivers/net/phy/marvell.c
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* Driver for Marvell PHYs
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* Copyright (c) 2004 Freescale Semiconductor, Inc.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/marvell_phy.h>
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#include <asm/uaccess.h>
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#define MII_MARVELL_PHY_PAGE 22
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#define MII_M1011_IEVENT 0x13
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#define MII_M1011_IEVENT_CLEAR 0x0000
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#define MII_M1011_IMASK 0x12
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#define MII_M1011_IMASK_INIT 0x6400
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#define MII_M1011_IMASK_CLEAR 0x0000
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#define MII_M1011_PHY_SCR 0x10
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#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
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#define MII_M1145_PHY_EXT_CR 0x14
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#define MII_M1145_RGMII_RX_DELAY 0x0080
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#define MII_M1145_RGMII_TX_DELAY 0x0002
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#define MII_M1111_PHY_LED_CONTROL 0x18
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#define MII_M1111_PHY_LED_DIRECT 0x4100
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#define MII_M1111_PHY_LED_COMBINE 0x411c
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#define MII_M1111_PHY_EXT_CR 0x14
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#define MII_M1111_RX_DELAY 0x80
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#define MII_M1111_TX_DELAY 0x2
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#define MII_M1111_PHY_EXT_SR 0x1b
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#define MII_M1111_HWCFG_MODE_MASK 0xf
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#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
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#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
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#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
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#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
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#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
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#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
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#define MII_M1111_COPPER 0
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#define MII_M1111_FIBER 1
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#define MII_88E1121_PHY_MSCR_PAGE 2
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#define MII_88E1121_PHY_MSCR_REG 21
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#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
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#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
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#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
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#define MII_88E1318S_PHY_MSCR1_REG 16
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#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
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#define MII_88E1121_PHY_LED_CTRL 16
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#define MII_88E1121_PHY_LED_PAGE 3
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#define MII_88E1121_PHY_LED_DEF 0x0030
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#define MII_M1011_PHY_STATUS 0x11
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#define MII_M1011_PHY_STATUS_1000 0x8000
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#define MII_M1011_PHY_STATUS_100 0x4000
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#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
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#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
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#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
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#define MII_M1011_PHY_STATUS_LINK 0x0400
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MODULE_DESCRIPTION("Marvell PHY driver");
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MODULE_AUTHOR("Andy Fleming");
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MODULE_LICENSE("GPL");
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static int marvell_ack_interrupt(struct phy_device *phydev)
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/* Clear the interrupts by reading the reg */
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err = phy_read(phydev, MII_M1011_IEVENT);
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static int marvell_config_intr(struct phy_device *phydev)
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
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err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
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static int marvell_config_aneg(struct phy_device *phydev)
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/* The Marvell PHY has an errata which requires
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* that certain registers get written in order
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* to restart autonegotiation */
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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err = phy_write(phydev, 0x1d, 0x1f);
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err = phy_write(phydev, 0x1e, 0x200c);
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err = phy_write(phydev, 0x1d, 0x5);
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err = phy_write(phydev, 0x1e, 0);
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err = phy_write(phydev, 0x1e, 0x100);
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err = phy_write(phydev, MII_M1011_PHY_SCR,
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MII_M1011_PHY_SCR_AUTO_CROSS);
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err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
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MII_M1111_PHY_LED_DIRECT);
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err = genphy_config_aneg(phydev);
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if (phydev->autoneg != AUTONEG_ENABLE) {
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* A write to speed/duplex bits (that is performed by
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* genphy_config_aneg() call above) must be followed by
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* a software reset. Otherwise, the write has no effect.
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bmcr = phy_read(phydev, MII_BMCR);
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err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
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#ifdef CONFIG_OF_MDIO
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* Set and/or override some configuration registers based on the
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* marvell,reg-init property stored in the of_node for the phydev.
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* marvell,reg-init = <reg-page reg mask value>,...;
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* There may be one or more sets of <reg-page reg mask value>:
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* reg-page: which register bank to use.
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* mask: if non-zero, ANDed with existing register value.
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* value: ORed with the masked value and written to the regiser.
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static int marvell_of_reg_init(struct phy_device *phydev)
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int len, i, saved_page, current_page, page_changed, ret;
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if (!phydev->dev.of_node)
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paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
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if (!paddr || len < (4 * sizeof(*paddr)))
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saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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current_page = saved_page;
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len /= sizeof(*paddr);
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for (i = 0; i < len - 3; i += 4) {
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u16 reg_page = be32_to_cpup(paddr + i);
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u16 reg = be32_to_cpup(paddr + i + 1);
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u16 mask = be32_to_cpup(paddr + i + 2);
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u16 val_bits = be32_to_cpup(paddr + i + 3);
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if (reg_page != current_page) {
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current_page = reg_page;
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ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
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val = phy_read(phydev, reg);
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ret = phy_write(phydev, reg, val);
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i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
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static int marvell_of_reg_init(struct phy_device *phydev)
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#endif /* CONFIG_OF_MDIO */
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static int m88e1121_config_aneg(struct phy_device *phydev)
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int err, oldpage, mscr;
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oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
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MII_88E1121_PHY_MSCR_PAGE);
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
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mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
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MII_88E1121_PHY_MSCR_DELAY_MASK;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
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MII_88E1121_PHY_MSCR_TX_DELAY);
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
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err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
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phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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err = phy_write(phydev, MII_M1011_PHY_SCR,
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MII_M1011_PHY_SCR_AUTO_CROSS);
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oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
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phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
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phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
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err = genphy_config_aneg(phydev);
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static int m88e1318_config_aneg(struct phy_device *phydev)
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int err, oldpage, mscr;
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oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
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MII_88E1121_PHY_MSCR_PAGE);
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mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
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mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
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err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
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return m88e1121_config_aneg(phydev);
351
static int m88e1111_config_init(struct phy_device *phydev)
356
/* Enable Fiber/Copper auto selection */
357
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
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temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
359
phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
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temp = phy_read(phydev, MII_BMCR);
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phy_write(phydev, MII_BMCR, temp);
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
370
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
376
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
377
temp &= ~MII_M1111_TX_DELAY;
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temp |= MII_M1111_RX_DELAY;
379
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
380
temp &= ~MII_M1111_RX_DELAY;
381
temp |= MII_M1111_TX_DELAY;
384
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
388
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
392
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
394
if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
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temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
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temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
399
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
404
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
405
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
409
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
410
temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
411
temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
413
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
418
if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
419
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
422
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
423
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
427
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
430
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
431
temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
432
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
437
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
441
temp = phy_read(phydev, MII_BMCR);
442
while (temp & BMCR_RESET);
444
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
447
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
448
temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
449
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
454
err = marvell_of_reg_init(phydev);
458
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
465
static int m88e1118_config_aneg(struct phy_device *phydev)
469
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
473
err = phy_write(phydev, MII_M1011_PHY_SCR,
474
MII_M1011_PHY_SCR_AUTO_CROSS);
478
err = genphy_config_aneg(phydev);
482
static int m88e1118_config_init(struct phy_device *phydev)
487
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
491
/* Enable 1000 Mbit */
492
err = phy_write(phydev, 0x15, 0x1070);
497
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
501
/* Adjust LED Control */
502
if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
503
err = phy_write(phydev, 0x10, 0x1100);
505
err = phy_write(phydev, 0x10, 0x021e);
509
err = marvell_of_reg_init(phydev);
514
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
518
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
525
static int m88e1149_config_init(struct phy_device *phydev)
530
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
534
/* Enable 1000 Mbit */
535
err = phy_write(phydev, 0x15, 0x1048);
539
err = marvell_of_reg_init(phydev);
544
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
548
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
555
static int m88e1145_config_init(struct phy_device *phydev)
559
/* Take care of errata E0 & E1 */
560
err = phy_write(phydev, 0x1d, 0x001b);
564
err = phy_write(phydev, 0x1e, 0x418f);
568
err = phy_write(phydev, 0x1d, 0x0016);
572
err = phy_write(phydev, 0x1e, 0xa2da);
576
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
577
int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
581
temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
583
err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
587
if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
588
err = phy_write(phydev, 0x1d, 0x0012);
592
temp = phy_read(phydev, 0x1e);
597
temp |= 2 << 9; /* 36 ohm */
598
temp |= 2 << 6; /* 39 ohm */
600
err = phy_write(phydev, 0x1e, temp);
604
err = phy_write(phydev, 0x1d, 0x3);
608
err = phy_write(phydev, 0x1e, 0x8000);
614
err = marvell_of_reg_init(phydev);
621
/* marvell_read_status
623
* Generic status code does not detect Fiber correctly!
625
* Check the link, then figure out the current state
626
* by comparing what we advertise with what the link partner
627
* advertises. Start by checking the gigabit possibilities,
628
* then move on to 10/100.
630
static int marvell_read_status(struct phy_device *phydev)
637
/* Update the link, but return if there
639
err = genphy_update_link(phydev);
643
if (AUTONEG_ENABLE == phydev->autoneg) {
644
status = phy_read(phydev, MII_M1011_PHY_STATUS);
648
lpa = phy_read(phydev, MII_LPA);
652
adv = phy_read(phydev, MII_ADVERTISE);
658
if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
659
phydev->duplex = DUPLEX_FULL;
661
phydev->duplex = DUPLEX_HALF;
663
status = status & MII_M1011_PHY_STATUS_SPD_MASK;
664
phydev->pause = phydev->asym_pause = 0;
667
case MII_M1011_PHY_STATUS_1000:
668
phydev->speed = SPEED_1000;
671
case MII_M1011_PHY_STATUS_100:
672
phydev->speed = SPEED_100;
676
phydev->speed = SPEED_10;
680
if (phydev->duplex == DUPLEX_FULL) {
681
phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
682
phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
685
int bmcr = phy_read(phydev, MII_BMCR);
690
if (bmcr & BMCR_FULLDPLX)
691
phydev->duplex = DUPLEX_FULL;
693
phydev->duplex = DUPLEX_HALF;
695
if (bmcr & BMCR_SPEED1000)
696
phydev->speed = SPEED_1000;
697
else if (bmcr & BMCR_SPEED100)
698
phydev->speed = SPEED_100;
700
phydev->speed = SPEED_10;
702
phydev->pause = phydev->asym_pause = 0;
708
static int m88e1121_did_interrupt(struct phy_device *phydev)
712
imask = phy_read(phydev, MII_M1011_IEVENT);
714
if (imask & MII_M1011_IMASK_INIT)
720
static struct phy_driver marvell_drivers[] = {
722
.phy_id = MARVELL_PHY_ID_88E1101,
723
.phy_id_mask = MARVELL_PHY_ID_MASK,
724
.name = "Marvell 88E1101",
725
.features = PHY_GBIT_FEATURES,
726
.flags = PHY_HAS_INTERRUPT,
727
.config_aneg = &marvell_config_aneg,
728
.read_status = &genphy_read_status,
729
.ack_interrupt = &marvell_ack_interrupt,
730
.config_intr = &marvell_config_intr,
731
.driver = { .owner = THIS_MODULE },
734
.phy_id = MARVELL_PHY_ID_88E1112,
735
.phy_id_mask = MARVELL_PHY_ID_MASK,
736
.name = "Marvell 88E1112",
737
.features = PHY_GBIT_FEATURES,
738
.flags = PHY_HAS_INTERRUPT,
739
.config_init = &m88e1111_config_init,
740
.config_aneg = &marvell_config_aneg,
741
.read_status = &genphy_read_status,
742
.ack_interrupt = &marvell_ack_interrupt,
743
.config_intr = &marvell_config_intr,
744
.driver = { .owner = THIS_MODULE },
747
.phy_id = MARVELL_PHY_ID_88E1111,
748
.phy_id_mask = MARVELL_PHY_ID_MASK,
749
.name = "Marvell 88E1111",
750
.features = PHY_GBIT_FEATURES,
751
.flags = PHY_HAS_INTERRUPT,
752
.config_init = &m88e1111_config_init,
753
.config_aneg = &marvell_config_aneg,
754
.read_status = &marvell_read_status,
755
.ack_interrupt = &marvell_ack_interrupt,
756
.config_intr = &marvell_config_intr,
757
.driver = { .owner = THIS_MODULE },
760
.phy_id = MARVELL_PHY_ID_88E1118,
761
.phy_id_mask = MARVELL_PHY_ID_MASK,
762
.name = "Marvell 88E1118",
763
.features = PHY_GBIT_FEATURES,
764
.flags = PHY_HAS_INTERRUPT,
765
.config_init = &m88e1118_config_init,
766
.config_aneg = &m88e1118_config_aneg,
767
.read_status = &genphy_read_status,
768
.ack_interrupt = &marvell_ack_interrupt,
769
.config_intr = &marvell_config_intr,
770
.driver = {.owner = THIS_MODULE,},
773
.phy_id = MARVELL_PHY_ID_88E1121R,
774
.phy_id_mask = MARVELL_PHY_ID_MASK,
775
.name = "Marvell 88E1121R",
776
.features = PHY_GBIT_FEATURES,
777
.flags = PHY_HAS_INTERRUPT,
778
.config_aneg = &m88e1121_config_aneg,
779
.read_status = &marvell_read_status,
780
.ack_interrupt = &marvell_ack_interrupt,
781
.config_intr = &marvell_config_intr,
782
.did_interrupt = &m88e1121_did_interrupt,
783
.driver = { .owner = THIS_MODULE },
786
.phy_id = MARVELL_PHY_ID_88E1318S,
787
.phy_id_mask = MARVELL_PHY_ID_MASK,
788
.name = "Marvell 88E1318S",
789
.features = PHY_GBIT_FEATURES,
790
.flags = PHY_HAS_INTERRUPT,
791
.config_aneg = &m88e1318_config_aneg,
792
.read_status = &marvell_read_status,
793
.ack_interrupt = &marvell_ack_interrupt,
794
.config_intr = &marvell_config_intr,
795
.did_interrupt = &m88e1121_did_interrupt,
796
.driver = { .owner = THIS_MODULE },
799
.phy_id = MARVELL_PHY_ID_88E1145,
800
.phy_id_mask = MARVELL_PHY_ID_MASK,
801
.name = "Marvell 88E1145",
802
.features = PHY_GBIT_FEATURES,
803
.flags = PHY_HAS_INTERRUPT,
804
.config_init = &m88e1145_config_init,
805
.config_aneg = &marvell_config_aneg,
806
.read_status = &genphy_read_status,
807
.ack_interrupt = &marvell_ack_interrupt,
808
.config_intr = &marvell_config_intr,
809
.driver = { .owner = THIS_MODULE },
812
.phy_id = MARVELL_PHY_ID_88E1149R,
813
.phy_id_mask = MARVELL_PHY_ID_MASK,
814
.name = "Marvell 88E1149R",
815
.features = PHY_GBIT_FEATURES,
816
.flags = PHY_HAS_INTERRUPT,
817
.config_init = &m88e1149_config_init,
818
.config_aneg = &m88e1118_config_aneg,
819
.read_status = &genphy_read_status,
820
.ack_interrupt = &marvell_ack_interrupt,
821
.config_intr = &marvell_config_intr,
822
.driver = { .owner = THIS_MODULE },
825
.phy_id = MARVELL_PHY_ID_88E1240,
826
.phy_id_mask = MARVELL_PHY_ID_MASK,
827
.name = "Marvell 88E1240",
828
.features = PHY_GBIT_FEATURES,
829
.flags = PHY_HAS_INTERRUPT,
830
.config_init = &m88e1111_config_init,
831
.config_aneg = &marvell_config_aneg,
832
.read_status = &genphy_read_status,
833
.ack_interrupt = &marvell_ack_interrupt,
834
.config_intr = &marvell_config_intr,
835
.driver = { .owner = THIS_MODULE },
839
static int __init marvell_init(void)
844
for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
845
ret = phy_driver_register(&marvell_drivers[i]);
849
phy_driver_unregister(&marvell_drivers[i]);
857
static void __exit marvell_exit(void)
861
for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
862
phy_driver_unregister(&marvell_drivers[i]);
865
module_init(marvell_init);
866
module_exit(marvell_exit);
868
static struct mdio_device_id __maybe_unused marvell_tbl[] = {
869
{ 0x01410c60, 0xfffffff0 },
870
{ 0x01410c90, 0xfffffff0 },
871
{ 0x01410cc0, 0xfffffff0 },
872
{ 0x01410e10, 0xfffffff0 },
873
{ 0x01410cb0, 0xfffffff0 },
874
{ 0x01410cd0, 0xfffffff0 },
875
{ 0x01410e50, 0xfffffff0 },
876
{ 0x01410e30, 0xfffffff0 },
877
{ 0x01410e90, 0xfffffff0 },
881
MODULE_DEVICE_TABLE(mdio, marvell_tbl);