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* Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
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* Copyright: 2011 Raumfeld GmbH
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* Author: Johannes Stezenbach <js@sig21.net>
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* Wolfson Microelectronics PLC.
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* Mark Brown <broonie@opensource.wolfsonmicro.com>
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* Freescale Semiconductor, Inc.
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* Timur Tabi <timur@freescale.com>
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
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SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | \
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SNDRV_PCM_RATE_88200 | \
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SNDRV_PCM_RATE_96000 | \
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SNDRV_PCM_RATE_176400 | \
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SNDRV_PCM_RATE_192000)
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#define STA32X_FORMATS \
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(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
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SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
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SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
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SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
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SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
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SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)
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/* Power-up register defaults */
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static const u8 sta32x_regs[STA32X_REGISTER_COUNT] = {
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0x63, 0x80, 0xc2, 0x40, 0xc2, 0x5c, 0x10, 0xff, 0x60, 0x60,
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0x60, 0x80, 0x00, 0x00, 0x00, 0x40, 0x80, 0x77, 0x6a, 0x69,
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0x6a, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d,
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0xc0, 0xf3, 0x33, 0x00, 0x0c,
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/* regulator power supply names */
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static const char *sta32x_supply_names[] = {
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"Vdda", /* analog supply, 3.3VV */
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"Vdd3", /* digital supply, 3.3V */
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"Vcc" /* power amp spply, 10V - 36V */
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/* codec private data */
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struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
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struct snd_soc_codec *codec;
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u32 coef_shadow[STA32X_COEF_COUNT];
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static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
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static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
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static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
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static const char *sta32x_drc_ac[] = {
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"Anti-Clipping", "Dynamic Range Compression" };
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static const char *sta32x_auto_eq_mode[] = {
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"User", "Preset", "Loudness" };
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static const char *sta32x_auto_gc_mode[] = {
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"User", "AC no clipping", "AC limited clipping (10%)",
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"DRC nighttime listening mode" };
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static const char *sta32x_auto_xo_mode[] = {
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"User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
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"220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
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static const char *sta32x_preset_eq_mode[] = {
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"Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
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"Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
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"Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
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"Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
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"Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
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"Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
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static const char *sta32x_limiter_select[] = {
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"Limiter Disabled", "Limiter #1", "Limiter #2" };
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static const char *sta32x_limiter_attack_rate[] = {
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"3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
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"0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
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"0.0645", "0.0564", "0.0501", "0.0451" };
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static const char *sta32x_limiter_release_rate[] = {
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"0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
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"0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
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"0.0134", "0.0117", "0.0110", "0.0104" };
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static const unsigned int sta32x_limiter_ac_attack_tlv[] = {
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TLV_DB_RANGE_HEAD(2),
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0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
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8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
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static const unsigned int sta32x_limiter_ac_release_tlv[] = {
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TLV_DB_RANGE_HEAD(5),
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0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
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1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
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2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
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3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
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8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
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static const unsigned int sta32x_limiter_drc_attack_tlv[] = {
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TLV_DB_RANGE_HEAD(3),
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0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
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8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
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14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
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static const unsigned int sta32x_limiter_drc_release_tlv[] = {
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TLV_DB_RANGE_HEAD(5),
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0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
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1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
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3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
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5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
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13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
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static const struct soc_enum sta32x_drc_ac_enum =
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SOC_ENUM_SINGLE(STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
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static const struct soc_enum sta32x_auto_eq_enum =
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SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
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3, sta32x_auto_eq_mode);
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static const struct soc_enum sta32x_auto_gc_enum =
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SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
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4, sta32x_auto_gc_mode);
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static const struct soc_enum sta32x_auto_xo_enum =
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SOC_ENUM_SINGLE(STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
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16, sta32x_auto_xo_mode);
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static const struct soc_enum sta32x_preset_eq_enum =
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SOC_ENUM_SINGLE(STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
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32, sta32x_preset_eq_mode);
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static const struct soc_enum sta32x_limiter_ch1_enum =
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SOC_ENUM_SINGLE(STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
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3, sta32x_limiter_select);
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static const struct soc_enum sta32x_limiter_ch2_enum =
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SOC_ENUM_SINGLE(STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
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3, sta32x_limiter_select);
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static const struct soc_enum sta32x_limiter_ch3_enum =
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SOC_ENUM_SINGLE(STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
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3, sta32x_limiter_select);
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static const struct soc_enum sta32x_limiter1_attack_rate_enum =
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SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxA_SHIFT,
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16, sta32x_limiter_attack_rate);
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static const struct soc_enum sta32x_limiter2_attack_rate_enum =
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SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxA_SHIFT,
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16, sta32x_limiter_attack_rate);
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static const struct soc_enum sta32x_limiter1_release_rate_enum =
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SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxR_SHIFT,
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16, sta32x_limiter_release_rate);
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static const struct soc_enum sta32x_limiter2_release_rate_enum =
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SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxR_SHIFT,
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16, sta32x_limiter_release_rate);
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/* byte array controls for setting biquad, mixer, scaling coefficients;
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* for biquads all five coefficients need to be set in one go,
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* mixer and pre/postscale coefs can be set individually;
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* each coef is 24bit, the bytes are ordered in the same way
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* as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
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static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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int numcoef = kcontrol->private_value >> 16;
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uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
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uinfo->count = 3 * numcoef;
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static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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int numcoef = kcontrol->private_value >> 16;
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int index = kcontrol->private_value & 0xffff;
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/* preserve reserved bits in STA32X_CFUD */
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cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
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/* chip documentation does not say if the bits are self clearing,
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* so do it explicitly */
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snd_soc_write(codec, STA32X_CFUD, cfud);
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snd_soc_write(codec, STA32X_CFADDR2, index);
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x04);
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else if (numcoef == 5)
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x08);
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for (i = 0; i < 3 * numcoef; i++)
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ucontrol->value.bytes.data[i] =
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snd_soc_read(codec, STA32X_B1CF1 + i);
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static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
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int numcoef = kcontrol->private_value >> 16;
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int index = kcontrol->private_value & 0xffff;
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/* preserve reserved bits in STA32X_CFUD */
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cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
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/* chip documentation does not say if the bits are self clearing,
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* so do it explicitly */
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snd_soc_write(codec, STA32X_CFUD, cfud);
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snd_soc_write(codec, STA32X_CFADDR2, index);
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for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
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sta32x->coef_shadow[index + i] =
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(ucontrol->value.bytes.data[3 * i] << 16)
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| (ucontrol->value.bytes.data[3 * i + 1] << 8)
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| (ucontrol->value.bytes.data[3 * i + 2]);
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for (i = 0; i < 3 * numcoef; i++)
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snd_soc_write(codec, STA32X_B1CF1 + i,
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ucontrol->value.bytes.data[i]);
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
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else if (numcoef == 5)
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x02);
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int sta32x_sync_coef_shadow(struct snd_soc_codec *codec)
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struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
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/* preserve reserved bits in STA32X_CFUD */
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cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
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for (i = 0; i < STA32X_COEF_COUNT; i++) {
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snd_soc_write(codec, STA32X_CFADDR2, i);
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snd_soc_write(codec, STA32X_B1CF1,
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(sta32x->coef_shadow[i] >> 16) & 0xff);
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snd_soc_write(codec, STA32X_B1CF2,
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(sta32x->coef_shadow[i] >> 8) & 0xff);
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snd_soc_write(codec, STA32X_B1CF3,
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(sta32x->coef_shadow[i]) & 0xff);
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/* chip documentation does not say if the bits are
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* self-clearing, so do it explicitly */
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snd_soc_write(codec, STA32X_CFUD, cfud);
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
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int sta32x_cache_sync(struct snd_soc_codec *codec)
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if (!codec->cache_sync)
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/* mute during register sync */
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mute = snd_soc_read(codec, STA32X_MMUTE);
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snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
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sta32x_sync_coef_shadow(codec);
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rc = snd_soc_cache_sync(codec);
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snd_soc_write(codec, STA32X_MMUTE, mute);
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#define SINGLE_COEF(xname, index) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = sta32x_coefficient_info, \
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.get = sta32x_coefficient_get,\
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.put = sta32x_coefficient_put, \
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.private_value = index | (1 << 16) }
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#define BIQUAD_COEFS(xname, index) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = sta32x_coefficient_info, \
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.get = sta32x_coefficient_get,\
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.put = sta32x_coefficient_put, \
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.private_value = index | (5 << 16) }
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static const struct snd_kcontrol_new sta32x_snd_controls[] = {
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SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
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SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
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SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
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SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
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SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
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SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
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SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
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SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
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SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
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SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
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SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
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SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
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SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
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SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
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SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
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SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
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SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
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SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
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SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
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SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
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SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
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SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
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SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
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SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
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SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
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SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
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SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
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SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
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SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
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SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
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SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
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SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
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SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
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SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
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/* depending on mode, the attack/release thresholds have
356
* two different enum definitions; provide both
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SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
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16, 0, sta32x_limiter_ac_attack_tlv),
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SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
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16, 0, sta32x_limiter_ac_attack_tlv),
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SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
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16, 0, sta32x_limiter_ac_release_tlv),
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SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
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16, 0, sta32x_limiter_ac_release_tlv),
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SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
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16, 0, sta32x_limiter_drc_attack_tlv),
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SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
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16, 0, sta32x_limiter_drc_attack_tlv),
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SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
371
16, 0, sta32x_limiter_drc_release_tlv),
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SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
373
16, 0, sta32x_limiter_drc_release_tlv),
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BIQUAD_COEFS("Ch1 - Biquad 1", 0),
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BIQUAD_COEFS("Ch1 - Biquad 2", 5),
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BIQUAD_COEFS("Ch1 - Biquad 3", 10),
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BIQUAD_COEFS("Ch1 - Biquad 4", 15),
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BIQUAD_COEFS("Ch2 - Biquad 1", 20),
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BIQUAD_COEFS("Ch2 - Biquad 2", 25),
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BIQUAD_COEFS("Ch2 - Biquad 3", 30),
382
BIQUAD_COEFS("Ch2 - Biquad 4", 35),
383
BIQUAD_COEFS("High-pass", 40),
384
BIQUAD_COEFS("Low-pass", 45),
385
SINGLE_COEF("Ch1 - Prescale", 50),
386
SINGLE_COEF("Ch2 - Prescale", 51),
387
SINGLE_COEF("Ch1 - Postscale", 52),
388
SINGLE_COEF("Ch2 - Postscale", 53),
389
SINGLE_COEF("Ch3 - Postscale", 54),
390
SINGLE_COEF("Thermal warning - Postscale", 55),
391
SINGLE_COEF("Ch1 - Mix 1", 56),
392
SINGLE_COEF("Ch1 - Mix 2", 57),
393
SINGLE_COEF("Ch2 - Mix 1", 58),
394
SINGLE_COEF("Ch2 - Mix 2", 59),
395
SINGLE_COEF("Ch3 - Mix 1", 60),
396
SINGLE_COEF("Ch3 - Mix 2", 61),
399
static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
400
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
401
SND_SOC_DAPM_OUTPUT("LEFT"),
402
SND_SOC_DAPM_OUTPUT("RIGHT"),
403
SND_SOC_DAPM_OUTPUT("SUB"),
406
static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
407
{ "LEFT", NULL, "DAC" },
408
{ "RIGHT", NULL, "DAC" },
409
{ "SUB", NULL, "DAC" },
412
/* MCLK interpolation ratio per fs */
416
} interpolation_ratios[] = {
426
/* MCLK to fs clock ratios */
430
} mclk_ratios[3][7] = {
431
{ { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 },
432
{ 128, 4 }, { 576, 5 }, { 0, 0 } },
433
{ { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
434
{ { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
439
* sta32x_set_dai_sysclk - configure MCLK
440
* @codec_dai: the codec DAI
441
* @clk_id: the clock ID (ignored)
442
* @freq: the MCLK input frequency
443
* @dir: the clock direction (ignored)
445
* The value of MCLK is used to determine which sample rates are supported
446
* by the STA32X, based on the mclk_ratios table.
448
* This function must be called by the machine driver's 'startup' function,
449
* otherwise the list of supported sample rates will not be available in
452
* For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
453
* theoretically possible sample rates to be enabled. Call it again with a
454
* proper value set one the external clock is set (most probably you would do
455
* that from a machine's driver 'hw_param' hook.
457
static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
458
int clk_id, unsigned int freq, int dir)
460
struct snd_soc_codec *codec = codec_dai->codec;
461
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
463
unsigned int rates = 0;
464
unsigned int rate_min = -1;
465
unsigned int rate_max = 0;
467
pr_debug("mclk=%u\n", freq);
471
for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
472
ir = interpolation_ratios[i].ir;
473
fs = interpolation_ratios[i].fs;
474
for (j = 0; mclk_ratios[ir][j].ratio; j++) {
475
if (mclk_ratios[ir][j].ratio * fs == freq) {
476
rates |= snd_pcm_rate_to_rate_bit(fs);
484
/* FIXME: soc should support a rate list */
485
rates &= ~SNDRV_PCM_RATE_KNOT;
488
dev_err(codec->dev, "could not find a valid sample rate\n");
492
/* enable all possible rates */
493
rates = STA32X_RATES;
498
codec_dai->driver->playback.rates = rates;
499
codec_dai->driver->playback.rate_min = rate_min;
500
codec_dai->driver->playback.rate_max = rate_max;
505
* sta32x_set_dai_fmt - configure the codec for the selected audio format
506
* @codec_dai: the codec DAI
507
* @fmt: a SND_SOC_DAIFMT_x value indicating the data format
509
* This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
512
static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
515
struct snd_soc_codec *codec = codec_dai->codec;
516
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
517
u8 confb = snd_soc_read(codec, STA32X_CONFB);
520
confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM);
522
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
523
case SND_SOC_DAIFMT_CBS_CFS:
529
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
530
case SND_SOC_DAIFMT_I2S:
531
case SND_SOC_DAIFMT_RIGHT_J:
532
case SND_SOC_DAIFMT_LEFT_J:
533
sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
539
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
540
case SND_SOC_DAIFMT_NB_NF:
541
confb |= STA32X_CONFB_C2IM;
543
case SND_SOC_DAIFMT_NB_IF:
544
confb |= STA32X_CONFB_C1IM;
550
snd_soc_write(codec, STA32X_CONFB, confb);
555
* sta32x_hw_params - program the STA32X with the given hardware parameters.
556
* @substream: the audio stream
557
* @params: the hardware parameters to set
558
* @dai: the SOC DAI (ignored)
560
* This function programs the hardware with the values provided.
561
* Specifically, the sample rate and the data format.
563
static int sta32x_hw_params(struct snd_pcm_substream *substream,
564
struct snd_pcm_hw_params *params,
565
struct snd_soc_dai *dai)
567
struct snd_soc_pcm_runtime *rtd = substream->private_data;
568
struct snd_soc_codec *codec = rtd->codec;
569
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
571
int i, mcs = -1, ir = -1;
574
rate = params_rate(params);
575
pr_debug("rate: %u\n", rate);
576
for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++)
577
if (interpolation_ratios[i].fs == rate) {
578
ir = interpolation_ratios[i].ir;
583
for (i = 0; mclk_ratios[ir][i].ratio; i++)
584
if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) {
585
mcs = mclk_ratios[ir][i].mcs;
591
confa = snd_soc_read(codec, STA32X_CONFA);
592
confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK);
593
confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT);
595
confb = snd_soc_read(codec, STA32X_CONFB);
596
confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB);
597
switch (params_format(params)) {
598
case SNDRV_PCM_FORMAT_S24_LE:
599
case SNDRV_PCM_FORMAT_S24_BE:
600
case SNDRV_PCM_FORMAT_S24_3LE:
601
case SNDRV_PCM_FORMAT_S24_3BE:
604
case SNDRV_PCM_FORMAT_S32_LE:
605
case SNDRV_PCM_FORMAT_S32_BE:
606
pr_debug("24bit or 32bit\n");
607
switch (sta32x->format) {
608
case SND_SOC_DAIFMT_I2S:
611
case SND_SOC_DAIFMT_LEFT_J:
614
case SND_SOC_DAIFMT_RIGHT_J:
620
case SNDRV_PCM_FORMAT_S20_3LE:
621
case SNDRV_PCM_FORMAT_S20_3BE:
623
switch (sta32x->format) {
624
case SND_SOC_DAIFMT_I2S:
627
case SND_SOC_DAIFMT_LEFT_J:
630
case SND_SOC_DAIFMT_RIGHT_J:
636
case SNDRV_PCM_FORMAT_S18_3LE:
637
case SNDRV_PCM_FORMAT_S18_3BE:
639
switch (sta32x->format) {
640
case SND_SOC_DAIFMT_I2S:
643
case SND_SOC_DAIFMT_LEFT_J:
646
case SND_SOC_DAIFMT_RIGHT_J:
652
case SNDRV_PCM_FORMAT_S16_LE:
653
case SNDRV_PCM_FORMAT_S16_BE:
655
switch (sta32x->format) {
656
case SND_SOC_DAIFMT_I2S:
659
case SND_SOC_DAIFMT_LEFT_J:
662
case SND_SOC_DAIFMT_RIGHT_J:
672
snd_soc_write(codec, STA32X_CONFA, confa);
673
snd_soc_write(codec, STA32X_CONFB, confb);
678
* sta32x_set_bias_level - DAPM callback
679
* @codec: the codec device
680
* @level: DAPM power level
682
* This is called by ALSA to put the codec into low power mode
683
* or to wake it up. If the codec is powered off completely
684
* all registers must be restored after power on.
686
static int sta32x_set_bias_level(struct snd_soc_codec *codec,
687
enum snd_soc_bias_level level)
690
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
692
pr_debug("level = %d\n", level);
694
case SND_SOC_BIAS_ON:
697
case SND_SOC_BIAS_PREPARE:
699
snd_soc_update_bits(codec, STA32X_CONFF,
700
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
701
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
704
case SND_SOC_BIAS_STANDBY:
705
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
706
ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
710
"Failed to enable supplies: %d\n", ret);
714
sta32x_cache_sync(codec);
717
/* Power up to mute */
719
snd_soc_update_bits(codec, STA32X_CONFF,
720
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
721
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
725
case SND_SOC_BIAS_OFF:
726
/* The chip runs through the power down sequence for us. */
727
snd_soc_update_bits(codec, STA32X_CONFF,
728
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
732
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
736
codec->dapm.bias_level = level;
740
static struct snd_soc_dai_ops sta32x_dai_ops = {
741
.hw_params = sta32x_hw_params,
742
.set_sysclk = sta32x_set_dai_sysclk,
743
.set_fmt = sta32x_set_dai_fmt,
746
static struct snd_soc_dai_driver sta32x_dai = {
749
.stream_name = "Playback",
752
.rates = STA32X_RATES,
753
.formats = STA32X_FORMATS,
755
.ops = &sta32x_dai_ops,
759
static int sta32x_suspend(struct snd_soc_codec *codec, pm_message_t state)
761
sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
765
static int sta32x_resume(struct snd_soc_codec *codec)
767
sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
771
#define sta32x_suspend NULL
772
#define sta32x_resume NULL
775
static int sta32x_probe(struct snd_soc_codec *codec)
777
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
780
sta32x->codec = codec;
783
for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
784
sta32x->supplies[i].supply = sta32x_supply_names[i];
786
ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sta32x->supplies),
789
dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
793
ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
796
dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
800
/* Tell ASoC what kind of I/O to use to read the registers. ASoC will
801
* then do the I2C transactions itself.
803
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
805
dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret);
809
/* Chip documentation explicitly requires that the reset values
810
* of reserved register bits are left untouched.
811
* Write the register default value to cache for reserved registers,
812
* so the write to the these registers are suppressed by the cache
813
* restore code when it skips writes of default registers.
815
snd_soc_cache_write(codec, STA32X_CONFC, 0xc2);
816
snd_soc_cache_write(codec, STA32X_CONFE, 0xc2);
817
snd_soc_cache_write(codec, STA32X_CONFF, 0x5c);
818
snd_soc_cache_write(codec, STA32X_MMUTE, 0x10);
819
snd_soc_cache_write(codec, STA32X_AUTO1, 0x60);
820
snd_soc_cache_write(codec, STA32X_AUTO3, 0x00);
821
snd_soc_cache_write(codec, STA32X_C3CFG, 0x40);
823
/* FIXME enable thermal warning adjustment and recovery */
824
snd_soc_update_bits(codec, STA32X_CONFA,
825
STA32X_CONFA_TWAB | STA32X_CONFA_TWRB, 0);
827
/* FIXME select 2.1 mode */
828
snd_soc_update_bits(codec, STA32X_CONFF,
829
STA32X_CONFF_OCFG_MASK,
830
1 << STA32X_CONFF_OCFG_SHIFT);
832
/* FIXME channel to output mapping */
833
snd_soc_update_bits(codec, STA32X_C1CFG,
834
STA32X_CxCFG_OM_MASK,
835
0 << STA32X_CxCFG_OM_SHIFT);
836
snd_soc_update_bits(codec, STA32X_C2CFG,
837
STA32X_CxCFG_OM_MASK,
838
1 << STA32X_CxCFG_OM_SHIFT);
839
snd_soc_update_bits(codec, STA32X_C3CFG,
840
STA32X_CxCFG_OM_MASK,
841
2 << STA32X_CxCFG_OM_SHIFT);
843
/* initialize coefficient shadow RAM with reset values */
844
for (i = 4; i <= 49; i += 5)
845
sta32x->coef_shadow[i] = 0x400000;
846
for (i = 50; i <= 54; i++)
847
sta32x->coef_shadow[i] = 0x7fffff;
848
sta32x->coef_shadow[55] = 0x5a9df7;
849
sta32x->coef_shadow[56] = 0x7fffff;
850
sta32x->coef_shadow[59] = 0x7fffff;
851
sta32x->coef_shadow[60] = 0x400000;
852
sta32x->coef_shadow[61] = 0x400000;
854
sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
855
/* Bias level configuration will have done an extra enable */
856
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
861
regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
866
static int sta32x_remove(struct snd_soc_codec *codec)
868
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
870
sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
871
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
872
regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
877
static int sta32x_reg_is_volatile(struct snd_soc_codec *codec,
881
case STA32X_CONFA ... STA32X_L2ATRT:
882
case STA32X_MPCC1 ... STA32X_FDRC2:
888
static const struct snd_soc_codec_driver sta32x_codec = {
889
.probe = sta32x_probe,
890
.remove = sta32x_remove,
891
.suspend = sta32x_suspend,
892
.resume = sta32x_resume,
893
.reg_cache_size = STA32X_REGISTER_COUNT,
894
.reg_word_size = sizeof(u8),
895
.reg_cache_default = sta32x_regs,
896
.volatile_register = sta32x_reg_is_volatile,
897
.set_bias_level = sta32x_set_bias_level,
898
.controls = sta32x_snd_controls,
899
.num_controls = ARRAY_SIZE(sta32x_snd_controls),
900
.dapm_widgets = sta32x_dapm_widgets,
901
.num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
902
.dapm_routes = sta32x_dapm_routes,
903
.num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
906
static __devinit int sta32x_i2c_probe(struct i2c_client *i2c,
907
const struct i2c_device_id *id)
909
struct sta32x_priv *sta32x;
912
sta32x = kzalloc(sizeof(struct sta32x_priv), GFP_KERNEL);
916
i2c_set_clientdata(i2c, sta32x);
918
ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1);
920
dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
928
static __devexit int sta32x_i2c_remove(struct i2c_client *client)
930
struct sta32x_priv *sta32x = i2c_get_clientdata(client);
932
snd_soc_unregister_codec(&client->dev);
937
static const struct i2c_device_id sta32x_i2c_id[] = {
943
MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
945
static struct i2c_driver sta32x_i2c_driver = {
948
.owner = THIS_MODULE,
950
.probe = sta32x_i2c_probe,
951
.remove = __devexit_p(sta32x_i2c_remove),
952
.id_table = sta32x_i2c_id,
955
static int __init sta32x_init(void)
957
return i2c_add_driver(&sta32x_i2c_driver);
959
module_init(sta32x_init);
961
static void __exit sta32x_exit(void)
963
i2c_del_driver(&sta32x_i2c_driver);
965
module_exit(sta32x_exit);
967
MODULE_DESCRIPTION("ASoC STA32X driver");
968
MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
969
MODULE_LICENSE("GPL");