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* Boot code and exception vectors for Book3E processors
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* Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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#include <linux/threads.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/setup.h>
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#include <asm/thread_info.h>
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#include <asm/reg_a2.h>
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#include <asm/exception-64e.h>
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#include <asm/irqflags.h>
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#include <asm/ptrace.h>
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#include <asm/ppc-opcode.h>
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/* XXX This will ultimately add space for a special exception save
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* structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
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* when taking special interrupts. For now we don't support that,
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* special interrupts from within a non-standard level will probably
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#define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
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/* Exception prolog code for all exceptions */
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#define EXCEPTION_PROLOG(n, type, addition) \
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mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
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mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
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std r10,PACA_EX##type+EX_R10(r13); \
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std r11,PACA_EX##type+EX_R11(r13); \
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mfcr r10; /* save CR */ \
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addition; /* additional code for that exc. */ \
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std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
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stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
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mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
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type##_SET_KSTACK; /* get special stack if necessary */\
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andi. r10,r11,MSR_PR; /* save stack pointer */ \
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beq 1f; /* branch around if supervisor */ \
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ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
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1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
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bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
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mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
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/* Exception type-specific macros */
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#define GEN_SET_KSTACK \
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subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
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#define SPRN_GEN_SRR0 SPRN_SRR0
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#define SPRN_GEN_SRR1 SPRN_SRR1
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#define CRIT_SET_KSTACK \
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ld r1,PACA_CRIT_STACK(r13); \
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subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
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#define SPRN_CRIT_SRR0 SPRN_CSRR0
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#define SPRN_CRIT_SRR1 SPRN_CSRR1
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#define DBG_SET_KSTACK \
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ld r1,PACA_DBG_STACK(r13); \
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subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
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#define SPRN_DBG_SRR0 SPRN_DSRR0
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#define SPRN_DBG_SRR1 SPRN_DSRR1
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#define MC_SET_KSTACK \
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ld r1,PACA_MC_STACK(r13); \
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subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
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#define SPRN_MC_SRR0 SPRN_MCSRR0
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#define SPRN_MC_SRR1 SPRN_MCSRR1
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#define NORMAL_EXCEPTION_PROLOG(n, addition) \
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EXCEPTION_PROLOG(n, GEN, addition##_GEN)
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#define CRIT_EXCEPTION_PROLOG(n, addition) \
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EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
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#define DBG_EXCEPTION_PROLOG(n, addition) \
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EXCEPTION_PROLOG(n, DBG, addition##_DBG)
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#define MC_EXCEPTION_PROLOG(n, addition) \
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EXCEPTION_PROLOG(n, MC, addition##_MC)
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/* Variants of the "addition" argument for the prolog
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#define PROLOG_ADDITION_NONE_GEN
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#define PROLOG_ADDITION_NONE_CRIT
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#define PROLOG_ADDITION_NONE_DBG
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#define PROLOG_ADDITION_NONE_MC
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#define PROLOG_ADDITION_MASKABLE_GEN \
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lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
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cmpwi cr0,r11,0; /* yes -> go out of line */ \
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beq masked_interrupt_book3e;
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#define PROLOG_ADDITION_2REGS_GEN \
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std r14,PACA_EXGEN+EX_R14(r13); \
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std r15,PACA_EXGEN+EX_R15(r13)
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#define PROLOG_ADDITION_1REG_GEN \
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std r14,PACA_EXGEN+EX_R14(r13);
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#define PROLOG_ADDITION_2REGS_CRIT \
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std r14,PACA_EXCRIT+EX_R14(r13); \
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std r15,PACA_EXCRIT+EX_R15(r13)
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#define PROLOG_ADDITION_2REGS_DBG \
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std r14,PACA_EXDBG+EX_R14(r13); \
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std r15,PACA_EXDBG+EX_R15(r13)
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#define PROLOG_ADDITION_2REGS_MC \
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std r14,PACA_EXMC+EX_R14(r13); \
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std r15,PACA_EXMC+EX_R15(r13)
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#define PROLOG_ADDITION_DOORBELL_GEN \
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lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
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cmpwi cr0,r11,0; /* yes -> go out of line */ \
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beq masked_doorbell_book3e
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/* Core exception code for all exceptions except TLB misses.
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* XXX: Needs to make SPRN_SPRG_GEN depend on exception type
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#define EXCEPTION_COMMON(n, excf, ints) \
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std r0,GPR0(r1); /* save r0 in stackframe */ \
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std r2,GPR2(r1); /* save r2 in stackframe */ \
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SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
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SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
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std r9,GPR9(r1); /* save r9 in stackframe */ \
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std r10,_NIP(r1); /* save SRR0 to stackframe */ \
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std r11,_MSR(r1); /* save SRR1 to stackframe */ \
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ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
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ld r3,excf+EX_R10(r13); /* get back r10 */ \
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ld r4,excf+EX_R11(r13); /* get back r11 */ \
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mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
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std r12,GPR12(r1); /* save r12 in stackframe */ \
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ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
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mflr r6; /* save LR in stackframe */ \
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mfctr r7; /* save CTR in stackframe */ \
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mfspr r8,SPRN_XER; /* save XER in stackframe */ \
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ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
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lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
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lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
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ld r12,exception_marker@toc(r2); \
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std r3,GPR10(r1); /* save r10 to stackframe */ \
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std r4,GPR11(r1); /* save r11 to stackframe */ \
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std r5,GPR13(r1); /* save it to stackframe */ \
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li r3,(n)+1; /* indicate partial regs in trap */ \
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std r9,0(r1); /* store stack frame back link */ \
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std r10,_CCR(r1); /* store orig CR in stackframe */ \
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std r9,GPR1(r1); /* store stack frame back link */ \
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std r11,SOFTE(r1); /* and save it to stackframe */ \
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std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
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std r3,_TRAP(r1); /* set trap number */ \
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std r0,RESULT(r1); /* clear regs->result */ \
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/* Variants for the "ints" argument */
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#define INTS_DISABLE_SOFT \
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stb r0,PACASOFTIRQEN(r13); /* mark interrupts soft-disabled */ \
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#define INTS_DISABLE_HARD \
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stb r0,PACAHARDIRQEN(r13); /* and hard disabled */
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#define INTS_DISABLE_ALL \
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/* This is called by exceptions that used INTS_KEEP (that is did not clear
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* neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
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* to it's previous value
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* XXX In the long run, we may want to open-code it in order to separate the
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* load from the wrtee, thus limiting the latency caused by the dependency
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* but at this point, I'll favor code clarity until we have a near to final
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#define INTS_RESTORE_HARD \
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/* XXX FIXME: Restore r14/r15 when necessary */
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#define BAD_STACK_TRAMPOLINE(n) \
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exc_##n##_bad_stack: \
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li r1,(n); /* get exception number */ \
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sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
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b bad_stack_book3e; /* bad stack error */
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/* WARNING: If you change the layout of this stub, make sure you chcek
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* the debug exception handler which handles single stepping
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* into exceptions from userspace, and the MM code in
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* arch/powerpc/mm/tlb_nohash.c which patches the branch here
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* and would need to be updated if that branch is moved
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#define EXCEPTION_STUB(loc, label) \
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. = interrupt_base_book3e + loc; \
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nop; /* To make debug interrupts happy */ \
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b exc_##label##_book3e;
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/* Used by asynchronous interrupt that may happen in the idle loop.
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* This check if the thread was in the idle loop, and if yes, returns
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* to the caller rather than the PC. This is to avoid a race if
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* interrupts happen before the wait instruction.
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#define CHECK_NAPPING() \
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clrrdi r11,r1,THREAD_SHIFT; \
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ld r10,TI_LOCAL_FLAGS(r11); \
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andi. r9,r10,_TLF_NAPPING; \
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rlwinm r7,r10,0,~_TLF_NAPPING; \
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std r7,TI_LOCAL_FLAGS(r11); \
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#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
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START_EXCEPTION(label); \
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NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
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EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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b .ret_from_except_lite;
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/* This value is used to mark exception frames on the stack. */
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.tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
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* And here we have the exception vectors !
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.globl interrupt_base_book3e
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interrupt_base_book3e: /* fake trap */
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EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
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EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
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EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
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EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
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EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
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EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
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EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
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EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
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EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
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EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
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EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
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EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
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EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
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EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
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EXCEPTION_STUB(0x1c0, data_tlb_miss)
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EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
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EXCEPTION_STUB(0x260, perfmon)
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EXCEPTION_STUB(0x280, doorbell)
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EXCEPTION_STUB(0x2a0, doorbell_crit)
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EXCEPTION_STUB(0x2c0, guest_doorbell)
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EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
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EXCEPTION_STUB(0x300, hypercall)
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EXCEPTION_STUB(0x320, ehpriv)
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.globl interrupt_end_book3e
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interrupt_end_book3e:
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/* Critical Input Interrupt */
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START_EXCEPTION(critical_input);
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CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
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// EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
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// bl special_reg_save_crit
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// addi r3,r1,STACK_FRAME_OVERHEAD
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// bl .critical_exception
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// b ret_from_crit_except
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/* Machine Check Interrupt */
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START_EXCEPTION(machine_check);
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CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
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// EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
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// bl special_reg_save_mc
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// addi r3,r1,STACK_FRAME_OVERHEAD
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// bl .machine_check_exception
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// b ret_from_mc_except
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/* Data Storage Interrupt */
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START_EXCEPTION(data_storage)
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NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
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EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
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b storage_fault_common
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/* Instruction Storage Interrupt */
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START_EXCEPTION(instruction_storage);
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NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
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EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
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b storage_fault_common
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/* External Input Interrupt */
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MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
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START_EXCEPTION(alignment);
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NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
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EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
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b alignment_more /* no room, go out of line */
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/* Program Interrupt */
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START_EXCEPTION(program);
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NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
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EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
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addi r3,r1,STACK_FRAME_OVERHEAD
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ld r14,PACA_EXGEN+EX_R14(r13)
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bl .program_check_exception
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/* Floating Point Unavailable Interrupt */
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START_EXCEPTION(fp_unavailable);
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NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
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/* we can probably do a shorter exception entry for that one... */
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EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
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bne 1f /* if from user, just load it up */
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .kernel_fp_unavailable_exception
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b fast_exception_return
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/* Decrementer Interrupt */
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MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
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/* Fixed Interval Timer Interrupt */
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MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
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/* Watchdog Timer Interrupt */
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START_EXCEPTION(watchdog);
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CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
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// EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
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// bl special_reg_save_crit
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// addi r3,r1,STACK_FRAME_OVERHEAD
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// bl .unknown_exception
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// b ret_from_crit_except
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/* System Call Interrupt */
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START_EXCEPTION(system_call)
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mr r9,r13 /* keep a copy of userland r13 */
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mfspr r11,SPRN_SRR0 /* get return address */
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mfspr r12,SPRN_SRR1 /* get previous MSR */
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mfspr r13,SPRN_SPRG_PACA /* get our PACA */
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/* Auxiliary Processor Unavailable Interrupt */
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START_EXCEPTION(ap_unavailable);
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NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
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EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .unknown_exception
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/* Debug exception as a critical interrupt*/
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START_EXCEPTION(debug_crit);
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CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
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* If there is a single step or branch-taken exception in an
407
* exception entry sequence, it was probably meant to apply to
408
* the code where the exception occurred (since exception entry
409
* doesn't turn off DE automatically). We simulate the effect
410
* of turning off DE on entry to an exception handler by turning
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* off DE in the CSRR1 value and clearing the debug status.
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mfspr r14,SPRN_DBSR /* check single-step/branch taken */
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andis. r15,r14,DBSR_IC@h
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LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
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LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
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/* here it looks like we got an inappropriate debug exception. */
426
lis r14,DBSR_IC@h /* clear the IC event */
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rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
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lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
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ld r1,PACA_EXCRIT+EX_R1(r13)
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ld r14,PACA_EXCRIT+EX_R14(r13)
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ld r15,PACA_EXCRIT+EX_R15(r13)
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ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
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ld r11,PACA_EXCRIT+EX_R11(r13)
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mfspr r13,SPRN_SPRG_CRIT_SCRATCH
440
/* Normal debug exception */
441
/* XXX We only handle coming from userspace for now since we can't
442
* quite save properly an interrupted kernel state yet
444
1: andi. r14,r11,MSR_PR; /* check for userspace again */
445
beq kernel_dbg_exc; /* if from kernel mode */
447
/* Now we mash up things to make it look like we are coming on a
450
mfspr r15,SPRN_SPRG_CRIT_SCRATCH
451
mtspr SPRN_SPRG_GEN_SCRATCH,r15
453
EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
455
addi r3,r1,STACK_FRAME_OVERHEAD
457
ld r14,PACA_EXCRIT+EX_R14(r13)
458
ld r15,PACA_EXCRIT+EX_R15(r13)
466
/* Debug exception as a debug interrupt*/
467
START_EXCEPTION(debug_debug);
468
DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
471
* If there is a single step or branch-taken exception in an
472
* exception entry sequence, it was probably meant to apply to
473
* the code where the exception occurred (since exception entry
474
* doesn't turn off DE automatically). We simulate the effect
475
* of turning off DE on entry to an exception handler by turning
476
* off DE in the DSRR1 value and clearing the debug status.
479
mfspr r14,SPRN_DBSR /* check single-step/branch taken */
480
andis. r15,r14,DBSR_IC@h
483
LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
484
LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
490
/* here it looks like we got an inappropriate debug exception. */
491
lis r14,DBSR_IC@h /* clear the IC event */
492
rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
495
lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
496
ld r1,PACA_EXDBG+EX_R1(r13)
497
ld r14,PACA_EXDBG+EX_R14(r13)
498
ld r15,PACA_EXDBG+EX_R15(r13)
500
ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
501
ld r11,PACA_EXDBG+EX_R11(r13)
502
mfspr r13,SPRN_SPRG_DBG_SCRATCH
505
/* Normal debug exception */
506
/* XXX We only handle coming from userspace for now since we can't
507
* quite save properly an interrupted kernel state yet
509
1: andi. r14,r11,MSR_PR; /* check for userspace again */
510
beq kernel_dbg_exc; /* if from kernel mode */
512
/* Now we mash up things to make it look like we are coming on a
515
mfspr r15,SPRN_SPRG_DBG_SCRATCH
516
mtspr SPRN_SPRG_GEN_SCRATCH,r15
518
EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
520
addi r3,r1,STACK_FRAME_OVERHEAD
522
ld r14,PACA_EXDBG+EX_R14(r13)
523
ld r15,PACA_EXDBG+EX_R15(r13)
528
MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
530
/* Doorbell interrupt */
531
START_EXCEPTION(doorbell)
532
NORMAL_EXCEPTION_PROLOG(0x2070, PROLOG_ADDITION_DOORBELL)
533
EXCEPTION_COMMON(0x2070, PACA_EXGEN, INTS_DISABLE_ALL)
535
addi r3,r1,STACK_FRAME_OVERHEAD
536
bl .doorbell_exception
537
b .ret_from_except_lite
539
/* Doorbell critical Interrupt */
540
START_EXCEPTION(doorbell_crit);
541
CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
542
// EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
543
// bl special_reg_save_crit
545
// addi r3,r1,STACK_FRAME_OVERHEAD
546
// bl .doorbell_critical_exception
547
// b ret_from_crit_except
550
MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
551
MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE)
552
MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE)
553
MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE)
557
* An interrupt came in while soft-disabled; clear EE in SRR1,
558
* clear paca->hard_enabled and return.
560
masked_doorbell_book3e:
562
/* Resend the doorbell to fire again when ints enabled */
565
b masked_interrupt_book3e_common
567
masked_interrupt_book3e:
569
masked_interrupt_book3e_common:
570
stb r11,PACAHARDIRQEN(r13)
572
rldicl r11,r10,48,1 /* clear MSR_EE */
575
ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */
576
ld r11,PACA_EXGEN+EX_R11(r13);
577
mfspr r13,SPRN_SPRG_GEN_SCRATCH;
582
* This is called from 0x300 and 0x400 handlers after the prologs with
583
* r14 and r15 containing the fault address and error code, with the
584
* original values stashed away in the PACA
586
storage_fault_common:
589
addi r3,r1,STACK_FRAME_OVERHEAD
592
ld r14,PACA_EXGEN+EX_R14(r13)
593
ld r15,PACA_EXGEN+EX_R15(r13)
598
b .ret_from_except_lite
601
addi r3,r1,STACK_FRAME_OVERHEAD
607
* Alignment exception doesn't fit entirely in the 0x100 bytes so it
613
addi r3,r1,STACK_FRAME_OVERHEAD
614
ld r14,PACA_EXGEN+EX_R14(r13)
615
ld r15,PACA_EXGEN+EX_R15(r13)
618
bl .alignment_exception
622
* We branch here from entry_64.S for the last stage of the exception
623
* return code path. MSR:EE is expected to be off at that point
625
_GLOBAL(exception_return_book3e)
628
/* This is the return from load_up_fpu fast path which could do with
629
* less GPR restores in fact, but for now we have a single return path
631
.globl fast_exception_return
632
fast_exception_return:
640
ACCOUNT_CPU_USER_EXIT(r10, r11)
643
1: stdcx. r0,0,r1 /* to clear the reservation */
657
mtspr SPRN_SPRG_GEN_SCRATCH,r0
659
std r10,PACA_EXGEN+EX_R10(r13);
660
std r11,PACA_EXGEN+EX_R11(r13);
667
ld r10,PACA_EXGEN+EX_R10(r13)
668
ld r11,PACA_EXGEN+EX_R11(r13)
669
mfspr r13,SPRN_SPRG_GEN_SCRATCH
673
* Trampolines used when spotting a bad kernel stack pointer in
674
* the exception entry code.
676
* TODO: move some bits like SRR0 read to trampoline, pass PACA
677
* index around, etc... to handle crit & mcheck
679
BAD_STACK_TRAMPOLINE(0x000)
680
BAD_STACK_TRAMPOLINE(0x100)
681
BAD_STACK_TRAMPOLINE(0x200)
682
BAD_STACK_TRAMPOLINE(0x260)
683
BAD_STACK_TRAMPOLINE(0x2c0)
684
BAD_STACK_TRAMPOLINE(0x2e0)
685
BAD_STACK_TRAMPOLINE(0x300)
686
BAD_STACK_TRAMPOLINE(0x310)
687
BAD_STACK_TRAMPOLINE(0x320)
688
BAD_STACK_TRAMPOLINE(0x400)
689
BAD_STACK_TRAMPOLINE(0x500)
690
BAD_STACK_TRAMPOLINE(0x600)
691
BAD_STACK_TRAMPOLINE(0x700)
692
BAD_STACK_TRAMPOLINE(0x800)
693
BAD_STACK_TRAMPOLINE(0x900)
694
BAD_STACK_TRAMPOLINE(0x980)
695
BAD_STACK_TRAMPOLINE(0x9f0)
696
BAD_STACK_TRAMPOLINE(0xa00)
697
BAD_STACK_TRAMPOLINE(0xb00)
698
BAD_STACK_TRAMPOLINE(0xc00)
699
BAD_STACK_TRAMPOLINE(0xd00)
700
BAD_STACK_TRAMPOLINE(0xe00)
701
BAD_STACK_TRAMPOLINE(0xf00)
702
BAD_STACK_TRAMPOLINE(0xf20)
703
BAD_STACK_TRAMPOLINE(0x2070)
704
BAD_STACK_TRAMPOLINE(0x2080)
706
.globl bad_stack_book3e
708
/* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
709
mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
710
ld r1,PACAEMERGSP(r13)
711
subi r1,r1,64+INT_FRAME_SIZE
714
ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
715
lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
722
std r0,GPR0(r1); /* save r0 in stackframe */ \
723
std r2,GPR2(r1); /* save r2 in stackframe */ \
724
SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
725
SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
726
std r9,GPR9(r1); /* save r9 in stackframe */ \
727
ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
728
ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
729
mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
730
std r3,GPR10(r1); /* save r10 to stackframe */ \
731
std r4,GPR11(r1); /* save r11 to stackframe */ \
732
std r12,GPR12(r1); /* save r12 in stackframe */ \
733
std r5,GPR13(r1); /* save it to stackframe */ \
742
lhz r12,PACA_TRAP_SAVE(r13)
744
addi r11,r1,INT_FRAME_SIZE
749
1: addi r3,r1,STACK_FRAME_OVERHEAD
754
* Setup the initial TLB for a core. This current implementation
755
* assume that whatever we are running off will not conflict with
756
* the new mapping at PAGE_OFFSET.
758
_GLOBAL(initial_tlb_book3e)
760
/* Look for the first TLB with IPROT set */
761
mfspr r4,SPRN_TLB0CFG
762
andi. r3,r4,TLBnCFG_IPROT
763
lis r3,MAS0_TLBSEL(0)@h
766
mfspr r4,SPRN_TLB1CFG
767
andi. r3,r4,TLBnCFG_IPROT
768
lis r3,MAS0_TLBSEL(1)@h
771
mfspr r4,SPRN_TLB2CFG
772
andi. r3,r4,TLBnCFG_IPROT
773
lis r3,MAS0_TLBSEL(2)@h
776
lis r3,MAS0_TLBSEL(3)@h
777
mfspr r4,SPRN_TLB3CFG
781
andi. r5,r4,TLBnCFG_HES
784
mflr r8 /* save LR */
785
/* 1. Find the index of the entry we're executing in
787
* r3 = MAS0_TLBSEL (for the iprot array)
790
bl invstr /* Find our address */
791
invstr: mflr r6 /* Make it accessible */
793
rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
798
tlbsx 0,r6 /* search MSR[IS], SPID=PID */
801
rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
803
mfspr r7,SPRN_MAS1 /* Insure IPROT set */
804
oris r7,r7,MAS1_IPROT@h
808
/* 2. Invalidate all entries except the entry we're executing in
810
* r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
812
* r5 = ESEL of entry we are running in
814
andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
815
li r6,0 /* Set Entry counter to 0 */
816
1: mr r7,r3 /* Set MAS0(TLBSEL) */
817
rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
821
rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
823
beq skpinv /* Dont update the current execution TLB */
827
skpinv: addi r6,r6,1 /* Increment */
828
cmpw r6,r4 /* Are we done? */
829
bne 1b /* If not, repeat */
831
/* Invalidate all TLBs */
836
/* 3. Setup a temp mapping and jump to it
838
* r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
839
* r5 = ESEL of entry we are running in
841
andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
843
mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
847
rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
851
xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
859
bl 1f /* Find our address */
866
/* 4. Clear out PIDs & Search info
868
* r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
869
* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
876
/* 5. Invalidate mapping we started in
878
* r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
879
* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
885
rlwinm r6,r6,0,2,0 /* clear IPROT */
889
/* Invalidate TLB1 */
894
/* The mapping only needs to be cache-coherent on SMP */
896
#define M_IF_SMP MAS2_M
901
/* 6. Setup KERNELBASE mapping in TLB[0]
903
* r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
904
* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
907
rlwinm r3,r3,0,16,3 /* clear ESEL */
909
lis r6,(MAS1_VALID|MAS1_IPROT)@h
910
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
913
LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
917
ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
924
/* 7. Jump to KERNELBASE mapping
926
* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
928
/* Now we branch the new virtual address mapped by this entry */
929
LOAD_REG_IMMEDIATE(r6,2f)
931
ori r7,r7,MSR_KERNEL@l
934
rfi /* start execution out of TLB1[0] entry */
937
/* 8. Clear out the temp mapping
939
* r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
944
rlwinm r5,r5,0,2,0 /* clear IPROT */
948
/* Invalidate TLB1 */
953
/* We translate LR and return */
959
/* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
960
* kernel linear mapping. We also set MAS8 once for all here though
961
* that will have to be made dependent on whether we are running under
962
* a hypervisor I suppose.
966
* This code is called as an ordinary function on the boot CPU. But to
967
* avoid duplication, this code is also used in SCOM bringup of
968
* secondary CPUs. We read the code between the initial_tlb_code_start
969
* and initial_tlb_code_end labels one instruction at a time and RAM it
970
* into the new core via SCOM. That doesn't process branches, so there
971
* must be none between those two labels. It also means if this code
972
* ever takes any parameters, the SCOM code must also be updated to
975
.globl a2_tlbinit_code_start
976
a2_tlbinit_code_start:
978
ori r11,r3,MAS0_WQ_ALLWAYS
979
oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
981
lis r3,(MAS1_VALID | MAS1_IPROT)@h
982
ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
984
LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
986
li r3,MAS3_SR | MAS3_SW | MAS3_SX
987
mtspr SPRN_MAS7_MAS3,r3
991
/* Write the TLB entry */
994
.globl a2_tlbinit_after_linear_map
995
a2_tlbinit_after_linear_map:
997
/* Now we branch the new virtual address mapped by this entry */
998
LOAD_REG_IMMEDIATE(r3,1f)
1002
1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1003
* else (including IPROTed things left by firmware)
1005
* r3 = current address (more or less)
1012
rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1013
rlwinm r10,r4,8,0xff
1014
addi r10,r10,-1 /* Get inner loop mask */
1019
rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1022
rldicr r6,r6,0,51 /* Extract EPN */
1025
rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1027
rlwinm r8,r7,16,0xfff /* Extract ESEL */
1032
rlwimi r7,r4,16,MAS0_ESEL_MASK
1043
addis r6,r6,(1<<30)@h
1048
.globl a2_tlbinit_after_iprot_flush
1049
a2_tlbinit_after_iprot_flush:
1051
#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1052
/* Now establish early debug mappings if applicable */
1053
/* Restore the MAS0 we used for linear mapping load */
1056
lis r3,(MAS1_VALID | MAS1_IPROT)@h
1057
ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1059
LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1061
LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1062
mtspr SPRN_MAS7_MAS3,r3
1063
/* re-use the MAS8 value from the linear mapping */
1065
#endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1071
.globl a2_tlbinit_code_end
1072
a2_tlbinit_code_end:
1074
/* We translate LR and return */
1081
* Main entry (boot CPU, thread 0)
1083
* We enter here from head_64.S, possibly after the prom_init trampoline
1084
* with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1085
* mode. Anything else is as it was left by the bootloader
1087
* Initial requirements of this port:
1089
* - Kernel loaded at 0 physical
1090
* - A good lump of memory mapped 0:0 by UTLB entry 0
1091
* - MSR:IS & MSR:DS set to 0
1093
* Note that some of the above requirements will be relaxed in the future
1094
* as the kernel becomes smarter at dealing with different initial conditions
1095
* but for now you have to be careful
1097
_GLOBAL(start_initialization_book3e)
1100
/* First, we need to setup some initial TLBs to map the kernel
1101
* text, data and bss at PAGE_OFFSET. We don't have a real mode
1102
* and always use AS 0, so we just set it up to match our link
1103
* address and never use 0 based addresses.
1105
bl .initial_tlb_book3e
1107
/* Init global core bits */
1108
bl .init_core_book3e
1110
/* Init per-thread bits */
1111
bl .init_thread_book3e
1113
/* Return to common init code */
1120
* Secondary core/processor entry
1122
* This is entered for thread 0 of a secondary core, all other threads
1123
* are expected to be stopped. It's similar to start_initialization_book3e
1124
* except that it's generally entered from the holding loop in head_64.S
1125
* after CPUs have been gathered by Open Firmware.
1127
* We assume we are in 32 bits mode running with whatever TLB entry was
1128
* set for us by the firmware or POR engine.
1130
_GLOBAL(book3e_secondary_core_init_tlb_set)
1132
b .generic_secondary_smp_init
1134
_GLOBAL(book3e_secondary_core_init)
1137
/* Do we need to setup initial TLB entry ? */
1141
/* Setup TLB for this core */
1142
bl .initial_tlb_book3e
1144
/* We can return from the above running at a different
1145
* address, so recalculate r2 (TOC)
1149
/* Init global core bits */
1150
2: bl .init_core_book3e
1152
/* Init per-thread bits */
1153
3: bl .init_thread_book3e
1155
/* Return to common init code at proper virtual address.
1157
* Due to various previous assumptions, we know we entered this
1158
* function at either the final PAGE_OFFSET mapping or using a
1159
* 1:1 mapping at 0, so we don't bother doing a complicated check
1160
* here, we just ensure the return address has the right top bits.
1162
* Note that if we ever want to be smarter about where we can be
1163
* started from, we have to be careful that by the time we reach
1164
* the code below we may already be running at a different location
1165
* than the one we were called from since initial_tlb_book3e can
1166
* have moved us already.
1170
lis r3,PAGE_OFFSET@highest
1176
_GLOBAL(book3e_secondary_thread_init)
1180
_STATIC(init_core_book3e)
1181
/* Establish the interrupt vector base */
1182
LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1187
_STATIC(init_thread_book3e)
1188
lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1191
/* Make sure interrupts are off */
1194
/* disable all timers and clear out status */
1202
_GLOBAL(__setup_base_ivors)
1203
SET_IVOR(0, 0x020) /* Critical Input */
1204
SET_IVOR(1, 0x000) /* Machine Check */
1205
SET_IVOR(2, 0x060) /* Data Storage */
1206
SET_IVOR(3, 0x080) /* Instruction Storage */
1207
SET_IVOR(4, 0x0a0) /* External Input */
1208
SET_IVOR(5, 0x0c0) /* Alignment */
1209
SET_IVOR(6, 0x0e0) /* Program */
1210
SET_IVOR(7, 0x100) /* FP Unavailable */
1211
SET_IVOR(8, 0x120) /* System Call */
1212
SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1213
SET_IVOR(10, 0x160) /* Decrementer */
1214
SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1215
SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1216
SET_IVOR(13, 0x1c0) /* Data TLB Error */
1217
SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1218
SET_IVOR(15, 0x040) /* Debug */
1224
_GLOBAL(setup_perfmon_ivor)
1225
SET_IVOR(35, 0x260) /* Performance Monitor */
1228
_GLOBAL(setup_doorbell_ivors)
1229
SET_IVOR(36, 0x280) /* Processor Doorbell */
1230
SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1232
/* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
1233
mfspr r10,SPRN_MMUCFG
1234
rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1237
SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1238
SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1241
_GLOBAL(setup_ehv_ivors)
1243
* We may be running as a guest and lack E.HV even on a chip
1244
* that normally has it.
1246
mfspr r10,SPRN_MMUCFG
1247
rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1250
SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1251
SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */