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* CS5536 General timer functions
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* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
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* Author: Yanhua, yanh@lemote.com
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* Copyright (C) 2009 Lemote Inc.
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* Author: Wu zhangjin, wuzhangjin@gmail.com
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* Reference: AMD Geode(TM) CS5536 Companion Device Data Book
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/jiffies.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <cs5536/cs5536_mfgpt.h>
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DEFINE_SPINLOCK(mfgpt_lock);
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EXPORT_SYMBOL(mfgpt_lock);
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static u32 mfgpt_base;
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* Initialize the MFGPT timer.
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* This is also called after resume to bring the MFGPT into operation again.
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void disable_mfgpt0_counter(void)
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outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
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EXPORT_SYMBOL(disable_mfgpt0_counter);
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/* enable counter, comparator2 to event mode, 14.318MHz clock */
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void enable_mfgpt0_counter(void)
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outw(0xe310, MFGPT0_SETUP);
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EXPORT_SYMBOL(enable_mfgpt0_counter);
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static void init_mfgpt_timer(enum clock_event_mode mode,
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struct clock_event_device *evt)
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spin_lock(&mfgpt_lock);
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case CLOCK_EVT_MODE_PERIODIC:
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outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */
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outw(0, MFGPT0_CNT); /* set counter to 0 */
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enable_mfgpt0_counter();
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
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evt->mode == CLOCK_EVT_MODE_ONESHOT)
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disable_mfgpt0_counter();
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case CLOCK_EVT_MODE_ONESHOT:
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/* The oneshot mode have very high deviation, Not use it! */
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case CLOCK_EVT_MODE_RESUME:
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/* Nothing to do here */
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spin_unlock(&mfgpt_lock);
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static struct clock_event_device mfgpt_clockevent = {
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = init_mfgpt_timer,
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.irq = CS5536_MFGPT_INTR,
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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* get MFGPT base address
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* NOTE: do not remove me, it's need for the value of mfgpt_base is
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_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
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outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
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mfgpt_clockevent.event_handler(&mfgpt_clockevent);
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static struct irqaction irq5 = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
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* Initialize the conversion factor and the min/max deltas of the clock event
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* structure and register the clock event source with the framework.
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void __init setup_mfgpt0_timer(void)
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struct clock_event_device *cd = &mfgpt_clockevent;
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unsigned int cpu = smp_processor_id();
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cd->cpumask = cpumask_of(cpu);
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clockevent_set_clock(cd, MFGPT_TICK_RATE);
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cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
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/* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
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_wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
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/* Enable Interrupt Gate 5 */
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_wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
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/* get MFGPT base address */
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_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
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clockevents_register_device(cd);
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setup_irq(CS5536_MFGPT_INTR, &irq5);
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* Since the MFGPT overflows every tick, its not very useful
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* to just read by itself. So use jiffies to emulate a free
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static cycle_t mfgpt_read(struct clocksource *cs)
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static int old_count;
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spin_lock_irqsave(&mfgpt_lock, flags);
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* Although our caller may have the read side of xtime_lock,
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* this is now a seqlock, and we are cheating in this routine
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* by having side effects on state that we cannot undo if
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* there is a collision on the seqlock and our caller has to
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* retry. (Namely, old_jifs and old_count.) So we must treat
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* jiffies as volatile despite the lock. We read jiffies
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* before latching the timer count to guarantee that although
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* the jiffies value might be older than the count (that is,
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* the counter may underflow between the last point where
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* jiffies was incremented and the point where we latch the
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* count), it cannot be newer.
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count = inw(MFGPT0_CNT);
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* It's possible for count to appear to go the wrong way for this
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* The timer counter underflows, but we haven't handled the resulting
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* interrupt and incremented jiffies yet.
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* Previous attempts to handle these cases intelligently were buggy, so
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* we just do the simple thing now.
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if (count < old_count && jifs == old_jifs)
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spin_unlock_irqrestore(&mfgpt_lock, flags);
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return (cycle_t) (jifs * COMPARE) + count;
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static struct clocksource clocksource_mfgpt = {
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.rating = 120, /* Functional for real use, but not desired */
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.mask = CLOCKSOURCE_MASK(32),
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int __init init_mfgpt_clocksource(void)
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if (num_possible_cpus() > 1) /* MFGPT does not scale! */
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return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
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arch_initcall(init_mfgpt_clocksource);