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/* Driver for Realtek PCI-Express card reader
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* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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* wwang (wei_wang@realsil.com.cn)
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* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
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#ifndef __REALTEK_RTSX_CHIP_H
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#define __REALTEK_RTSX_CHIP_H
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#define SUPPORT_SDIO_ASPM
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#define SUPPORT_MAGIC_GATE
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#define SUPPORT_SD_LOCK
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/* Hardware switch bus_ctl and cd_ctl automatically */
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#define HW_AUTO_SWITCH_SD_BUS
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/* Enable hardware interrupt write clear */
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#define HW_INT_WRITE_CLR
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/* #define LED_AUTO_BLINK */
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/* #define DISABLE_CARD_INT */
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#ifdef SUPPORT_MAGIC_GATE
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/* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */
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#define MG_SET_ICV_SLOW
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/* HW may miss ERR/CMDNK signal when sampling INT status. */
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#define MS_SAMPLE_INT_ERR
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/* HW DO NOT support Wait_INT function during READ_BYTES transfer mode */
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#define READ_BYTES_WAIT_INT
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#define SUPPORT_PCGL_1P18
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#ifndef LED_AUTO_BLINK
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#define LED_BLINK_SPEED 5
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#define LED_TOGGLE_INTERVAL 6
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#define GPIO_TOGGLE_THRESHOLD 1024
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#define POLLING_INTERVAL 30
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#define TRACE_ITEM_CNT 64
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#ifndef STATUS_SUCCESS
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#define STATUS_SUCCESS 0
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#ifndef STATUS_TIMEDOUT
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#define STATUS_TIMEDOUT 2
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#define STATUS_NOMEM 3
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#ifndef STATUS_READ_FAIL
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#define STATUS_READ_FAIL 4
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#ifndef STATUS_WRITE_FAIL
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#define STATUS_WRITE_FAIL 5
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#define STATUS_ERROR 10
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* Transport return codes
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#define TRANSPORT_GOOD 0 /* Transport good, command good */
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#define TRANSPORT_FAILED 1 /* Transport good, command failed */
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#define TRANSPORT_NO_SENSE 2 /* Command failed, no auto-sense */
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#define TRANSPORT_ERROR 3 /* Transport bad (i.e. device dead) */
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/*-----------------------------------
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-----------------------------------*/
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#define STOP_MEDIUM 0x00 /* access disable */
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#define MAKE_MEDIUM_READY 0x01 /* access enable */
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#define UNLOAD_MEDIUM 0x02 /* unload */
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#define LOAD_MEDIUM 0x03 /* load */
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/*-----------------------------------
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-----------------------------------*/
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#define QULIFIRE 0x00
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#define AENC_FNC 0x00
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#define TRML_IOP 0x00
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#define VEN_ID_LEN 8 /* Vendor ID Length */
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#define PRDCT_ID_LEN 16 /* Product ID Length */
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#define PRDCT_REV_LEN 4 /* Product LOT Length */
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/* Dynamic flag definitions: used in set_bit() etc. */
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#define RTSX_FLIDX_TRANS_ACTIVE 18 /* 0x00040000 transfer is active */
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#define RTSX_FLIDX_ABORTING 20 /* 0x00100000 abort is in progress */
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#define RTSX_FLIDX_DISCONNECTING 21 /* 0x00200000 disconnect in progress */
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#define ABORTING_OR_DISCONNECTING ((1UL << US_FLIDX_ABORTING) | \
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(1UL << US_FLIDX_DISCONNECTING))
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#define RTSX_FLIDX_RESETTING 22 /* 0x00400000 device reset in progress */
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#define RTSX_FLIDX_TIMED_OUT 23 /* 0x00800000 SCSI midlayer timed out */
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#define DRCT_ACCESS_DEV 0x00 /* Direct Access Device */
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#define RMB_DISC 0x80 /* The Device is Removable */
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#define ANSI_SCSI2 0x02 /* Based on ANSI-SCSI2 */
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#define SCSI 0x00 /* Interface ID */
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#define WRITE_PROTECTED_MEDIA 0x07
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/*---- sense key ----*/
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#define ILI 0x20 /* ILI bit is on */
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#define NO_SENSE 0x00 /* not exist sense key */
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#define RECOVER_ERR 0x01 /* Target/Logical unit is recoverd */
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#define NOT_READY 0x02 /* Logical unit is not ready */
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#define MEDIA_ERR 0x03 /* medium/data error */
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#define HARDWARE_ERR 0x04 /* hardware error */
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#define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */
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#define UNIT_ATTENTION 0x06 /* unit attention condition occur */
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#define DAT_PRTCT 0x07 /* read/write is desable */
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#define BLNC_CHK 0x08 /* find blank/DOF in read */
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/* write to unblank area */
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#define CPY_ABRT 0x0a /* Copy/Compare/Copy&Verify illgal */
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#define ABRT_CMD 0x0b /* Target make the command in error */
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#define EQUAL 0x0c /* Search Data end with Equal */
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#define VLM_OVRFLW 0x0d /* Some data are left in buffer */
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#define MISCMP 0x0e /* find inequality */
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#define FIRST_RESET 0x01
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#define USED_EXIST 0x02
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/*-----------------------------------
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-----------------------------------*/
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#define SENSE_VALID 0x80 /* Sense data is valid as SCSI2 */
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#define SENSE_INVALID 0x00 /* Sense data is invalid as SCSI2 */
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/*---- error code ----*/
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#define CUR_ERR 0x70 /* current error */
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#define DEF_ERR 0x71 /* specific command error */
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/*---- sense key Information ----*/
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#define SNSKEYINFO_LEN 3 /* length of sense key information */
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#define CDB_ILLEGAL 0x40
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#define DAT_ILLEGAL 0x00
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#define BIT_ILLEGAL0 0 /* bit0 is illegal */
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#define BIT_ILLEGAL1 1 /* bit1 is illegal */
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#define BIT_ILLEGAL2 2 /* bit2 is illegal */
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#define BIT_ILLEGAL3 3 /* bit3 is illegal */
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#define BIT_ILLEGAL4 4 /* bit4 is illegal */
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#define BIT_ILLEGAL5 5 /* bit5 is illegal */
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#define BIT_ILLEGAL6 6 /* bit6 is illegal */
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#define BIT_ILLEGAL7 7 /* bit7 is illegal */
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#define ASC_NO_INFO 0x00
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#define ASC_MISCMP 0x1d
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#define ASC_INVLD_CDB 0x24
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#define ASC_INVLD_PARA 0x26
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#define ASC_LU_NOT_READY 0x04
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#define ASC_WRITE_ERR 0x0c
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#define ASC_READ_ERR 0x11
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#define ASC_LOAD_EJCT_ERR 0x53
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#define ASC_MEDIA_NOT_PRESENT 0x3A
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#define ASC_MEDIA_CHANGED 0x28
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#define ASC_MEDIA_IN_PROCESS 0x04
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#define ASC_WRITE_PROTECT 0x27
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#define ASC_LUN_NOT_SUPPORTED 0x25
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#define ASCQ_NO_INFO 0x00
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#define ASCQ_MEDIA_IN_PROCESS 0x01
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#define ASCQ_MISCMP 0x00
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#define ASCQ_INVLD_CDB 0x00
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#define ASCQ_INVLD_PARA 0x02
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#define ASCQ_LU_NOT_READY 0x02
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#define ASCQ_WRITE_ERR 0x02
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#define ASCQ_READ_ERR 0x00
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#define ASCQ_LOAD_EJCT_ERR 0x00
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#define ASCQ_WRITE_PROTECT 0x00
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struct sense_data_t {
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unsigned char err_code; /* error code */
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/* (0 : Vendor specific) */
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/* bit6-0 : error code */
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/* (0x70 : current error) */
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/* (0x71 : specific command error) */
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unsigned char seg_no; /* segment No. */
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unsigned char sense_key; /* byte5 : ILI */
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/* bit3-0 : sense key */
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unsigned char info[4]; /* information */
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unsigned char ad_sense_len; /* additional sense data length */
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unsigned char cmd_info[4]; /* command specific information */
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unsigned char asc; /* ASC */
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unsigned char ascq; /* ASCQ */
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unsigned char rfu; /* FRU */
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unsigned char sns_key_info[3]; /* sense key specific information */
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/* PCI Operation Register Address */
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#define RTSX_HCBAR 0x00
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#define RTSX_HCBCTLR 0x04
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#define RTSX_HDBAR 0x08
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#define RTSX_HDBCTLR 0x0C
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#define RTSX_HAIMR 0x10
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#define RTSX_BIPR 0x14
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#define RTSX_BIER 0x18
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/* Host command buffer control register */
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#define STOP_CMD (0x01 << 28)
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/* Host data buffer control register */
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#define SDMA_MODE 0x00
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#define ADMA_MODE (0x02 << 26)
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#define STOP_DMA (0x01 << 28)
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#define TRIG_DMA (0x01 << 31)
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/* Bus interrupt pending register */
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#define CMD_DONE_INT (1 << 31)
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#define DATA_DONE_INT (1 << 30)
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#define TRANS_OK_INT (1 << 29)
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#define TRANS_FAIL_INT (1 << 28)
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#define XD_INT (1 << 27)
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#define MS_INT (1 << 26)
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#define SD_INT (1 << 25)
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#define GPIO0_INT (1 << 24)
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#define OC_INT (1 << 23)
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#define SD_WRITE_PROTECT (1 << 19)
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#define XD_EXIST (1 << 18)
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#define MS_EXIST (1 << 17)
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#define SD_EXIST (1 << 16)
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#define DELINK_INT GPIO0_INT
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#define MS_OC_INT (1 << 23)
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#define SD_OC_INT (1 << 22)
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#define CARD_INT (XD_INT | MS_INT | SD_INT)
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#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
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#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | GPIO0_INT | OC_INT)
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#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
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/* Bus interrupt enable register */
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#define CMD_DONE_INT_EN (1 << 31)
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#define DATA_DONE_INT_EN (1 << 30)
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#define TRANS_OK_INT_EN (1 << 29)
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#define TRANS_FAIL_INT_EN (1 << 28)
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#define XD_INT_EN (1 << 27)
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#define MS_INT_EN (1 << 26)
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#define SD_INT_EN (1 << 25)
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#define GPIO0_INT_EN (1 << 24)
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#define OC_INT_EN (1 << 23)
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#define DELINK_INT_EN GPIO0_INT_EN
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#define MS_OC_INT_EN (1 << 23)
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#define SD_OC_INT_EN (1 << 22)
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#define READ_REG_CMD 0
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#define WRITE_REG_CMD 1
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#define CHECK_REG_CMD 2
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#define HOST_TO_DEVICE 0
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#define DEVICE_TO_HOST 1
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#define RTSX_RESV_BUF_LEN 4096
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#define HOST_CMDS_BUF_LEN 1024
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#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
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#define SD_CARD (1 << SD_NR)
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#define MS_CARD (1 << MS_NR)
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#define XD_CARD (1 << XD_NR)
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#define SPI_CARD (1 << SPI_NR)
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#define MAX_ALLOWED_LUN_CNT 8
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#define XD_FREE_TABLE_CNT 1200
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#define MS_FREE_TABLE_CNT 512
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#define SET_BIT(data, idx) ((data) |= 1 << (idx))
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#define CLR_BIT(data, idx) ((data) &= ~(1 << (idx)))
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#define CHK_BIT(data, idx) ((data) & (1 << (idx)))
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#define SG_VALID 0x01
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#define SG_NO_OP 0x00
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#define SG_TRANS_DATA (0x02 << 4)
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#define SG_LINK_DESC (0x03 << 4)
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typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 sec_addr, u16 sec_cnt);
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/* Supported Clock */
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enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, CLK_80, CLK_100, CLK_120, CLK_150, CLK_200};
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enum RTSX_STAT {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS,
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RTSX_STAT_DELINK, RTSX_STAT_SUSPEND, RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT};
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enum IC_VER {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3};
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#define MAX_RESET_CNT 3
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#define MAX_DEFECTIVE_BLOCK 10
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u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */
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/* To indicate whether the L2P table of this zone has been built. */
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#define TYPE_SD 0x0000
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#define TYPE_MMC 0x0001
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#define SD_SDR50 0x0200
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#define SD_DDR50 0x0400
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#define SD_SDR104 0x0800
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#define SD_HCXC 0x1000
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#define MMC_26M 0x0100
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#define MMC_52M 0x0200
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#define MMC_4BIT 0x0400
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#define MMC_8BIT 0x0800
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#define MMC_SECTOR_MODE 0x1000
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#define MMC_DDR52 0x2000
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#define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD)
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#define CHK_SD_HS(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS))
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#define CHK_SD_SDR50(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50))
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#define CHK_SD_DDR50(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50))
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#define CHK_SD_SDR104(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104))
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#define CHK_SD_HCXC(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC))
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#define CHK_SD_HC(sd_card) (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity <= 0x4000000))
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#define CHK_SD_XC(sd_card) (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity > 0x4000000))
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#define CHK_SD30_SPEED(sd_card) (CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) || CHK_SD_SDR104(sd_card))
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#define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD)
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#define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS)
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#define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50)
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#define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50)
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#define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104)
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#define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC)
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#define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS)
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#define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50)
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#define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50)
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#define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104)
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#define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC)
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#define CHK_MMC(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_MMC)
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#define CHK_MMC_26M(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M))
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#define CHK_MMC_52M(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M))
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#define CHK_MMC_4BIT(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT))
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#define CHK_MMC_8BIT(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT))
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#define CHK_MMC_SECTOR_MODE(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE))
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#define CHK_MMC_DDR52(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52))
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#define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC)
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#define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M)
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#define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M)
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#define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT)
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#define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT)
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#define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE)
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#define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52)
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#define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M)
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#define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M)
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#define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT)
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#define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT)
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#define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE)
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#define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52)
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#define CHK_MMC_HS(sd_card) (CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card))
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#define CLR_MMC_HS(sd_card) \
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CLR_MMC_DDR52(sd_card); \
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CLR_MMC_52M(sd_card); \
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CLR_MMC_26M(sd_card); \
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#define SD_SUPPORT_CLASS_TEN 0x01
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#define SD_SUPPORT_1V8 0x02
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#define SD_SET_CLASS_TEN(sd_card) ((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN)
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#define SD_CHK_CLASS_TEN(sd_card) ((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN)
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#define SD_CLR_CLASS_TEN(sd_card) ((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN)
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#define SD_SET_1V8(sd_card) ((sd_card)->sd_setting |= SD_SUPPORT_1V8)
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#define SD_CHK_1V8(sd_card) ((sd_card)->sd_setting & SD_SUPPORT_1V8)
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#define SD_CLR_1V8(sd_card) ((sd_card)->sd_setting &= ~SD_SUPPORT_1V8)
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u8 sd_data_buf_ready;
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enum dma_data_direction pre_dir;
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int mmc_dont_switch_bus;
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#ifdef SUPPORT_SD_LOCK
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struct xd_delay_write_tag {
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struct zone_entry *zone;
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struct xd_delay_write_tag delay_write;
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#define MODE_512_SEQ 0x01
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#define MODE_2K_SEQ 0x02
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#define TYPE_MS 0x0000
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#define TYPE_MSPRO 0x0001
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#define MS_4BIT 0x0100
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#define MS_8BIT 0x0200
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#define HG8BIT (MS_HG | MS_8BIT)
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#define CHK_MSPRO(ms_card) (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO)
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#define CHK_HG8BIT(ms_card) (CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT))
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#define CHK_MSXC(ms_card) (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC))
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#define CHK_MSHG(ms_card) (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG))
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#define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT))
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#define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT))
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struct ms_delay_write_tag {
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struct zone_entry *segment;
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int pro_under_formatting;
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#ifdef SUPPORT_PCGL_1P18
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u8 raw_model_name[48];
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enum dma_data_direction pre_dir;
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struct ms_delay_write_tag delay_write;
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#ifdef SUPPORT_MAGIC_GATE
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u8 magic_gate_id[16];
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int mg_auth; /* flag to indicate authentication process */
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#define MSG_FUNC_LEN 64
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char func[MSG_FUNC_LEN];
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#define MSG_FILE_LEN 32
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char file[MSG_FILE_LEN];
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#define TIME_VAL_LEN 16
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u8 timeval_buf[TIME_VAL_LEN];
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/* Single LUN, support xD/SD/MS */
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#define DEFAULT_SINGLE 0
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/* 2 LUN mode, support SD/MS */
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/* Single LUN, but only support SD/MS, for Barossa LQFP */
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#define LAST_LUN_MODE 2
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/* Barossa package */
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/* SD push point control, bit 0, 1 */
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#define SD_PUSH_POINT_CTL_MASK 0x03
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#define SD_PUSH_POINT_DELAY 0x01
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#define SD_PUSH_POINT_AUTO 0x02
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/* SD sample point control, bit 2, 3 */
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#define SD_SAMPLE_POINT_CTL_MASK 0x0C
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#define SD_SAMPLE_POINT_DELAY 0x04
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#define SD_SAMPLE_POINT_AUTO 0x08
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/* SD DDR Tx phase set by user, bit 4 */
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#define SD_DDR_TX_PHASE_SET_BY_USER 0x10
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/* MMC DDR Tx phase set by user, bit 5 */
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#define MMC_DDR_TX_PHASE_SET_BY_USER 0x20
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/* Support MMC DDR mode, bit 6 */
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#define SUPPORT_MMC_DDR_MODE 0x40
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/* Reset MMC at first */
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#define RESET_MMC_FIRST 0x80
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#define SEQ_START_CRITERIA 0x20
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/* MS Power Class En */
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#define POWER_CLASS_2_EN 0x02
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#define POWER_CLASS_1_EN 0x01
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#define MAX_SHOW_CNT 10
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#define MAX_RESET_CNT 3
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#define SDIO_EXIST 0x01
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#define SDIO_IGNORED 0x02
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#define CHK_SDIO_EXIST(chip) ((chip)->sdio_func_exist & SDIO_EXIST)
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#define SET_SDIO_EXIST(chip) ((chip)->sdio_func_exist |= SDIO_EXIST)
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#define CLR_SDIO_EXIST(chip) ((chip)->sdio_func_exist &= ~SDIO_EXIST)
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#define CHK_SDIO_IGNORED(chip) ((chip)->sdio_func_exist & SDIO_IGNORED)
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#define SET_SDIO_IGNORED(chip) ((chip)->sdio_func_exist |= SDIO_IGNORED)
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#define CLR_SDIO_IGNORED(chip) ((chip)->sdio_func_exist &= ~SDIO_IGNORED)
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u32 int_reg; /* Bus interrupt pending register */
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void *host_cmds_ptr; /* host commands buffer pointer */
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dma_addr_t host_cmds_addr;
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int ci; /* Command Index */
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void *host_sg_tbl_ptr; /* SG descriptor table */
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dma_addr_t host_sg_tbl_addr;
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int sgi; /* SG entry index */
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struct scsi_cmnd *srb; /* current srb */
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struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT];
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int cur_clk; /* current card clock */
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/* Current accessed card */
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unsigned long need_release; /* need release bit map */
707
unsigned long need_reset; /* need reset bit map */
708
/* Flag to indicate that this card is just resumed from SS state,
709
* and need released before being resetted
711
unsigned long need_reinit;
720
u8 card_exist; /* card exist bit map (physical exist) */
721
u8 card_ready; /* card ready bit map (reset successfully) */
722
u8 card_fail; /* card reset fail bit map */
723
u8 card_ejected; /* card ejected bit map */
724
u8 card_wp; /* card write protected bit map */
726
u8 lun_mc; /* flag to indicate whether to answer MediaChange */
728
#ifndef LED_AUTO_BLINK
729
int led_toggle_counter;
732
int sd_reset_counter;
733
int xd_reset_counter;
734
int ms_reset_counter;
737
u8 card_bus_width[MAX_ALLOWED_LUN_CNT];
739
u32 capacity[MAX_ALLOWED_LUN_CNT];
740
/* read/write card function pointer */
741
card_rw_func rw_card[MAX_ALLOWED_LUN_CNT];
742
/* read/write capacity, used for GPIO Toggle */
743
u32 rw_cap[MAX_ALLOWED_LUN_CNT];
744
/* card to lun mapping table */
746
/* lun to card mapping table */
747
u8 lun2card[MAX_ALLOWED_LUN_CNT];
749
int rw_fail_cnt[MAX_ALLOWED_LUN_CNT];
755
/* card information */
756
struct sd_info sd_card;
757
struct xd_info xd_card;
758
struct ms_info ms_card;
763
struct trace_msg_t trace_msg[TRACE_ITEM_CNT];
768
int auto_delink_allowed;
775
u8 sdio_raw_data[12];
784
enum RTSX_STAT rtsx_stat;
790
int driver_first_load;
792
#ifdef HW_AUTO_SWITCH_SD_BUS
798
int chip_insert_with_sdio;
809
int power_down_in_ss;
822
u8 ms_power_class_en;
824
int mspro_formatter_enable;
826
int remote_wakeup_en;
835
int fpga_sd_sdr104_clk;
836
int fpga_sd_ddr50_clk;
837
int fpga_sd_sdr50_clk;
839
int fpga_mmc_52m_clk;
841
int fpga_ms_4bit_clk;
842
int fpga_ms_1bit_clk;
844
int asic_sd_sdr104_clk;
845
int asic_sd_ddr50_clk;
846
int asic_sd_sdr50_clk;
848
int asic_mmc_52m_clk;
850
int asic_ms_4bit_clk;
851
int asic_ms_1bit_clk;
853
u8 ssc_depth_sd_sdr104;
854
u8 ssc_depth_sd_ddr50;
855
u8 ssc_depth_sd_sdr50;
857
u8 ssc_depth_mmc_52m;
859
u8 ssc_depth_ms_4bit;
860
u8 ssc_depth_low_speed;
863
u8 sd30_drive_sel_1v8;
864
u8 sd30_drive_sel_3v3;
881
int mmc_ddr_tx_phase;
882
int sd_default_tx_phase;
883
int sd_default_rx_phase;
885
int pmos_pwr_on_interval;
886
int sd_voltage_switch_delay;
887
int s3_pwr_off_delay;
892
int do_delink_before_power_down;
896
int delink_stage1_step;
897
int delink_stage2_step;
898
int delink_stage3_step;
900
int auto_delink_in_L1;
901
int hp_watch_bios_hotplug;
909
u32 sd_current_prior;
913
#define rtsx_set_stat(chip, stat) \
915
if ((stat) != RTSX_STAT_IDLE) { \
916
(chip)->idle_counter = 0; \
918
(chip)->rtsx_stat = (enum RTSX_STAT)(stat); \
920
#define rtsx_get_stat(chip) ((chip)->rtsx_stat)
921
#define rtsx_chk_stat(chip, stat) ((chip)->rtsx_stat == (stat))
923
#define RTSX_SET_DELINK(chip) ((chip)->rtsx_flag |= 0x01)
924
#define RTSX_CLR_DELINK(chip) ((chip)->rtsx_flag &= 0xFE)
925
#define RTSX_TST_DELINK(chip) ((chip)->rtsx_flag & 0x01)
927
#define CHECK_PID(chip, pid) ((chip)->product_id == (pid))
928
#define CHECK_BARO_PKG(chip, pkg) ((chip)->baro_pkg == (pkg))
929
#define CHECK_LUN_MODE(chip, mode) ((chip)->lun_mode == (mode))
931
/* Power down control */
932
#define SSC_PDCTL 0x01
933
#define OC_PDCTL 0x02
935
int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl);
936
int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl);
938
void rtsx_disable_card_int(struct rtsx_chip *chip);
939
void rtsx_enable_card_int(struct rtsx_chip *chip);
940
void rtsx_enable_bus_int(struct rtsx_chip *chip);
941
void rtsx_disable_bus_int(struct rtsx_chip *chip);
942
int rtsx_reset_chip(struct rtsx_chip *chip);
943
int rtsx_init_chip(struct rtsx_chip *chip);
944
void rtsx_release_chip(struct rtsx_chip *chip);
945
void rtsx_polling_func(struct rtsx_chip *chip);
946
void rtsx_undo_delink(struct rtsx_chip *chip);
947
void rtsx_stop_cmd(struct rtsx_chip *chip, int card);
948
int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data);
949
int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data);
950
int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val);
951
int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val);
952
int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len);
953
int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len);
954
int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val);
955
int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val);
956
int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val);
957
int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val);
958
int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
959
int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
960
int rtsx_check_link_ready(struct rtsx_chip *chip);
961
void rtsx_enter_ss(struct rtsx_chip *chip);
962
void rtsx_exit_ss(struct rtsx_chip *chip);
963
int rtsx_pre_handle_interrupt(struct rtsx_chip *chip);
964
void rtsx_enter_L1(struct rtsx_chip *chip);
965
void rtsx_exit_L1(struct rtsx_chip *chip);
966
void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat);
967
void rtsx_enable_aspm(struct rtsx_chip *chip);
968
void rtsx_disable_aspm(struct rtsx_chip *chip);
969
int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
970
int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
971
int rtsx_check_chip_exist(struct rtsx_chip *chip);
973
#define RTSX_WRITE_REG(chip, addr, mask, data) \
975
int retval = rtsx_write_register((chip), (addr), (mask), (data)); \
976
if (retval != STATUS_SUCCESS) { \
977
TRACE_RET((chip), retval); \
981
#define RTSX_READ_REG(chip, addr, data) \
983
int retval = rtsx_read_register((chip), (addr), (data)); \
984
if (retval != STATUS_SUCCESS) { \
985
TRACE_RET((chip), retval); \
989
#endif /* __REALTEK_RTSX_CHIP_H */