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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
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* This file contains a module version of the ioc4 serial driver. This
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* includes all the support functions needed (support functions, etc.)
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* and the serial driver itself.
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#include <linux/errno.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial.h>
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#include <linux/serialP.h>
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#include <linux/circ_buf.h>
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#include <linux/serial_reg.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/ioc4.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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* interesting things about the ioc4
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#define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
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#define IOC4_NUM_CARDS 8 /* max cards per partition */
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#define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
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(_n == 1) ? (IOC4_SIO_IR_S1) : \
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(_n == 2) ? (IOC4_SIO_IR_S2) : \
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#define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
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(_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
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(_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
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(IOC4_OTHER_IR_S3_MEMERR)
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* All IOC4 registers are 32 bits wide.
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* PCI Memory Space Map
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#define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
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#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
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#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
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#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
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#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
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#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
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#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
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#define IOC4_SIO_INTR_TYPE 0
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#define IOC4_OTHER_INTR_TYPE 1
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#define IOC4_NUM_INTR_TYPES 2
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/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
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#define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
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#define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
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#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
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#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
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#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
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#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
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#define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
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#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
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#define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
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#define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
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#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
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#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
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#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
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#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
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#define IOC4_SIO_IR_S1_INT 0x00004000 /* */
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#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
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#define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
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#define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
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#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
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#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
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#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
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#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
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#define IOC4_SIO_IR_S2_INT 0x00400000 /* */
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#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
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#define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
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#define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
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#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
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#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
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#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
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#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
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#define IOC4_SIO_IR_S3_INT 0x40000000 /* */
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#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
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/* Per device interrupt masks */
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#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
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IOC4_SIO_IR_S0_RX_FULL | \
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IOC4_SIO_IR_S0_RX_HIGH | \
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IOC4_SIO_IR_S0_RX_TIMER | \
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IOC4_SIO_IR_S0_DELTA_DCD | \
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IOC4_SIO_IR_S0_DELTA_CTS | \
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IOC4_SIO_IR_S0_INT | \
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IOC4_SIO_IR_S0_TX_EXPLICIT)
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#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
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IOC4_SIO_IR_S1_RX_FULL | \
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IOC4_SIO_IR_S1_RX_HIGH | \
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IOC4_SIO_IR_S1_RX_TIMER | \
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IOC4_SIO_IR_S1_DELTA_DCD | \
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IOC4_SIO_IR_S1_DELTA_CTS | \
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IOC4_SIO_IR_S1_INT | \
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IOC4_SIO_IR_S1_TX_EXPLICIT)
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#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
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IOC4_SIO_IR_S2_RX_FULL | \
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IOC4_SIO_IR_S2_RX_HIGH | \
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IOC4_SIO_IR_S2_RX_TIMER | \
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IOC4_SIO_IR_S2_DELTA_DCD | \
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IOC4_SIO_IR_S2_DELTA_CTS | \
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IOC4_SIO_IR_S2_INT | \
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IOC4_SIO_IR_S2_TX_EXPLICIT)
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#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
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IOC4_SIO_IR_S3_RX_FULL | \
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IOC4_SIO_IR_S3_RX_HIGH | \
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IOC4_SIO_IR_S3_RX_TIMER | \
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IOC4_SIO_IR_S3_DELTA_DCD | \
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IOC4_SIO_IR_S3_DELTA_CTS | \
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IOC4_SIO_IR_S3_INT | \
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IOC4_SIO_IR_S3_TX_EXPLICIT)
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/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
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#define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
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#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
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#define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
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#define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
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#define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
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#define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
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#define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
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#define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
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#define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
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#define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
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#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
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IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
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/* Bitmasks for IOC4_SIO_CR */
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#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
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#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
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#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
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#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
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#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
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#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
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#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
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#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
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#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
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#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
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/* Defs for some of the generic I/O pins */
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#define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
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#define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
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#define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
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#define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
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#define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
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uart 0 mode select */
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#define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
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uart 1 mode select */
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#define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
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uart 2 mode select */
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#define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
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uart 3 mode select */
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/* Bitmasks for serial RX status byte */
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#define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
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#define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
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#define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
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#define IOC4_RXSB_BREAK 0x08 /* Break character */
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#define IOC4_RXSB_CTS 0x10 /* State of CTS */
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#define IOC4_RXSB_DCD 0x20 /* State of DCD */
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#define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
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#define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
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/* Bitmasks for serial TX control byte */
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#define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
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#define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
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#define IOC4_TXCB_VALID 0x40 /* Byte is valid */
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#define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
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#define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
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/* Bitmasks for IOC4_SBBR_L */
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#define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
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/* Bitmasks for IOC4_SSCR_<3:0> */
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#define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
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#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
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#define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
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#define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
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#define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
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#define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
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#define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
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#define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
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#define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
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#define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
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#define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
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/* All producer/comsumer pointers are the same bitfield */
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#define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
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#define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
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#define IOC4_PROD_CONS_PTR_OFF 3
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/* Bitmasks for IOC4_SRCIR_<3:0> */
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#define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
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/* Bitmasks for IOC4_SHADOW_<3:0> */
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#define IOC4_SHADOW_DR 0x00000001 /* Data ready */
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#define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
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#define IOC4_SHADOW_PE 0x00000004 /* Parity error */
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#define IOC4_SHADOW_FE 0x00000008 /* Framing error */
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#define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
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#define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
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#define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
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#define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
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#define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
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#define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
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#define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
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#define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
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#define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
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#define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
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#define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
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#define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
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#define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
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/* Bitmasks for IOC4_SRTR_<3:0> */
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#define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
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#define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
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#define IOC4_SRTR_CNT_VAL_SHIFT 16
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#define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
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/* Serial port register map used for DMA and PIO serial I/O */
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struct ioc4_serialregs {
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/* IOC4 UART register map */
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struct ioc4_uartregs {
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char iir; /* read only */
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char fcr; /* write only */
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char ier; /* DLAB == 0 */
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char dlm; /* DLAB == 1 */
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char rbr; /* read only, DLAB == 0 */
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char thr; /* write only, DLAB == 0 */
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char dll; /* DLAB == 1 */
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#define i4u_dll u1.dll
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#define i4u_ier u2.ier
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#define i4u_dlm u2.dlm
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#define i4u_fcr u3.fcr
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/* Serial port registers used for DMA serial I/O */
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struct ioc4_serialregs port_0;
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struct ioc4_serialregs port_1;
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struct ioc4_serialregs port_2;
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struct ioc4_serialregs port_3;
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struct ioc4_uartregs uart_0;
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struct ioc4_uartregs uart_1;
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struct ioc4_uartregs uart_2;
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struct ioc4_uartregs uart_3;
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/* UART clock speed */
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#define IOC4_SER_XIN_CLK_66 66666667
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#define IOC4_SER_XIN_CLK_33 33333333
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typedef void ioc4_intr_func_f(void *, uint32_t);
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typedef ioc4_intr_func_f *ioc4_intr_func_t;
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static unsigned int Num_of_ioc4_cards;
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/* defining this will get you LOTS of great debug info */
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//#define DEBUG_INTERRUPTS
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#define DPRINT_CONFIG(_x...) ;
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//#define DPRINT_CONFIG(_x...) printk _x
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/* number of characters left in xmit buffer before we ask for more */
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#define WAKEUP_CHARS 256
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/* number of characters we want to transmit to the lower level at a time */
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#define IOC4_MAX_CHARS 256
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#define IOC4_FIFO_CHARS 255
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/* Device name we're using */
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#define DEVICE_NAME_RS232 "ttyIOC"
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#define DEVICE_NAME_RS422 "ttyAIOC"
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#define DEVICE_MAJOR 204
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#define DEVICE_MINOR_RS232 50
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#define DEVICE_MINOR_RS422 84
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/* register offsets */
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#define IOC4_SERIAL_OFFSET 0x300
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/* flags for next_char_state */
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#define NCS_BREAK 0x1
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#define NCS_PARITY 0x2
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#define NCS_FRAMING 0x4
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#define NCS_OVERRUN 0x8
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/* cause we need SOME parameters ... */
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#define MIN_BAUD_SUPPORTED 1200
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#define MAX_BAUD_SUPPORTED 115200
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/* protocol types supported */
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#define PROTO_RS232 3
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#define PROTO_RS422 7
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/* Notification types */
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#define N_DATA_READY 0x01
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#define N_OUTPUT_LOWAT 0x02
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#define N_PARITY_ERROR 0x08
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#define N_FRAMING_ERROR 0x10
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#define N_OVERRUN_ERROR 0x20
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#define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
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N_PARITY_ERROR | N_FRAMING_ERROR | \
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N_OVERRUN_ERROR | N_DDCD | N_DCTS)
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#define N_ALL_OUTPUT N_OUTPUT_LOWAT
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#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
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#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
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N_PARITY_ERROR | N_FRAMING_ERROR | \
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N_OVERRUN_ERROR | N_DDCD | N_DCTS)
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#define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
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#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
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#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
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| UART_LCR_WLEN7 | UART_LCR_WLEN8)
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#define LCR_MASK_STOP_BITS (UART_LCR_STOP)
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#define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
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#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
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/* Default to 4k buffers */
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#ifdef IOC4_1K_BUFFERS
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#define RING_BUF_SIZE 1024
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#define IOC4_BUF_SIZE_BIT 0
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#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
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#define RING_BUF_SIZE 4096
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#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
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#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
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#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
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* This is the entry saved by the driver - one per card
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#define UART_PORT_MIN 0
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#define UART_PORT_RS232 UART_PORT_MIN
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#define UART_PORT_RS422 1
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#define UART_PORT_COUNT 2 /* one for each mode */
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struct ioc4_control {
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/* uart ports are allocated here - 1 for rs232, 1 for rs422 */
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struct uart_port icp_uart_port[UART_PORT_COUNT];
412
/* Handy reference material */
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struct ioc4_port *icp_port;
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} ic_port[IOC4_NUM_SERIAL_PORTS];
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struct ioc4_soft *ic_soft;
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* per-IOC4 data structure
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#define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
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struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
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struct ioc4_serial __iomem *is_ioc4_serial_addr;
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/* Each interrupt type has an entry in the array */
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struct ioc4_intr_type {
430
* Each in-use entry in this array contains at least
431
* one nonzero bit in sd_bits; no two entries in this
432
* array have overlapping sd_bits values.
434
struct ioc4_intr_info {
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ioc4_intr_func_f *sd_intr;
438
} is_intr_info[MAX_IOC4_INTR_ENTS];
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/* Number of entries active in the above array */
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atomic_t is_num_intrs;
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} is_intr_type[IOC4_NUM_INTR_TYPES];
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/* is_ir_lock must be held while
445
* modifying sio_ie values, so
446
* we can be sure that sio_ie is
447
* not changing when we read it
450
spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
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/* Local port info for each IOC4 serial ports */
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struct uart_port *ip_port; /* current active port ptr */
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/* Ptrs for all ports */
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struct uart_port *ip_all_ports[UART_PORT_COUNT];
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/* Back ptrs for this port */
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struct ioc4_control *ip_control;
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struct pci_dev *ip_pdev;
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struct ioc4_soft *ip_ioc4_soft;
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/* pci mem addresses */
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struct ioc4_misc_regs __iomem *ip_mem;
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struct ioc4_serial __iomem *ip_serial;
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struct ioc4_serialregs __iomem *ip_serial_regs;
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struct ioc4_uartregs __iomem *ip_uart_regs;
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/* Ring buffer page for this port */
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dma_addr_t ip_dma_ringbuf;
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/* vaddr of ring buffer */
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struct ring_buffer *ip_cpu_ringbuf;
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/* Rings for this port */
475
struct ring *ip_inring;
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struct ring *ip_outring;
478
/* Hook to port specific values */
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struct hooks *ip_hooks;
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/* Various rx/tx parameters */
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/* Copy of notification bits */
491
/* Shadow copies of various registers so we don't need to PIO
492
* read them constantly
494
uint32_t ip_ienb; /* Enabled interrupts */
498
int ip_pci_bus_speed;
499
unsigned char ip_flags;
502
/* tx low water mark. We need to notify the driver whenever tx is getting
503
* close to empty so it can refill the tx buffer and keep things going.
504
* Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
505
* have no trouble getting in more chars in time (I certainly hope so).
507
#define TX_LOWAT_LATENCY 1000
508
#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
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#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
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#define INPUT_HIGH 0x01
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#define LOWAT_WRITTEN 0x04
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#define READ_ABORTED 0x08
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#define PORT_ACTIVE 0x10
517
#define PORT_INACTIVE 0 /* This is the value when "off" */
520
/* Since each port has different register offsets and bitmasks
521
* for everything, we'll store those that we need in tables so we
522
* don't have to be constantly checking the port we are dealing with.
525
uint32_t intr_delta_dcd;
526
uint32_t intr_delta_cts;
528
uint32_t intr_rx_timer;
529
uint32_t intr_rx_high;
530
uint32_t intr_tx_explicit;
531
uint32_t intr_dma_error;
534
int rs422_select_pin;
537
static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
538
/* Values for port 0 */
540
IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
541
IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
542
IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
543
IOC4_OTHER_IR_S0_MEMERR,
544
(IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
545
IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
546
IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
547
IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
548
IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
551
/* Values for port 1 */
553
IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
554
IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
555
IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
556
IOC4_OTHER_IR_S1_MEMERR,
557
(IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
558
IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
559
IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
560
IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
561
IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
564
/* Values for port 2 */
566
IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
567
IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
568
IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
569
IOC4_OTHER_IR_S2_MEMERR,
570
(IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
571
IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
572
IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
573
IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
574
IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
577
/* Values for port 3 */
579
IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
580
IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
581
IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
582
IOC4_OTHER_IR_S3_MEMERR,
583
(IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
584
IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
585
IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
586
IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
587
IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
591
/* A ring buffer entry */
599
char data[4]; /* data bytes */
600
char sc[4]; /* status/control */
605
/* Test the valid bits in any of the 4 sc chars using "allsc" member */
606
#define RING_ANY_VALID \
607
((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
609
#define ring_sc u.s.sc
610
#define ring_data u.s.data
611
#define ring_allsc u.all.allsc
613
/* Number of entries per ring buffer. */
614
#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
616
/* An individual ring */
618
struct ring_entry entries[ENTRIES_PER_RING];
621
/* The whole enchilada */
623
struct ring TX_0_OR_2;
624
struct ring RX_0_OR_2;
625
struct ring TX_1_OR_3;
626
struct ring RX_1_OR_3;
629
/* Get a ring from a port struct */
630
#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
632
/* Infinite loop detection.
634
#define MAXITER 10000000
637
static void receive_chars(struct uart_port *);
638
static void handle_intr(void *arg, uint32_t sio_ir);
641
* port_is_active - determines if this port is currently active
642
* @port: ptr to soft struct for this port
643
* @uart_port: uart port to test for
645
static inline int port_is_active(struct ioc4_port *port,
646
struct uart_port *uart_port)
649
if ((port->ip_flags & PORT_ACTIVE)
650
&& (port->ip_port == uart_port))
658
* write_ireg - write the interrupt regs
659
* @ioc4_soft: ptr to soft struct for this port
660
* @val: value to write
661
* @which: which register
662
* @type: which ireg set
665
write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
667
struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
670
spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
673
case IOC4_SIO_INTR_TYPE:
676
writel(val, &mem->sio_ies.raw);
680
writel(val, &mem->sio_iec.raw);
685
case IOC4_OTHER_INTR_TYPE:
688
writel(val, &mem->other_ies.raw);
692
writel(val, &mem->other_iec.raw);
700
spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
704
* set_baud - Baud rate setting code
706
* @baud: baud rate to use
708
static int set_baud(struct ioc4_port *port, int baud)
713
unsigned short divisor;
714
struct ioc4_uartregs __iomem *uart;
716
divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
719
actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
721
diff = actual_baud - baud;
725
/* If we're within 1%, we've found a match */
726
if (diff * 100 > actual_baud)
729
uart = port->ip_uart_regs;
730
lcr = readb(&uart->i4u_lcr);
731
writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
732
writeb((unsigned char)divisor, &uart->i4u_dll);
733
writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
734
writeb(lcr, &uart->i4u_lcr);
740
* get_ioc4_port - given a uart port, return the control structure
742
* @set: set this port as current
744
static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
746
struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
747
struct ioc4_control *control = idd->idd_serial_data;
748
struct ioc4_port *port;
749
int port_num, port_type;
752
for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
754
port = control->ic_port[port_num].icp_port;
757
for (port_type = UART_PORT_MIN;
758
port_type < UART_PORT_COUNT;
760
if (the_port == port->ip_all_ports
764
port->ip_port = the_port;
774
/* The IOC4 hardware provides no atomic way to determine if interrupts
775
* are pending since two reads are required to do so. The handler must
776
* read the SIO_IR and the SIO_IES, and take the logical and of the
777
* two. When this value is zero, all interrupts have been serviced and
778
* the handler may return.
780
* This has the unfortunate "hole" that, if some other CPU or
781
* some other thread or some higher level interrupt manages to
782
* modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
783
* think we have observed SIO_IR&SIO_IE==0 when in fact this
784
* condition never really occurred.
786
* To solve this, we use a simple spinlock that must be held
787
* whenever modifying SIO_IE; holding this lock while observing
788
* both SIO_IR and SIO_IE guarantees that we do not falsely
789
* conclude that no enabled interrupts are pending.
792
static inline uint32_t
793
pending_intrs(struct ioc4_soft *soft, int type)
795
struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
799
BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
800
|| (type == IOC4_OTHER_INTR_TYPE)));
802
spin_lock_irqsave(&soft->is_ir_lock, flag);
805
case IOC4_SIO_INTR_TYPE:
806
intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
809
case IOC4_OTHER_INTR_TYPE:
810
intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
812
/* Don't process any ATA interrupte */
813
intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
819
spin_unlock_irqrestore(&soft->is_ir_lock, flag);
824
* port_init - Initialize the sio and ioc4 hardware for a given port
825
* called per port from attach...
826
* @port: port to initialize
828
static int inline port_init(struct ioc4_port *port)
831
struct hooks *hooks = port->ip_hooks;
832
struct ioc4_uartregs __iomem *uart;
834
/* Idle the IOC4 serial interface */
835
writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
837
/* Wait until any pending bus activity for this port has ceased */
839
sio_cr = readl(&port->ip_mem->sio_cr.raw);
840
while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
842
/* Finish reset sequence */
843
writel(0, &port->ip_serial_regs->sscr);
845
/* Once RESET is done, reload cached tx_prod and rx_cons values
846
* and set rings to empty by making prod == cons
848
port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
849
writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
850
port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
851
writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
853
/* Disable interrupts for this 16550 */
854
uart = port->ip_uart_regs;
855
writeb(0, &uart->i4u_lcr);
856
writeb(0, &uart->i4u_ier);
858
/* Set the default baud */
859
set_baud(port, port->ip_baud);
861
/* Set line control to 8 bits no parity */
862
writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
863
/* UART_LCR_STOP == 1 stop */
865
/* Enable the FIFOs */
866
writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
867
/* then reset 16550 FIFOs */
868
writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
871
/* Clear modem control register */
872
writeb(0, &uart->i4u_mcr);
874
/* Clear deltas in modem status register */
875
readb(&uart->i4u_msr);
877
/* Only do this once per port pair */
878
if (port->ip_hooks == &hooks_array[0]
879
|| port->ip_hooks == &hooks_array[2]) {
880
unsigned long ring_pci_addr;
881
uint32_t __iomem *sbbr_l;
882
uint32_t __iomem *sbbr_h;
884
if (port->ip_hooks == &hooks_array[0]) {
885
sbbr_l = &port->ip_serial->sbbr01_l;
886
sbbr_h = &port->ip_serial->sbbr01_h;
888
sbbr_l = &port->ip_serial->sbbr23_l;
889
sbbr_h = &port->ip_serial->sbbr23_h;
892
ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
893
DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
894
__func__, ring_pci_addr));
896
writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
897
writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
900
/* Set the receive timeout value to 10 msec */
901
writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
903
/* Set rx threshold, enable DMA */
904
/* Set high water mark at 3/4 of full ring */
905
port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
906
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
908
/* Disable and clear all serial related interrupt bits */
909
write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
910
IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
911
port->ip_ienb &= ~hooks->intr_clear;
912
writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
917
* handle_dma_error_intr - service any pending DMA error interrupts for the
918
* given port - 2nd level called via sd_intr
920
* @other_ir: ioc4regs
922
static void handle_dma_error_intr(void *arg, uint32_t other_ir)
924
struct ioc4_port *port = (struct ioc4_port *)arg;
925
struct hooks *hooks = port->ip_hooks;
928
spin_lock_irqsave(&port->ip_lock, flags);
930
/* ACK the interrupt */
931
writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
933
if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
935
"PCI error address is 0x%llx, "
936
"master is serial port %c %s\n",
937
(((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
939
| readl(&port->ip_mem->pci_err_addr_l.raw))
940
& IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
941
((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
942
IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
943
(readl(&port->ip_mem->pci_err_addr_l.raw)
944
& IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
947
if (readl(&port->ip_mem->pci_err_addr_l.raw)
948
& IOC4_PCI_ERR_ADDR_MUL_ERR) {
950
"Multiple errors occurred\n");
953
spin_unlock_irqrestore(&port->ip_lock, flags);
955
/* Re-enable DMA error interrupts */
956
write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
957
IOC4_OTHER_INTR_TYPE);
961
* intr_connect - interrupt connect function
962
* @soft: soft struct for this card
963
* @type: interrupt type
964
* @intrbits: bit pattern to set
965
* @intr: handler function
969
intr_connect(struct ioc4_soft *soft, int type,
970
uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
973
struct ioc4_intr_info *intr_ptr;
975
BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
976
|| (type == IOC4_OTHER_INTR_TYPE)));
978
i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
979
BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
981
/* Save off the lower level interrupt handler */
982
intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
983
intr_ptr->sd_bits = intrbits;
984
intr_ptr->sd_intr = intr;
985
intr_ptr->sd_info = info;
989
* ioc4_intr - Top level IOC4 interrupt handler.
994
static irqreturn_t ioc4_intr(int irq, void *arg)
996
struct ioc4_soft *soft;
997
uint32_t this_ir, this_mir;
998
int xx, num_intrs = 0;
1001
struct ioc4_intr_info *intr_info;
1004
for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1005
num_intrs = (int)atomic_read(
1006
&soft->is_intr_type[intr_type].is_num_intrs);
1008
this_mir = this_ir = pending_intrs(soft, intr_type);
1010
/* Farm out the interrupt to the various drivers depending on
1011
* which interrupt bits are set.
1013
for (xx = 0; xx < num_intrs; xx++) {
1014
intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1015
if ((this_mir = this_ir & intr_info->sd_bits)) {
1016
/* Disable owned interrupts, call handler */
1018
write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1020
intr_info->sd_intr(intr_info->sd_info, this_mir);
1021
this_ir &= ~this_mir;
1025
#ifdef DEBUG_INTERRUPTS
1027
struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1030
spin_lock_irqsave(&soft->is_ir_lock, flag);
1031
printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1032
"other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1034
(void *)mem, readl(&mem->sio_ir.raw),
1035
readl(&mem->sio_ies.raw),
1036
readl(&mem->other_ir.raw),
1037
readl(&mem->other_ies.raw),
1038
IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1039
spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1042
return handled ? IRQ_HANDLED : IRQ_NONE;
1046
* ioc4_attach_local - Device initialization.
1047
* Called at *_attach() time for each
1048
* IOC4 with serial ports in the system.
1049
* @idd: Master module data for this IOC4
1051
static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1053
struct ioc4_port *port;
1054
struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1056
uint16_t ioc4_revid_min = 62;
1057
uint16_t ioc4_revid;
1058
struct pci_dev *pdev = idd->idd_pdev;
1059
struct ioc4_control* control = idd->idd_serial_data;
1060
struct ioc4_soft *soft = control->ic_soft;
1061
void __iomem *ioc4_misc = idd->idd_misc_regs;
1062
void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1064
/* IOC4 firmware must be at least rev 62 */
1065
pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1067
printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1068
if (ioc4_revid < ioc4_revid_min) {
1070
"IOC4 serial not supported on firmware rev %d, "
1071
"please upgrade to rev %d or higher\n",
1072
ioc4_revid, ioc4_revid_min);
1075
BUG_ON(ioc4_misc == NULL);
1076
BUG_ON(ioc4_serial == NULL);
1078
/* Create port structures for each port */
1079
for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1081
port = kzalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1084
"IOC4 serial memory not available for port\n");
1087
spin_lock_init(&port->ip_lock);
1089
/* we need to remember the previous ones, to point back to
1090
* them farther down - setting up the ring buffers.
1092
ports[port_number] = port;
1094
/* Allocate buffers and jumpstart the hardware. */
1095
control->ic_port[port_number].icp_port = port;
1096
port->ip_ioc4_soft = soft;
1097
port->ip_pdev = pdev;
1099
/* Use baud rate calculations based on detected PCI
1100
* bus speed. Simply test whether the PCI clock is
1101
* running closer to 66MHz or 33MHz.
1103
if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1104
port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1106
port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1108
port->ip_baud = 9600;
1109
port->ip_control = control;
1110
port->ip_mem = ioc4_misc;
1111
port->ip_serial = ioc4_serial;
1113
/* point to the right hook */
1114
port->ip_hooks = &hooks_array[port_number];
1116
/* Get direct hooks to the serial regs and uart regs
1119
switch (port_number) {
1121
port->ip_serial_regs = &(port->ip_serial->port_0);
1122
port->ip_uart_regs = &(port->ip_serial->uart_0);
1125
port->ip_serial_regs = &(port->ip_serial->port_1);
1126
port->ip_uart_regs = &(port->ip_serial->uart_1);
1129
port->ip_serial_regs = &(port->ip_serial->port_2);
1130
port->ip_uart_regs = &(port->ip_serial->uart_2);
1134
port->ip_serial_regs = &(port->ip_serial->port_3);
1135
port->ip_uart_regs = &(port->ip_serial->uart_3);
1139
/* ring buffers are 1 to a pair of ports */
1140
if (port_number && (port_number & 1)) {
1141
/* odd use the evens buffer */
1142
port->ip_dma_ringbuf =
1143
ports[port_number - 1]->ip_dma_ringbuf;
1144
port->ip_cpu_ringbuf =
1145
ports[port_number - 1]->ip_cpu_ringbuf;
1146
port->ip_inring = RING(port, RX_1_OR_3);
1147
port->ip_outring = RING(port, TX_1_OR_3);
1150
if (port->ip_dma_ringbuf == 0) {
1151
port->ip_cpu_ringbuf = pci_alloc_consistent
1152
(pdev, TOTAL_RING_BUF_SIZE,
1153
&port->ip_dma_ringbuf);
1156
BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1157
(TOTAL_RING_BUF_SIZE - 1)) == 0));
1158
DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1159
"ip_dma_ringbuf 0x%p\n",
1161
(void *)port->ip_cpu_ringbuf,
1162
(void *)port->ip_dma_ringbuf));
1163
port->ip_inring = RING(port, RX_0_OR_2);
1164
port->ip_outring = RING(port, TX_0_OR_2);
1166
DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1168
port_number, (void *)port, (void *)control));
1169
DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1170
(void *)port->ip_serial_regs,
1171
(void *)port->ip_uart_regs));
1173
/* Initialize the hardware for IOC4 */
1176
DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1179
port_number, (void *)port,
1180
(void *)port->ip_inring,
1181
(void *)port->ip_outring));
1183
/* Attach interrupt handlers */
1184
intr_connect(soft, IOC4_SIO_INTR_TYPE,
1185
GET_SIO_IR(port_number),
1188
intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1189
GET_OTHER_IR(port_number),
1190
handle_dma_error_intr, port);
1196
* enable_intrs - enable interrupts
1197
* @port: port to enable
1198
* @mask: mask to use
1200
static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1202
struct hooks *hooks = port->ip_hooks;
1204
if ((port->ip_ienb & mask) != mask) {
1205
write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1206
IOC4_SIO_INTR_TYPE);
1207
port->ip_ienb |= mask;
1211
write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1212
IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1216
* local_open - local open a port
1217
* @port: port to open
1219
static inline int local_open(struct ioc4_port *port)
1223
port->ip_flags = PORT_ACTIVE;
1225
/* Pause the DMA interface if necessary */
1226
if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1227
writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1228
&port->ip_serial_regs->sscr);
1229
while((readl(&port->ip_serial_regs-> sscr)
1230
& IOC4_SSCR_PAUSE_STATE) == 0) {
1232
if (spiniter > MAXITER) {
1233
port->ip_flags = PORT_INACTIVE;
1239
/* Reset the input fifo. If the uart received chars while the port
1240
* was closed and DMA is not enabled, the uart may have a bunch of
1241
* chars hanging around in its rx fifo which will not be discarded
1242
* by rclr in the upper layer. We must get rid of them here.
1244
writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1245
&port->ip_uart_regs->i4u_fcr);
1247
writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1248
/* UART_LCR_STOP == 1 stop */
1250
/* Re-enable DMA, set default threshold to intr whenever there is
1253
port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1254
port->ip_sscr |= 1; /* default threshold */
1256
/* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1257
* flag if it was set above
1259
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1260
port->ip_tx_lowat = 1;
1265
* set_rx_timeout - Set rx timeout and threshold values.
1266
* @port: port to use
1267
* @timeout: timeout value in ticks
1269
static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1273
port->ip_rx_timeout = timeout;
1275
/* Timeout is in ticks. Let's figure out how many chars we
1276
* can receive at the current baud rate in that interval
1277
* and set the rx threshold to that amount. There are 4 chars
1278
* per ring entry, so we'll divide the number of chars that will
1279
* arrive in timeout by 4.
1280
* So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1282
threshold = timeout * port->ip_baud / 4000;
1284
threshold = 1; /* otherwise we'll intr all the time! */
1286
if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1289
port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1290
port->ip_sscr |= threshold;
1292
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1294
/* Now set the rx timeout to the given value
1295
* again timeout * IOC4_SRTR_HZ / HZ
1297
timeout = timeout * IOC4_SRTR_HZ / 100;
1298
if (timeout > IOC4_SRTR_CNT)
1299
timeout = IOC4_SRTR_CNT;
1301
writel(timeout, &port->ip_serial_regs->srtr);
1306
* config_port - config the hardware
1307
* @port: port to config
1308
* @baud: baud rate for the port
1309
* @byte_size: data size
1310
* @stop_bits: number of stop bits
1311
* @parenb: parity enable ?
1312
* @parodd: odd parity ?
1315
config_port(struct ioc4_port *port,
1316
int baud, int byte_size, int stop_bits, int parenb, int parodd)
1321
DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1322
__func__, baud, byte_size, stop_bits, parenb, parodd));
1324
if (set_baud(port, baud))
1327
switch (byte_size) {
1329
sizebits = UART_LCR_WLEN5;
1332
sizebits = UART_LCR_WLEN6;
1335
sizebits = UART_LCR_WLEN7;
1338
sizebits = UART_LCR_WLEN8;
1344
/* Pause the DMA interface if necessary */
1345
if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1346
writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1347
&port->ip_serial_regs->sscr);
1348
while((readl(&port->ip_serial_regs->sscr)
1349
& IOC4_SSCR_PAUSE_STATE) == 0) {
1351
if (spiniter > MAXITER)
1356
/* Clear relevant fields in lcr */
1357
lcr = readb(&port->ip_uart_regs->i4u_lcr);
1358
lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1359
UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1361
/* Set byte size in lcr */
1366
lcr |= UART_LCR_PARITY;
1368
lcr |= UART_LCR_EPAR;
1373
lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1375
writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1377
/* Re-enable the DMA interface if necessary */
1378
if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1379
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1381
port->ip_baud = baud;
1383
/* When we get within this number of ring entries of filling the
1384
* entire ring on tx, place an EXPLICIT intr to generate a lowat
1385
* notification when output has drained.
1387
port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1388
if (port->ip_tx_lowat == 0)
1389
port->ip_tx_lowat = 1;
1391
set_rx_timeout(port, 2);
1397
* do_write - Write bytes to the port. Returns the number of bytes
1398
* actually written. Called from transmit_chars
1399
* @port: port to use
1400
* @buf: the stuff to write
1401
* @len: how many bytes in 'buf'
1403
static inline int do_write(struct ioc4_port *port, char *buf, int len)
1405
int prod_ptr, cons_ptr, total = 0;
1406
struct ring *outring;
1407
struct ring_entry *entry;
1408
struct hooks *hooks = port->ip_hooks;
1410
BUG_ON(!(len >= 0));
1412
prod_ptr = port->ip_tx_prod;
1413
cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1414
outring = port->ip_outring;
1416
/* Maintain a 1-entry red-zone. The ring buffer is full when
1417
* (cons - prod) % ring_size is 1. Rather than do this subtraction
1418
* in the body of the loop, I'll do it now.
1420
cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1422
/* Stuff the bytes into the output */
1423
while ((prod_ptr != cons_ptr) && (len > 0)) {
1426
/* Get 4 bytes (one ring entry) at a time */
1427
entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1429
/* Invalidate all entries */
1430
entry->ring_allsc = 0;
1432
/* Copy in some bytes */
1433
for (xx = 0; (xx < 4) && (len > 0); xx++) {
1434
entry->ring_data[xx] = *buf++;
1435
entry->ring_sc[xx] = IOC4_TXCB_VALID;
1440
/* If we are within some small threshold of filling up the
1441
* entire ring buffer, we must place an EXPLICIT intr here
1442
* to generate a lowat interrupt in case we subsequently
1443
* really do fill up the ring and the caller goes to sleep.
1444
* No need to place more than one though.
1446
if (!(port->ip_flags & LOWAT_WRITTEN) &&
1447
((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1448
<= port->ip_tx_lowat
1449
* (int)sizeof(struct ring_entry)) {
1450
port->ip_flags |= LOWAT_WRITTEN;
1451
entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1454
/* Go on to next entry */
1455
prod_ptr += sizeof(struct ring_entry);
1456
prod_ptr &= PROD_CONS_MASK;
1459
/* If we sent something, start DMA if necessary */
1460
if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1461
port->ip_sscr |= IOC4_SSCR_DMA_EN;
1462
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1465
/* Store the new producer pointer. If tx is disabled, we stuff the
1466
* data into the ring buffer, but we don't actually start tx.
1468
if (!uart_tx_stopped(port->ip_port)) {
1469
writel(prod_ptr, &port->ip_serial_regs->stpir);
1471
/* If we are now transmitting, enable tx_mt interrupt so we
1472
* can disable DMA if necessary when the tx finishes.
1475
enable_intrs(port, hooks->intr_tx_mt);
1477
port->ip_tx_prod = prod_ptr;
1482
* disable_intrs - disable interrupts
1483
* @port: port to enable
1484
* @mask: mask to use
1486
static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1488
struct hooks *hooks = port->ip_hooks;
1490
if (port->ip_ienb & mask) {
1491
write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1492
IOC4_SIO_INTR_TYPE);
1493
port->ip_ienb &= ~mask;
1497
write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1498
IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1502
* set_notification - Modify event notification
1503
* @port: port to use
1504
* @mask: events mask
1507
static int set_notification(struct ioc4_port *port, int mask, int set_on)
1509
struct hooks *hooks = port->ip_hooks;
1510
uint32_t intrbits, sscrbits;
1514
intrbits = sscrbits = 0;
1516
if (mask & N_DATA_READY)
1517
intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1518
if (mask & N_OUTPUT_LOWAT)
1519
intrbits |= hooks->intr_tx_explicit;
1520
if (mask & N_DDCD) {
1521
intrbits |= hooks->intr_delta_dcd;
1522
sscrbits |= IOC4_SSCR_RX_RING_DCD;
1525
intrbits |= hooks->intr_delta_cts;
1528
enable_intrs(port, intrbits);
1529
port->ip_notify |= mask;
1530
port->ip_sscr |= sscrbits;
1532
disable_intrs(port, intrbits);
1533
port->ip_notify &= ~mask;
1534
port->ip_sscr &= ~sscrbits;
1537
/* We require DMA if either DATA_READY or DDCD notification is
1538
* currently requested. If neither of these is requested and
1539
* there is currently no tx in progress, DMA may be disabled.
1541
if (port->ip_notify & (N_DATA_READY | N_DDCD))
1542
port->ip_sscr |= IOC4_SSCR_DMA_EN;
1543
else if (!(port->ip_ienb & hooks->intr_tx_mt))
1544
port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1546
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1551
* set_mcr - set the master control reg
1552
* @the_port: port to use
1554
* @mask2: shadow mask
1556
static inline int set_mcr(struct uart_port *the_port,
1557
int mask1, int mask2)
1559
struct ioc4_port *port = get_ioc4_port(the_port, 0);
1567
/* Pause the DMA interface if necessary */
1568
if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1569
writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1570
&port->ip_serial_regs->sscr);
1571
while ((readl(&port->ip_serial_regs->sscr)
1572
& IOC4_SSCR_PAUSE_STATE) == 0) {
1574
if (spiniter > MAXITER)
1578
shadow = readl(&port->ip_serial_regs->shadow);
1579
mcr = (shadow & 0xff000000) >> 24;
1585
writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1586
writel(shadow, &port->ip_serial_regs->shadow);
1588
/* Re-enable the DMA interface if necessary */
1589
if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1590
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1596
* ioc4_set_proto - set the protocol for the port
1597
* @port: port to use
1598
* @proto: protocol to use
1600
static int ioc4_set_proto(struct ioc4_port *port, int proto)
1602
struct hooks *hooks = port->ip_hooks;
1606
/* Clear the appropriate GIO pin */
1607
writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1611
/* Set the appropriate GIO pin */
1612
writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1622
* transmit_chars - upper level write, called with ip_lock
1623
* @the_port: port to write
1625
static void transmit_chars(struct uart_port *the_port)
1627
int xmit_count, tail, head;
1630
struct tty_struct *tty;
1631
struct ioc4_port *port = get_ioc4_port(the_port, 0);
1632
struct uart_state *state;
1639
state = the_port->state;
1640
tty = state->port.tty;
1642
if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
1643
/* Nothing to do or hw stopped */
1644
set_notification(port, N_ALL_OUTPUT, 0);
1648
head = state->xmit.head;
1649
tail = state->xmit.tail;
1650
start = (char *)&state->xmit.buf[tail];
1652
/* write out all the data or until the end of the buffer */
1653
xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1654
if (xmit_count > 0) {
1655
result = do_write(port, start, xmit_count);
1658
xmit_count -= result;
1659
the_port->icount.tx += result;
1660
/* advance the pointers */
1662
tail &= UART_XMIT_SIZE - 1;
1663
state->xmit.tail = tail;
1664
start = (char *)&state->xmit.buf[tail];
1667
if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
1668
uart_write_wakeup(the_port);
1670
if (uart_circ_empty(&state->xmit)) {
1671
set_notification(port, N_OUTPUT_LOWAT, 0);
1673
set_notification(port, N_OUTPUT_LOWAT, 1);
1678
* ioc4_change_speed - change the speed of the port
1679
* @the_port: port to change
1680
* @new_termios: new termios settings
1681
* @old_termios: old termios settings
1684
ioc4_change_speed(struct uart_port *the_port,
1685
struct ktermios *new_termios, struct ktermios *old_termios)
1687
struct ioc4_port *port = get_ioc4_port(the_port, 0);
1689
unsigned cflag, iflag;
1690
int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1691
struct uart_state *state = the_port->state;
1693
cflag = new_termios->c_cflag;
1694
iflag = new_termios->c_iflag;
1696
switch (cflag & CSIZE) {
1714
/* cuz we always need a default ... */
1719
if (cflag & CSTOPB) {
1723
if (cflag & PARENB) {
1725
new_parity_enable = 1;
1729
baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1730
MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1731
DPRINT_CONFIG(("%s: returned baud %d\n", __func__, baud));
1733
/* default is 9600 */
1737
if (!the_port->fifosize)
1738
the_port->fifosize = IOC4_FIFO_CHARS;
1739
the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1740
the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1742
the_port->ignore_status_mask = N_ALL_INPUT;
1744
state->port.tty->low_latency = 1;
1747
the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1749
if (iflag & IGNBRK) {
1750
the_port->ignore_status_mask &= ~N_BREAK;
1752
the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1754
if (!(cflag & CREAD)) {
1755
/* ignore everything */
1756
the_port->ignore_status_mask &= ~N_DATA_READY;
1759
if (cflag & CRTSCTS) {
1760
port->ip_sscr |= IOC4_SSCR_HFC_EN;
1763
port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1765
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1767
/* Set the configuration and proper notification call */
1768
DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1769
"config_port(baud %d data %d stop %d p enable %d parity %d),"
1770
" notification 0x%x\n",
1771
__func__, (void *)port, cflag, baud, new_data, new_stop,
1772
new_parity_enable, new_parity, the_port->ignore_status_mask));
1774
if ((config_port(port, baud, /* baud */
1775
new_data, /* byte size */
1776
new_stop, /* stop bits */
1777
new_parity_enable, /* set parity */
1778
new_parity)) >= 0) { /* parity 1==odd */
1779
set_notification(port, the_port->ignore_status_mask, 1);
1784
* ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1785
* @the_port: Port to operate on
1787
static inline int ic4_startup_local(struct uart_port *the_port)
1789
struct ioc4_port *port;
1790
struct uart_state *state;
1795
port = get_ioc4_port(the_port, 0);
1799
state = the_port->state;
1803
/* set the protocol - mapbase has the port type */
1804
ioc4_set_proto(port, the_port->mapbase);
1806
/* set the speed of the serial port */
1807
ioc4_change_speed(the_port, state->port.tty->termios,
1808
(struct ktermios *)0);
1814
* ioc4_cb_output_lowat - called when the output low water mark is hit
1815
* @the_port: port to output
1817
static void ioc4_cb_output_lowat(struct uart_port *the_port)
1819
unsigned long pflags;
1821
/* ip_lock is set on the call here */
1823
spin_lock_irqsave(&the_port->lock, pflags);
1824
transmit_chars(the_port);
1825
spin_unlock_irqrestore(&the_port->lock, pflags);
1830
* handle_intr - service any interrupts for the given port - 2nd level
1831
* called via sd_intr
1835
static void handle_intr(void *arg, uint32_t sio_ir)
1837
struct ioc4_port *port = (struct ioc4_port *)arg;
1838
struct hooks *hooks = port->ip_hooks;
1839
unsigned int rx_high_rd_aborted = 0;
1840
unsigned long flags;
1841
struct uart_port *the_port;
1844
/* Possible race condition here: The tx_mt interrupt bit may be
1845
* cleared without the intervention of the interrupt handler,
1846
* e.g. by a write. If the top level interrupt handler reads a
1847
* tx_mt, then some other processor does a write, starting up
1848
* output, then we come in here, see the tx_mt and stop DMA, the
1849
* output started by the other processor will hang. Thus we can
1850
* only rely on tx_mt being legitimate if it is read while the
1851
* port lock is held. Therefore this bit must be ignored in the
1852
* passed in interrupt mask which was read by the top level
1853
* interrupt handler since the port lock was not held at the time
1854
* it was read. We can only rely on this bit being accurate if it
1855
* is read while the port lock is held. So we'll clear it for now,
1856
* and reload it later once we have the port lock.
1858
sio_ir &= ~(hooks->intr_tx_mt);
1860
spin_lock_irqsave(&port->ip_lock, flags);
1862
loop_counter = MAXITER; /* to avoid hangs */
1867
if ( loop_counter-- <= 0 ) {
1868
printk(KERN_WARNING "IOC4 serial: "
1869
"possible hang condition/"
1870
"port stuck on interrupt.\n");
1874
/* Handle a DCD change */
1875
if (sio_ir & hooks->intr_delta_dcd) {
1876
/* ACK the interrupt */
1877
writel(hooks->intr_delta_dcd,
1878
&port->ip_mem->sio_ir.raw);
1880
shadow = readl(&port->ip_serial_regs->shadow);
1882
if ((port->ip_notify & N_DDCD)
1883
&& (shadow & IOC4_SHADOW_DCD)
1884
&& (port->ip_port)) {
1885
the_port = port->ip_port;
1886
the_port->icount.dcd = 1;
1887
wake_up_interruptible
1888
(&the_port->state->port.delta_msr_wait);
1889
} else if ((port->ip_notify & N_DDCD)
1890
&& !(shadow & IOC4_SHADOW_DCD)) {
1891
/* Flag delta DCD/no DCD */
1892
port->ip_flags |= DCD_ON;
1896
/* Handle a CTS change */
1897
if (sio_ir & hooks->intr_delta_cts) {
1898
/* ACK the interrupt */
1899
writel(hooks->intr_delta_cts,
1900
&port->ip_mem->sio_ir.raw);
1902
shadow = readl(&port->ip_serial_regs->shadow);
1904
if ((port->ip_notify & N_DCTS)
1905
&& (port->ip_port)) {
1906
the_port = port->ip_port;
1907
the_port->icount.cts =
1908
(shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1909
wake_up_interruptible
1910
(&the_port->state->port.delta_msr_wait);
1914
/* rx timeout interrupt. Must be some data available. Put this
1915
* before the check for rx_high since servicing this condition
1916
* may cause that condition to clear.
1918
if (sio_ir & hooks->intr_rx_timer) {
1919
/* ACK the interrupt */
1920
writel(hooks->intr_rx_timer,
1921
&port->ip_mem->sio_ir.raw);
1923
if ((port->ip_notify & N_DATA_READY)
1924
&& (port->ip_port)) {
1925
/* ip_lock is set on call here */
1926
receive_chars(port->ip_port);
1930
/* rx high interrupt. Must be after rx_timer. */
1931
else if (sio_ir & hooks->intr_rx_high) {
1932
/* Data available, notify upper layer */
1933
if ((port->ip_notify & N_DATA_READY)
1935
/* ip_lock is set on call here */
1936
receive_chars(port->ip_port);
1939
/* We can't ACK this interrupt. If receive_chars didn't
1940
* cause the condition to clear, we'll have to disable
1941
* the interrupt until the data is drained.
1942
* If the read was aborted, don't disable the interrupt
1943
* as this may cause us to hang indefinitely. An
1944
* aborted read generally means that this interrupt
1945
* hasn't been delivered to the cpu yet anyway, even
1946
* though we see it as asserted when we read the sio_ir.
1948
if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1949
if ((port->ip_flags & READ_ABORTED) == 0) {
1950
port->ip_ienb &= ~hooks->intr_rx_high;
1951
port->ip_flags |= INPUT_HIGH;
1953
rx_high_rd_aborted++;
1958
/* We got a low water interrupt: notify upper layer to
1959
* send more data. Must come before tx_mt since servicing
1960
* this condition may cause that condition to clear.
1962
if (sio_ir & hooks->intr_tx_explicit) {
1963
port->ip_flags &= ~LOWAT_WRITTEN;
1965
/* ACK the interrupt */
1966
writel(hooks->intr_tx_explicit,
1967
&port->ip_mem->sio_ir.raw);
1969
if (port->ip_notify & N_OUTPUT_LOWAT)
1970
ioc4_cb_output_lowat(port->ip_port);
1973
/* Handle tx_mt. Must come after tx_explicit. */
1974
else if (sio_ir & hooks->intr_tx_mt) {
1975
/* If we are expecting a lowat notification
1976
* and we get to this point it probably means that for
1977
* some reason the tx_explicit didn't work as expected
1978
* (that can legitimately happen if the output buffer is
1979
* filled up in just the right way).
1980
* So send the notification now.
1982
if (port->ip_notify & N_OUTPUT_LOWAT) {
1983
ioc4_cb_output_lowat(port->ip_port);
1985
/* We need to reload the sio_ir since the lowat
1986
* call may have caused another write to occur,
1987
* clearing the tx_mt condition.
1989
sio_ir = PENDING(port);
1992
/* If the tx_mt condition still persists even after the
1993
* lowat call, we've got some work to do.
1995
if (sio_ir & hooks->intr_tx_mt) {
1997
/* If we are not currently expecting DMA input,
1998
* and the transmitter has just gone idle,
1999
* there is no longer any reason for DMA, so
2002
if (!(port->ip_notify
2003
& (N_DATA_READY | N_DDCD))) {
2004
BUG_ON(!(port->ip_sscr
2005
& IOC4_SSCR_DMA_EN));
2006
port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2007
writel(port->ip_sscr,
2008
&port->ip_serial_regs->sscr);
2011
/* Prevent infinite tx_mt interrupt */
2012
port->ip_ienb &= ~hooks->intr_tx_mt;
2015
sio_ir = PENDING(port);
2017
/* if the read was aborted and only hooks->intr_rx_high,
2018
* clear hooks->intr_rx_high, so we do not loop forever.
2021
if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2022
sio_ir &= ~hooks->intr_rx_high;
2024
} while (sio_ir & hooks->intr_all);
2026
spin_unlock_irqrestore(&port->ip_lock, flags);
2028
/* Re-enable interrupts before returning from interrupt handler.
2029
* Getting interrupted here is okay. It'll just v() our semaphore, and
2030
* we'll come through the loop again.
2033
write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2034
IOC4_SIO_INTR_TYPE);
2038
* ioc4_cb_post_ncs - called for some basic errors
2039
* @port: port to use
2042
static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2044
struct uart_icount *icount;
2046
icount = &the_port->icount;
2048
if (ncs & NCS_BREAK)
2050
if (ncs & NCS_FRAMING)
2052
if (ncs & NCS_OVERRUN)
2054
if (ncs & NCS_PARITY)
2059
* do_read - Read in bytes from the port. Return the number of bytes
2061
* @the_port: port to use
2062
* @buf: place to put the stuff we read
2063
* @len: how big 'buf' is
2066
static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2069
int prod_ptr, cons_ptr, total;
2070
struct ioc4_port *port = get_ioc4_port(the_port, 0);
2071
struct ring *inring;
2072
struct ring_entry *entry;
2073
struct hooks *hooks = port->ip_hooks;
2078
BUG_ON(!(len >= 0));
2081
/* There is a nasty timing issue in the IOC4. When the rx_timer
2082
* expires or the rx_high condition arises, we take an interrupt.
2083
* At some point while servicing the interrupt, we read bytes from
2084
* the ring buffer and re-arm the rx_timer. However the rx_timer is
2085
* not started until the first byte is received *after* it is armed,
2086
* and any bytes pending in the rx construction buffers are not drained
2087
* to memory until either there are 4 bytes available or the rx_timer
2088
* expires. This leads to a potential situation where data is left
2089
* in the construction buffers forever - 1 to 3 bytes were received
2090
* after the interrupt was generated but before the rx_timer was
2091
* re-armed. At that point as long as no subsequent bytes are received
2092
* the timer will never be started and the bytes will remain in the
2093
* construction buffer forever. The solution is to execute a DRAIN
2094
* command after rearming the timer. This way any bytes received before
2095
* the DRAIN will be drained to memory, and any bytes received after
2096
* the DRAIN will start the TIMER and be drained when it expires.
2097
* Luckily, this only needs to be done when the DMA buffer is empty
2098
* since there is no requirement that this function return all
2099
* available data as long as it returns some.
2101
/* Re-arm the timer */
2102
writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2104
prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2105
cons_ptr = port->ip_rx_cons;
2107
if (prod_ptr == cons_ptr) {
2110
/* Input buffer appears empty, do a flush. */
2112
/* DMA must be enabled for this to work. */
2113
if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2114
port->ip_sscr |= IOC4_SSCR_DMA_EN;
2118
/* Potential race condition: we must reload the srpir after
2119
* issuing the drain command, otherwise we could think the rx
2120
* buffer is empty, then take a very long interrupt, and when
2121
* we come back it's full and we wait forever for the drain to
2124
writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2125
&port->ip_serial_regs->sscr);
2126
prod_ptr = readl(&port->ip_serial_regs->srpir)
2129
/* We must not wait for the DRAIN to complete unless there are
2130
* at least 8 bytes (2 ring entries) available to receive the
2131
* data otherwise the DRAIN will never complete and we'll
2133
* In fact, to make things easier, I'll just ignore the flush if
2134
* there is any data at all now available.
2136
if (prod_ptr == cons_ptr) {
2138
while (readl(&port->ip_serial_regs->sscr) &
2139
IOC4_SSCR_RX_DRAIN) {
2141
if (loop_counter > MAXITER)
2145
/* SIGH. We have to reload the prod_ptr *again* since
2146
* the drain may have caused it to change
2148
prod_ptr = readl(&port->ip_serial_regs->srpir)
2152
port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2153
writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2156
inring = port->ip_inring;
2157
port->ip_flags &= ~READ_ABORTED;
2160
loop_counter = 0xfffff; /* to avoid hangs */
2162
/* Grab bytes from the hardware */
2163
while ((prod_ptr != cons_ptr) && (len > 0)) {
2164
entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2166
if ( loop_counter-- <= 0 ) {
2167
printk(KERN_WARNING "IOC4 serial: "
2168
"possible hang condition/"
2169
"port stuck on read.\n");
2173
/* According to the producer pointer, this ring entry
2174
* must contain some data. But if the PIO happened faster
2175
* than the DMA, the data may not be available yet, so let's
2176
* wait until it arrives.
2178
if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2179
/* Indicate the read is aborted so we don't disable
2180
* the interrupt thinking that the consumer is
2183
port->ip_flags |= READ_ABORTED;
2188
/* Load the bytes/status out of the ring entry */
2189
for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2190
sc = &(entry->ring_sc[byte_num]);
2192
/* Check for change in modem state or overrun */
2193
if ((*sc & IOC4_RXSB_MODEM_VALID)
2194
&& (port->ip_notify & N_DDCD)) {
2195
/* Notify upper layer if DCD dropped */
2197
if ((port->ip_flags & DCD_ON)
2198
&& !(*sc & IOC4_RXSB_DCD)) {
2200
/* If we have already copied some data,
2201
* return it. We'll pick up the carrier
2202
* drop on the next pass. That way we
2203
* don't throw away the data that has
2204
* already been copied back to
2205
* the caller's buffer.
2211
port->ip_flags &= ~DCD_ON;
2213
/* Turn off this notification so the
2214
* carrier drop protocol won't see it
2215
* again when it does a read.
2217
*sc &= ~IOC4_RXSB_MODEM_VALID;
2219
/* To keep things consistent, we need
2220
* to update the consumer pointer so
2221
* the next reader won't come in and
2222
* try to read the same ring entries
2223
* again. This must be done here before
2227
if ((entry->ring_allsc & RING_ANY_VALID)
2229
cons_ptr += (int)sizeof
2230
(struct ring_entry);
2231
cons_ptr &= PROD_CONS_MASK;
2234
&port->ip_serial_regs->srcir);
2235
port->ip_rx_cons = cons_ptr;
2237
/* Notify upper layer of carrier drop */
2238
if ((port->ip_notify & N_DDCD)
2240
the_port->icount.dcd = 0;
2241
wake_up_interruptible
2243
port.delta_msr_wait);
2246
/* If we had any data to return, we
2247
* would have returned it above.
2252
if (*sc & IOC4_RXSB_MODEM_VALID) {
2253
/* Notify that an input overrun occurred */
2254
if ((*sc & IOC4_RXSB_OVERRUN)
2255
&& (port->ip_notify & N_OVERRUN_ERROR)) {
2256
ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2258
/* Don't look at this byte again */
2259
*sc &= ~IOC4_RXSB_MODEM_VALID;
2262
/* Check for valid data or RX errors */
2263
if ((*sc & IOC4_RXSB_DATA_VALID) &&
2264
((*sc & (IOC4_RXSB_PAR_ERR
2265
| IOC4_RXSB_FRAME_ERR
2267
&& (port->ip_notify & (N_PARITY_ERROR
2270
/* There is an error condition on the next byte.
2271
* If we have already transferred some bytes,
2272
* we'll stop here. Otherwise if this is the
2273
* first byte to be read, we'll just transfer
2274
* it alone after notifying the
2275
* upper layer of its status.
2281
if ((*sc & IOC4_RXSB_PAR_ERR) &&
2282
(port->ip_notify & N_PARITY_ERROR)) {
2283
ioc4_cb_post_ncs(the_port,
2286
if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2287
(port->ip_notify & N_FRAMING_ERROR)){
2288
ioc4_cb_post_ncs(the_port,
2291
if ((*sc & IOC4_RXSB_BREAK)
2292
&& (port->ip_notify & N_BREAK)) {
2300
if (*sc & IOC4_RXSB_DATA_VALID) {
2301
*sc &= ~IOC4_RXSB_DATA_VALID;
2302
*buf = entry->ring_data[byte_num];
2309
/* If we used up this entry entirely, go on to the next one,
2310
* otherwise we must have run out of buffer space, so
2311
* leave the consumer pointer here for the next read in case
2312
* there are still unread bytes in this entry.
2314
if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2315
cons_ptr += (int)sizeof(struct ring_entry);
2316
cons_ptr &= PROD_CONS_MASK;
2320
/* Update consumer pointer and re-arm rx timer interrupt */
2321
writel(cons_ptr, &port->ip_serial_regs->srcir);
2322
port->ip_rx_cons = cons_ptr;
2324
/* If we have now dipped below the rx high water mark and we have
2325
* rx_high interrupt turned off, we can now turn it back on again.
2327
if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2328
& PROD_CONS_MASK) < ((port->ip_sscr &
2329
IOC4_SSCR_RX_THRESHOLD)
2330
<< IOC4_PROD_CONS_PTR_OFF))) {
2331
port->ip_flags &= ~INPUT_HIGH;
2332
enable_intrs(port, hooks->intr_rx_high);
2338
* receive_chars - upper level read. Called with ip_lock.
2339
* @the_port: port to read from
2341
static void receive_chars(struct uart_port *the_port)
2343
struct tty_struct *tty;
2344
unsigned char ch[IOC4_MAX_CHARS];
2345
int read_count, request_count = IOC4_MAX_CHARS;
2346
struct uart_icount *icount;
2347
struct uart_state *state = the_port->state;
2348
unsigned long pflags;
2350
/* Make sure all the pointers are "good" ones */
2353
if (!state->port.tty)
2356
spin_lock_irqsave(&the_port->lock, pflags);
2357
tty = state->port.tty;
2359
request_count = tty_buffer_request_room(tty, IOC4_MAX_CHARS);
2361
if (request_count > 0) {
2362
icount = &the_port->icount;
2363
read_count = do_read(the_port, ch, request_count);
2364
if (read_count > 0) {
2365
tty_insert_flip_string(tty, ch, read_count);
2366
icount->rx += read_count;
2370
spin_unlock_irqrestore(&the_port->lock, pflags);
2372
tty_flip_buffer_push(tty);
2376
* ic4_type - What type of console are we?
2377
* @port: Port to operate with (we ignore since we only have one port)
2380
static const char *ic4_type(struct uart_port *the_port)
2382
if (the_port->mapbase == PROTO_RS232)
2383
return "SGI IOC4 Serial [rs232]";
2385
return "SGI IOC4 Serial [rs422]";
2389
* ic4_tx_empty - Is the transmitter empty?
2390
* @port: Port to operate on
2393
static unsigned int ic4_tx_empty(struct uart_port *the_port)
2395
struct ioc4_port *port = get_ioc4_port(the_port, 0);
2396
unsigned int ret = 0;
2398
if (port_is_active(port, the_port)) {
2399
if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2406
* ic4_stop_tx - stop the transmitter
2407
* @port: Port to operate on
2410
static void ic4_stop_tx(struct uart_port *the_port)
2412
struct ioc4_port *port = get_ioc4_port(the_port, 0);
2414
if (port_is_active(port, the_port))
2415
set_notification(port, N_OUTPUT_LOWAT, 0);
2419
* null_void_function -
2420
* @port: Port to operate on
2423
static void null_void_function(struct uart_port *the_port)
2428
* ic4_shutdown - shut down the port - free irq and disable
2429
* @port: Port to shut down
2432
static void ic4_shutdown(struct uart_port *the_port)
2434
unsigned long port_flags;
2435
struct ioc4_port *port;
2436
struct uart_state *state;
2438
port = get_ioc4_port(the_port, 0);
2442
state = the_port->state;
2443
port->ip_port = NULL;
2445
wake_up_interruptible(&state->port.delta_msr_wait);
2447
if (state->port.tty)
2448
set_bit(TTY_IO_ERROR, &state->port.tty->flags);
2450
spin_lock_irqsave(&the_port->lock, port_flags);
2451
set_notification(port, N_ALL, 0);
2452
port->ip_flags = PORT_INACTIVE;
2453
spin_unlock_irqrestore(&the_port->lock, port_flags);
2457
* ic4_set_mctrl - set control lines (dtr, rts, etc)
2458
* @port: Port to operate on
2459
* @mctrl: Lines to set/unset
2462
static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2464
unsigned char mcr = 0;
2465
struct ioc4_port *port;
2467
port = get_ioc4_port(the_port, 0);
2468
if (!port_is_active(port, the_port))
2471
if (mctrl & TIOCM_RTS)
2472
mcr |= UART_MCR_RTS;
2473
if (mctrl & TIOCM_DTR)
2474
mcr |= UART_MCR_DTR;
2475
if (mctrl & TIOCM_OUT1)
2476
mcr |= UART_MCR_OUT1;
2477
if (mctrl & TIOCM_OUT2)
2478
mcr |= UART_MCR_OUT2;
2479
if (mctrl & TIOCM_LOOP)
2480
mcr |= UART_MCR_LOOP;
2482
set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2486
* ic4_get_mctrl - get control line info
2487
* @port: port to operate on
2490
static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2492
struct ioc4_port *port = get_ioc4_port(the_port, 0);
2494
unsigned int ret = 0;
2496
if (!port_is_active(port, the_port))
2499
shadow = readl(&port->ip_serial_regs->shadow);
2500
if (shadow & IOC4_SHADOW_DCD)
2502
if (shadow & IOC4_SHADOW_DR)
2504
if (shadow & IOC4_SHADOW_CTS)
2510
* ic4_start_tx - Start transmitter, flush any output
2511
* @port: Port to operate on
2514
static void ic4_start_tx(struct uart_port *the_port)
2516
struct ioc4_port *port = get_ioc4_port(the_port, 0);
2518
if (port_is_active(port, the_port)) {
2519
set_notification(port, N_OUTPUT_LOWAT, 1);
2520
enable_intrs(port, port->ip_hooks->intr_tx_mt);
2525
* ic4_break_ctl - handle breaks
2526
* @port: Port to operate on
2527
* @break_state: Break state
2530
static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2535
* ic4_startup - Start up the serial port
2536
* @port: Port to operate on
2539
static int ic4_startup(struct uart_port *the_port)
2542
struct ioc4_port *port;
2543
struct ioc4_control *control;
2544
struct uart_state *state;
2545
unsigned long port_flags;
2549
port = get_ioc4_port(the_port, 1);
2552
state = the_port->state;
2554
control = port->ip_control;
2556
port->ip_port = NULL;
2560
/* Start up the serial port */
2561
spin_lock_irqsave(&the_port->lock, port_flags);
2562
retval = ic4_startup_local(the_port);
2563
spin_unlock_irqrestore(&the_port->lock, port_flags);
2568
* ic4_set_termios - set termios stuff
2569
* @port: port to operate on
2570
* @termios: New settings
2575
ic4_set_termios(struct uart_port *the_port,
2576
struct ktermios *termios, struct ktermios *old_termios)
2578
unsigned long port_flags;
2580
spin_lock_irqsave(&the_port->lock, port_flags);
2581
ioc4_change_speed(the_port, termios, old_termios);
2582
spin_unlock_irqrestore(&the_port->lock, port_flags);
2586
* ic4_request_port - allocate resources for port - no op....
2587
* @port: port to operate on
2590
static int ic4_request_port(struct uart_port *port)
2595
/* Associate the uart functions above - given to serial core */
2597
static struct uart_ops ioc4_ops = {
2598
.tx_empty = ic4_tx_empty,
2599
.set_mctrl = ic4_set_mctrl,
2600
.get_mctrl = ic4_get_mctrl,
2601
.stop_tx = ic4_stop_tx,
2602
.start_tx = ic4_start_tx,
2603
.stop_rx = null_void_function,
2604
.enable_ms = null_void_function,
2605
.break_ctl = ic4_break_ctl,
2606
.startup = ic4_startup,
2607
.shutdown = ic4_shutdown,
2608
.set_termios = ic4_set_termios,
2610
.release_port = null_void_function,
2611
.request_port = ic4_request_port,
2615
* Boot-time initialization code
2618
static struct uart_driver ioc4_uart_rs232 = {
2619
.owner = THIS_MODULE,
2620
.driver_name = "ioc4_serial_rs232",
2621
.dev_name = DEVICE_NAME_RS232,
2622
.major = DEVICE_MAJOR,
2623
.minor = DEVICE_MINOR_RS232,
2624
.nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2627
static struct uart_driver ioc4_uart_rs422 = {
2628
.owner = THIS_MODULE,
2629
.driver_name = "ioc4_serial_rs422",
2630
.dev_name = DEVICE_NAME_RS422,
2631
.major = DEVICE_MAJOR,
2632
.minor = DEVICE_MINOR_RS422,
2633
.nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2638
* ioc4_serial_remove_one - detach function
2640
* @idd: IOC4 master module data for this IOC4
2643
static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2645
int port_num, port_type;
2646
struct ioc4_control *control;
2647
struct uart_port *the_port;
2648
struct ioc4_port *port;
2649
struct ioc4_soft *soft;
2651
/* If serial driver did not attach, don't try to detach */
2652
control = idd->idd_serial_data;
2656
for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2657
for (port_type = UART_PORT_MIN;
2658
port_type < UART_PORT_COUNT;
2660
the_port = &control->ic_port[port_num].icp_uart_port
2663
switch (port_type) {
2664
case UART_PORT_RS422:
2665
uart_remove_one_port(&ioc4_uart_rs422,
2669
case UART_PORT_RS232:
2670
uart_remove_one_port(&ioc4_uart_rs232,
2676
port = control->ic_port[port_num].icp_port;
2677
/* we allocate in pairs */
2678
if (!(port_num & 1) && port) {
2679
pci_free_consistent(port->ip_pdev,
2680
TOTAL_RING_BUF_SIZE,
2681
port->ip_cpu_ringbuf,
2682
port->ip_dma_ringbuf);
2686
soft = control->ic_soft;
2688
free_irq(control->ic_irq, soft);
2689
if (soft->is_ioc4_serial_addr) {
2690
iounmap(soft->is_ioc4_serial_addr);
2691
release_mem_region((unsigned long)
2692
soft->is_ioc4_serial_addr,
2693
sizeof(struct ioc4_serial));
2698
idd->idd_serial_data = NULL;
2705
* ioc4_serial_core_attach_rs232 - register with serial core
2706
* This is done during pci probing
2707
* @pdev: handle for this card
2710
ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2712
struct ioc4_port *port;
2713
struct uart_port *the_port;
2714
struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2715
struct ioc4_control *control = idd->idd_serial_data;
2718
struct uart_driver *u_driver;
2721
DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2722
__func__, pdev, (void *)control));
2727
port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2730
u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2733
/* once around for each port on this card */
2734
for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2735
the_port = &control->ic_port[port_num].icp_uart_port
2737
port = control->ic_port[port_num].icp_port;
2738
port->ip_all_ports[port_type_idx] = the_port;
2740
DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2741
__func__, (void *)the_port,
2743
port_type == PROTO_RS232 ? "rs232" : "rs422"));
2745
/* membase, iobase and mapbase just need to be non-0 */
2746
the_port->membase = (unsigned char __iomem *)1;
2747
the_port->iobase = (pdev->bus->number << 16) | port_num;
2748
the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2749
the_port->mapbase = port_type;
2750
the_port->type = PORT_16550A;
2751
the_port->fifosize = IOC4_FIFO_CHARS;
2752
the_port->ops = &ioc4_ops;
2753
the_port->irq = control->ic_irq;
2754
the_port->dev = &pdev->dev;
2755
spin_lock_init(&the_port->lock);
2756
if (uart_add_one_port(u_driver, the_port) < 0) {
2758
"%s: unable to add port %d bus %d\n",
2759
__func__, the_port->line, pdev->bus->number);
2762
("IOC4 serial port %d irq = %d, bus %d\n",
2763
the_port->line, the_port->irq, pdev->bus->number));
2770
* ioc4_serial_attach_one - register attach function
2771
* called per card found from IOC4 master module.
2772
* @idd: Master module data for this IOC4
2775
ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2777
unsigned long tmp_addr1;
2778
struct ioc4_serial __iomem *serial;
2779
struct ioc4_soft *soft;
2780
struct ioc4_control *control;
2784
DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, idd->idd_pdev,
2787
/* PCI-RT does not bring out serial connections.
2788
* Do not attach to this particular IOC4.
2790
if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2793
/* request serial registers */
2794
tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2796
if (!request_mem_region(tmp_addr1, sizeof(struct ioc4_serial),
2799
"ioc4 (%p): unable to get request region for "
2800
"uart space\n", (void *)idd->idd_pdev);
2804
serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2807
"ioc4 (%p) : unable to remap ioc4 serial register\n",
2808
(void *)idd->idd_pdev);
2812
DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2813
__func__, (void *)idd->idd_misc_regs,
2816
/* Get memory for the new card */
2817
control = kzalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2820
printk(KERN_WARNING "ioc4_attach_one"
2821
": unable to get memory for the IOC4\n");
2825
idd->idd_serial_data = control;
2827
/* Allocate the soft structure */
2828
soft = kzalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2831
"ioc4 (%p): unable to get memory for the soft struct\n",
2832
(void *)idd->idd_pdev);
2837
spin_lock_init(&soft->is_ir_lock);
2838
soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2839
soft->is_ioc4_serial_addr = serial;
2842
writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2843
&idd->idd_misc_regs->sio_cr.raw);
2845
/* Enable serial port mode select generic PIO pins as outputs */
2846
writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2847
| IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2848
&idd->idd_misc_regs->gpcr_s.raw);
2850
/* Clear and disable all serial interrupts */
2851
write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2852
writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2853
write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2854
IOC4_OTHER_INTR_TYPE);
2855
writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2856
control->ic_soft = soft;
2858
/* Hook up interrupt handler */
2859
if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2860
"sgi-ioc4serial", soft)) {
2861
control->ic_irq = idd->idd_pdev->irq;
2864
"%s : request_irq fails for IRQ 0x%x\n ",
2865
__func__, idd->idd_pdev->irq);
2867
ret = ioc4_attach_local(idd);
2871
/* register port with the serial core - 1 rs232, 1 rs422 */
2873
if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2876
if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2879
Num_of_ioc4_cards++;
2883
/* error exits that give back resources */
2885
ioc4_serial_remove_one(idd);
2893
release_mem_region(tmp_addr1, sizeof(struct ioc4_serial));
2900
static struct ioc4_submodule ioc4_serial_submodule = {
2901
.is_name = "IOC4_serial",
2902
.is_owner = THIS_MODULE,
2903
.is_probe = ioc4_serial_attach_one,
2904
.is_remove = ioc4_serial_remove_one,
2908
* ioc4_serial_init - module init
2910
static int __init ioc4_serial_init(void)
2914
/* register with serial core */
2915
if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2917
"%s: Couldn't register rs232 IOC4 serial driver\n",
2921
if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2923
"%s: Couldn't register rs422 IOC4 serial driver\n",
2925
goto out_uart_rs232;
2928
/* register with IOC4 main module */
2929
ret = ioc4_register_submodule(&ioc4_serial_submodule);
2931
goto out_uart_rs422;
2935
uart_unregister_driver(&ioc4_uart_rs422);
2937
uart_unregister_driver(&ioc4_uart_rs232);
2942
static void __exit ioc4_serial_exit(void)
2944
ioc4_unregister_submodule(&ioc4_serial_submodule);
2945
uart_unregister_driver(&ioc4_uart_rs232);
2946
uart_unregister_driver(&ioc4_uart_rs422);
2949
late_initcall(ioc4_serial_init); /* Call only after tty init is done */
2950
module_exit(ioc4_serial_exit);
2952
MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2953
MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2954
MODULE_LICENSE("GPL");