2
* linux/arch/arm/mm/cache-v4wt.S
4
* Copyright (C) 1997-2002 Russell king
6
* This program is free software; you can redistribute it and/or modify
7
* it under the terms of the GNU General Public License version 2 as
8
* published by the Free Software Foundation.
10
* ARMv4 write through cache operations support.
12
* We assume that the write buffer is not enabled.
14
#include <linux/linkage.h>
15
#include <linux/init.h>
17
#include "proc-macros.S"
20
* The size of one data cache line.
22
#define CACHE_DLINESIZE 32
25
* The number of data cache segments.
27
#define CACHE_DSEGMENTS 8
30
* The number of lines in a cache segment.
32
#define CACHE_DENTRIES 64
35
* This is the size at which it becomes more efficient to
36
* clean the whole cache, rather than using the individual
37
* cache line maintenance instructions.
39
* *** This needs benchmarking
41
#define CACHE_DLIMIT 16384
46
* Unconditionally clean and invalidate the entire icache.
48
ENTRY(v4wt_flush_icache_all)
50
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
52
ENDPROC(v4wt_flush_icache_all)
55
* flush_user_cache_all()
57
* Invalidate all cache entries in a particular address
60
ENTRY(v4wt_flush_user_cache_all)
63
* flush_kern_cache_all()
65
* Clean and invalidate the entire cache.
67
ENTRY(v4wt_flush_kern_cache_all)
72
mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
73
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
77
* flush_user_cache_range(start, end, flags)
79
* Clean and invalidate a range of cache entries in the specified
82
* - start - start address (inclusive, page aligned)
83
* - end - end address (exclusive, page aligned)
84
* - flags - vma_area_struct flags describing address space
86
ENTRY(v4wt_flush_user_cache_range)
87
sub r3, r1, r0 @ calculate total size
89
bhs __flush_whole_cache
91
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
93
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
94
add r0, r0, #CACHE_DLINESIZE
100
* coherent_kern_range(start, end)
102
* Ensure coherency between the Icache and the Dcache in the
103
* region described by start. If you have non-snooping
104
* Harvard caches, you need to implement this function.
106
* - start - virtual start address
107
* - end - virtual end address
109
ENTRY(v4wt_coherent_kern_range)
113
* coherent_user_range(start, end)
115
* Ensure coherency between the Icache and the Dcache in the
116
* region described by start. If you have non-snooping
117
* Harvard caches, you need to implement this function.
119
* - start - virtual start address
120
* - end - virtual end address
122
ENTRY(v4wt_coherent_user_range)
123
bic r0, r0, #CACHE_DLINESIZE - 1
124
1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
125
add r0, r0, #CACHE_DLINESIZE
131
* flush_kern_dcache_area(void *addr, size_t size)
133
* Ensure no D cache aliasing occurs, either with itself or
136
* - addr - kernel address
137
* - size - region size
139
ENTRY(v4wt_flush_kern_dcache_area)
141
mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
146
* dma_inv_range(start, end)
148
* Invalidate (discard) the specified virtual address range.
149
* May not write back any entries. If 'start' or 'end'
150
* are not cache line aligned, those lines must be written
153
* - start - virtual start address
154
* - end - virtual end address
157
bic r0, r0, #CACHE_DLINESIZE - 1
158
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
159
add r0, r0, #CACHE_DLINESIZE
165
* dma_flush_range(start, end)
167
* Clean and invalidate the specified virtual address range.
169
* - start - virtual start address
170
* - end - virtual end address
172
.globl v4wt_dma_flush_range
173
.equ v4wt_dma_flush_range, v4wt_dma_inv_range
176
* dma_unmap_area(start, size, dir)
177
* - start - kernel virtual start address
178
* - size - size of region
179
* - dir - DMA direction
181
ENTRY(v4wt_dma_unmap_area)
183
teq r2, #DMA_TO_DEVICE
184
bne v4wt_dma_inv_range
188
* dma_map_area(start, size, dir)
189
* - start - kernel virtual start address
190
* - size - size of region
191
* - dir - DMA direction
193
ENTRY(v4wt_dma_map_area)
195
ENDPROC(v4wt_dma_unmap_area)
196
ENDPROC(v4wt_dma_map_area)
200
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
201
define_cache_functions v4wt