2
* Copyright 2000, 2008 MontaVista Software Inc.
3
* Author: MontaVista Software, Inc. <source@mvista.com>
5
* This program is free software; you can redistribute it and/or modify it
6
* under the terms of the GNU General Public License as published by the
7
* Free Software Foundation; either version 2 of the License, or (at your
8
* option) any later version.
10
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21
* You should have received a copy of the GNU General Public License along
22
* with this program; if not, write to the Free Software Foundation, Inc.,
23
* 675 Mass Ave, Cambridge, MA 02139, USA.
26
#include <linux/delay.h>
27
#include <linux/gpio.h>
28
#include <linux/init.h>
29
#include <linux/interrupt.h>
31
#include <asm/mach-au1x00/au1000.h>
32
#include <asm/mach-pb1x00/pb1000.h>
33
#include <asm/reboot.h>
36
#include "../platform.h"
38
const char *get_system_type(void)
40
return "Alchemy Pb1000";
43
static void board_reset(char *c)
45
asm volatile ("jr %0" : : "r" (0xbfc00000));
48
static void board_power_off(void)
57
void __init board_setup(void)
59
u32 pin_func, static_cfg0;
60
u32 sys_freqctrl, sys_clksrc;
61
u32 prid = read_c0_prid();
66
/* Set AUX clock to 12 MHz * 8 = 96 MHz */
67
au_writel(8, SYS_AUXPLL);
68
alchemy_gpio1_input_enable();
71
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
72
/* Zero and disable FREQ2 */
73
sys_freqctrl = au_readl(SYS_FREQCTRL0);
74
sys_freqctrl &= ~0xFFF00000;
75
au_writel(sys_freqctrl, SYS_FREQCTRL0);
77
/* Zero and disable USBH/USBD clocks */
78
sys_clksrc = au_readl(SYS_CLKSRC);
79
sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
80
SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
81
au_writel(sys_clksrc, SYS_CLKSRC);
83
sys_freqctrl = au_readl(SYS_FREQCTRL0);
84
sys_freqctrl &= ~0xFFF00000;
86
sys_clksrc = au_readl(SYS_CLKSRC);
87
sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
88
SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
90
switch (prid & 0x000000FF) {
94
/* CPU core freq to 48 MHz to slow it way down... */
95
au_writel(4, SYS_CPUPLL);
98
* Setup 48 MHz FREQ2 from CPUPLL for USB Host
99
* FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
101
sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
102
au_writel(sys_freqctrl, SYS_FREQCTRL0);
104
/* CPU core freq to 384 MHz */
105
au_writel(0x20, SYS_CPUPLL);
107
printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
110
default: /* HC and newer */
111
/* FREQ2 = aux / 2 = 48 MHz */
112
sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
113
SYS_FC_FE2 | SYS_FC_FS2;
114
au_writel(sys_freqctrl, SYS_FREQCTRL0);
119
* Route 48 MHz FREQ2 into USB Host and/or Device
121
sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
122
au_writel(sys_clksrc, SYS_CLKSRC);
124
/* Configure pins GPIO[14:9] as GPIO */
125
pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
127
/* 2nd USB port is USB host */
128
pin_func |= SYS_PF_USB;
130
au_writel(pin_func, SYS_PINFUNC);
132
alchemy_gpio_direction_input(11);
133
alchemy_gpio_direction_input(13);
134
alchemy_gpio_direction_output(4, 0);
135
alchemy_gpio_direction_output(5, 0);
136
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
138
/* Make GPIO 15 an input (for interrupt line) */
139
pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
140
/* We don't need I2S, so make it available for GPIO[31:29] */
141
pin_func |= SYS_PF_I2S;
142
au_writel(pin_func, SYS_PINFUNC);
144
alchemy_gpio_direction_input(15);
146
static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
147
au_writel(static_cfg0, MEM_STCFG0);
149
/* configure RCE2* for LCD */
150
au_writel(0x00000004, MEM_STCFG2);
153
au_writel(0x09000000, MEM_STTIME2);
155
/* Set 32-bit base address decoding for RCE2* */
156
au_writel(0x10003ff0, MEM_STADDR2);
160
* Expand CE0 to cover PCI
162
au_writel(0x11803e40, MEM_STADDR1);
164
/* Burst visibility on */
165
au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
167
au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
168
au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
170
/* Setup the static bus controller */
171
au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
172
au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
173
au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
176
* Enable Au1000 BCLK switching - note: sed1356 must not use
177
* its BCLK (Au1000 LCLK) for any timings
179
switch (prid & 0x000000FF) {
184
default: /* HC and newer */
186
* Enable sys bus clock divider when IDLE state or no bus
189
au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
193
pm_power_off = board_power_off;
194
_machine_halt = board_power_off;
195
_machine_restart = board_reset;
198
static int __init pb1000_init_irq(void)
200
irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
203
arch_initcall(pb1000_init_irq);
205
static int __init pb1000_device_init(void)
207
return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
209
device_initcall(pb1000_device_init);