2
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4
* Refer to drivers/dma/imx-sdma.c
6
* This program is free software; you can redistribute it and/or modify
7
* it under the terms of the GNU General Public License version 2 as
8
* published by the Free Software Foundation.
11
#include <linux/init.h>
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#include <linux/types.h>
14
#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <linux/semaphore.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
29
#include <mach/common.h>
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* NOTE: The term "PIO" throughout the mxs-dma implementation means
33
* PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
34
* dma can program the controller registers of peripheral devices.
37
#define MXS_DMA_APBH 0
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#define MXS_DMA_APBX 1
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#define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH)
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#define APBH_VERSION_LATEST 3
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#define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST)
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#define HW_APBHX_CTRL0 0x000
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#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
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#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
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#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8
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#define BP_APBH_CTRL0_RESET_CHANNEL 16
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#define HW_APBHX_CTRL1 0x010
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#define HW_APBHX_CTRL2 0x020
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#define HW_APBHX_CHANNEL_CTRL 0x030
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#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
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#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
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#define HW_APBX_VERSION 0x800
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#define BP_APBHX_VERSION_MAJOR 24
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#define HW_APBHX_CHn_NXTCMDAR(n) \
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(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA(n) \
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(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
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* ccw bits definitions
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* NAND_LOCK: 4 (1) - not implemented
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* NAND_WAIT4READY: 5 (1) - not implemented
71
* HALT_ON_TERMINATE: 8 (1)
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* TERMINATE_FLUSH: 9 (1)
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* RESERVED: 10..11 (2)
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#define BP_CCW_COMMAND 0
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#define BM_CCW_COMMAND (3 << 0)
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#define CCW_CHAIN (1 << 2)
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#define CCW_IRQ (1 << 3)
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#define CCW_DEC_SEM (1 << 6)
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#define CCW_WAIT4END (1 << 7)
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#define CCW_HALT_ON_TERM (1 << 8)
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#define CCW_TERM_FLUSH (1 << 9)
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#define BP_CCW_PIO_NUM 12
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#define BM_CCW_PIO_NUM (0xf << 12)
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#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
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#define MXS_DMA_CMD_NO_XFER 0
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#define MXS_DMA_CMD_WRITE 1
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#define MXS_DMA_CMD_READ 2
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#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
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#define MAX_XFER_BYTES 0xff00
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#define MXS_PIO_WORDS 16
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u32 pio_words[MXS_PIO_WORDS];
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#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
106
struct mxs_dma_chan {
107
struct mxs_dma_engine *mxs_dma;
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struct dma_chan chan;
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struct dma_async_tx_descriptor desc;
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struct tasklet_struct tasklet;
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struct mxs_dma_ccw *ccw;
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dma_cookie_t last_completed;
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enum dma_status status;
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#define MXS_DMA_SG_LOOP (1 << 0)
120
#define MXS_DMA_CHANNELS 16
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#define MXS_DMA_CHANNELS_MASK 0xffff
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struct mxs_dma_engine {
125
unsigned int version;
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struct dma_device dma_device;
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struct device_dma_parameters dma_parms;
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struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
133
static inline void mxs_dma_clkgate(struct mxs_dma_chan *mxs_chan, int enable)
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
136
int chan_id = mxs_chan->chan.chan_id;
137
int set_clr = enable ? MXS_CLR_ADDR : MXS_SET_ADDR;
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/* enable apbh channel clock */
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writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL),
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mxs_dma->base + HW_APBHX_CTRL0 + set_clr);
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mxs_dma->base + HW_APBHX_CTRL0 + set_clr);
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static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
152
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
153
int chan_id = mxs_chan->chan.chan_id;
155
if (dma_is_apbh() && apbh_is_old())
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writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
157
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
159
writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
163
static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
165
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
166
int chan_id = mxs_chan->chan.chan_id;
168
/* clkgate needs to be enabled before writing other registers */
169
mxs_dma_clkgate(mxs_chan, 1);
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/* set cmd_addr up */
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writel(mxs_chan->ccw_phys,
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mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
175
/* write 1 to SEMA to kick off the channel */
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writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
179
static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
181
/* disable apbh channel clock */
182
mxs_dma_clkgate(mxs_chan, 0);
184
mxs_chan->status = DMA_SUCCESS;
187
static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
189
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
190
int chan_id = mxs_chan->chan.chan_id;
192
/* freeze the channel */
193
if (dma_is_apbh() && apbh_is_old())
195
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
198
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
200
mxs_chan->status = DMA_PAUSED;
203
static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
205
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
206
int chan_id = mxs_chan->chan.chan_id;
208
/* unfreeze the channel */
209
if (dma_is_apbh() && apbh_is_old())
211
mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
214
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
216
mxs_chan->status = DMA_IN_PROGRESS;
219
static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan)
221
dma_cookie_t cookie = mxs_chan->chan.cookie;
226
mxs_chan->chan.cookie = cookie;
227
mxs_chan->desc.cookie = cookie;
232
static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
234
return container_of(chan, struct mxs_dma_chan, chan);
237
static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
239
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);
241
mxs_dma_enable_chan(mxs_chan);
243
return mxs_dma_assign_cookie(mxs_chan);
246
static void mxs_dma_tasklet(unsigned long data)
248
struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
250
if (mxs_chan->desc.callback)
251
mxs_chan->desc.callback(mxs_chan->desc.callback_param);
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static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
256
struct mxs_dma_engine *mxs_dma = dev_id;
259
/* completion status */
260
stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
261
stat1 &= MXS_DMA_CHANNELS_MASK;
262
writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
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stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
266
writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
269
* When both completion and error of termination bits set at the
270
* same time, we do not take it as an error. IOW, it only becomes
271
* an error we need to handler here in case of ether it's (1) an bus
272
* error or (2) a termination error with no completion.
274
stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
275
(~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
277
/* combine error and completion status for checking */
278
stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
280
int channel = fls(stat1) - 1;
281
struct mxs_dma_chan *mxs_chan =
282
&mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
284
if (channel >= MXS_DMA_CHANNELS) {
285
dev_dbg(mxs_dma->dma_device.dev,
286
"%s: error in channel %d\n", __func__,
287
channel - MXS_DMA_CHANNELS);
288
mxs_chan->status = DMA_ERROR;
289
mxs_dma_reset_chan(mxs_chan);
291
if (mxs_chan->flags & MXS_DMA_SG_LOOP)
292
mxs_chan->status = DMA_IN_PROGRESS;
294
mxs_chan->status = DMA_SUCCESS;
297
stat1 &= ~(1 << channel);
299
if (mxs_chan->status == DMA_SUCCESS)
300
mxs_chan->last_completed = mxs_chan->desc.cookie;
302
/* schedule tasklet on this channel */
303
tasklet_schedule(&mxs_chan->tasklet);
309
static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
311
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
312
struct mxs_dma_data *data = chan->private;
313
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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mxs_chan->chan_irq = data->chan_irq;
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mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
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&mxs_chan->ccw_phys, GFP_KERNEL);
323
if (!mxs_chan->ccw) {
328
memset(mxs_chan->ccw, 0, PAGE_SIZE);
330
if (mxs_chan->chan_irq != NO_IRQ) {
331
ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
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0, "mxs-dma", mxs_dma);
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ret = clk_enable(mxs_dma->clk);
341
/* clkgate needs to be enabled for reset to finish */
342
mxs_dma_clkgate(mxs_chan, 1);
343
mxs_dma_reset_chan(mxs_chan);
344
mxs_dma_clkgate(mxs_chan, 0);
346
dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
347
mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
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/* the descriptor is ready */
350
async_tx_ack(&mxs_chan->desc);
355
free_irq(mxs_chan->chan_irq, mxs_dma);
357
dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
358
mxs_chan->ccw, mxs_chan->ccw_phys);
363
static void mxs_dma_free_chan_resources(struct dma_chan *chan)
365
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
366
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
368
mxs_dma_disable_chan(mxs_chan);
370
free_irq(mxs_chan->chan_irq, mxs_dma);
372
dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
373
mxs_chan->ccw, mxs_chan->ccw_phys);
375
clk_disable(mxs_dma->clk);
378
static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
379
struct dma_chan *chan, struct scatterlist *sgl,
380
unsigned int sg_len, enum dma_data_direction direction,
381
unsigned long append)
383
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
384
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
385
struct mxs_dma_ccw *ccw;
386
struct scatterlist *sg;
391
if (mxs_chan->status == DMA_IN_PROGRESS && !append)
394
if (sg_len + (append ? idx : 0) > NUM_CCW) {
395
dev_err(mxs_dma->dma_device.dev,
396
"maximum number of sg exceeded: %d > %d\n",
401
mxs_chan->status = DMA_IN_PROGRESS;
405
* If the sg is prepared with append flag set, the sg
406
* will be appended to the last prepared sg.
410
ccw = &mxs_chan->ccw[idx - 1];
411
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
412
ccw->bits |= CCW_CHAIN;
413
ccw->bits &= ~CCW_IRQ;
414
ccw->bits &= ~CCW_DEC_SEM;
415
ccw->bits &= ~CCW_WAIT4END;
420
if (direction == DMA_NONE) {
421
ccw = &mxs_chan->ccw[idx++];
424
for (j = 0; j < sg_len;)
425
ccw->pio_words[j++] = *pio++;
428
ccw->bits |= CCW_IRQ;
429
ccw->bits |= CCW_DEC_SEM;
430
ccw->bits |= CCW_WAIT4END;
431
ccw->bits |= CCW_HALT_ON_TERM;
432
ccw->bits |= CCW_TERM_FLUSH;
433
ccw->bits |= BF_CCW(sg_len, PIO_NUM);
434
ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
436
for_each_sg(sgl, sg, sg_len, i) {
437
if (sg->length > MAX_XFER_BYTES) {
438
dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
439
sg->length, MAX_XFER_BYTES);
443
ccw = &mxs_chan->ccw[idx++];
445
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
446
ccw->bufaddr = sg->dma_address;
447
ccw->xfer_bytes = sg->length;
450
ccw->bits |= CCW_CHAIN;
451
ccw->bits |= CCW_HALT_ON_TERM;
452
ccw->bits |= CCW_TERM_FLUSH;
453
ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ?
454
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
457
if (i + 1 == sg_len) {
458
ccw->bits &= ~CCW_CHAIN;
459
ccw->bits |= CCW_IRQ;
460
ccw->bits |= CCW_DEC_SEM;
461
ccw->bits |= CCW_WAIT4END;
466
return &mxs_chan->desc;
469
mxs_chan->status = DMA_ERROR;
473
static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
474
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
475
size_t period_len, enum dma_data_direction direction)
477
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
478
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
479
int num_periods = buf_len / period_len;
482
if (mxs_chan->status == DMA_IN_PROGRESS)
485
mxs_chan->status = DMA_IN_PROGRESS;
486
mxs_chan->flags |= MXS_DMA_SG_LOOP;
488
if (num_periods > NUM_CCW) {
489
dev_err(mxs_dma->dma_device.dev,
490
"maximum number of sg exceeded: %d > %d\n",
491
num_periods, NUM_CCW);
495
if (period_len > MAX_XFER_BYTES) {
496
dev_err(mxs_dma->dma_device.dev,
497
"maximum period size exceeded: %d > %d\n",
498
period_len, MAX_XFER_BYTES);
502
while (buf < buf_len) {
503
struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
505
if (i + 1 == num_periods)
506
ccw->next = mxs_chan->ccw_phys;
508
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
510
ccw->bufaddr = dma_addr;
511
ccw->xfer_bytes = period_len;
514
ccw->bits |= CCW_CHAIN;
515
ccw->bits |= CCW_IRQ;
516
ccw->bits |= CCW_HALT_ON_TERM;
517
ccw->bits |= CCW_TERM_FLUSH;
518
ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ?
519
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
521
dma_addr += period_len;
527
return &mxs_chan->desc;
530
mxs_chan->status = DMA_ERROR;
534
static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
537
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
541
case DMA_TERMINATE_ALL:
542
mxs_dma_disable_chan(mxs_chan);
543
mxs_dma_reset_chan(mxs_chan);
546
mxs_dma_pause_chan(mxs_chan);
549
mxs_dma_resume_chan(mxs_chan);
558
static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
559
dma_cookie_t cookie, struct dma_tx_state *txstate)
561
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
562
dma_cookie_t last_used;
564
last_used = chan->cookie;
565
dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0);
567
return mxs_chan->status;
570
static void mxs_dma_issue_pending(struct dma_chan *chan)
573
* Nothing to do. We only have a single descriptor.
577
static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
581
ret = clk_enable(mxs_dma->clk);
585
ret = mxs_reset_block(mxs_dma->base);
589
/* only major version matters */
590
mxs_dma->version = readl(mxs_dma->base +
591
((mxs_dma->dev_id == MXS_DMA_APBX) ?
592
HW_APBX_VERSION : HW_APBH_VERSION)) >>
593
BP_APBHX_VERSION_MAJOR;
595
/* enable apbh burst */
597
writel(BM_APBH_CTRL0_APB_BURST_EN,
598
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
599
writel(BM_APBH_CTRL0_APB_BURST8_EN,
600
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
603
/* enable irq for all the channels */
604
writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
605
mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
607
clk_disable(mxs_dma->clk);
615
static int __init mxs_dma_probe(struct platform_device *pdev)
617
const struct platform_device_id *id_entry =
618
platform_get_device_id(pdev);
619
struct mxs_dma_engine *mxs_dma;
620
struct resource *iores;
623
mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
627
mxs_dma->dev_id = id_entry->driver_data;
629
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
631
if (!request_mem_region(iores->start, resource_size(iores),
634
goto err_request_region;
637
mxs_dma->base = ioremap(iores->start, resource_size(iores));
638
if (!mxs_dma->base) {
643
mxs_dma->clk = clk_get(&pdev->dev, NULL);
644
if (IS_ERR(mxs_dma->clk)) {
645
ret = PTR_ERR(mxs_dma->clk);
649
dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
650
dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
652
INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
654
/* Initialize channel parameters */
655
for (i = 0; i < MXS_DMA_CHANNELS; i++) {
656
struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
658
mxs_chan->mxs_dma = mxs_dma;
659
mxs_chan->chan.device = &mxs_dma->dma_device;
661
tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
662
(unsigned long) mxs_chan);
665
/* Add the channel to mxs_chan list */
666
list_add_tail(&mxs_chan->chan.device_node,
667
&mxs_dma->dma_device.channels);
670
ret = mxs_dma_init(mxs_dma);
674
mxs_dma->dma_device.dev = &pdev->dev;
676
/* mxs_dma gets 65535 bytes maximum sg size */
677
mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
678
dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
680
mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
681
mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
682
mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
683
mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
684
mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
685
mxs_dma->dma_device.device_control = mxs_dma_control;
686
mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
688
ret = dma_async_device_register(&mxs_dma->dma_device);
690
dev_err(mxs_dma->dma_device.dev, "unable to register\n");
694
dev_info(mxs_dma->dma_device.dev, "initialized\n");
699
clk_put(mxs_dma->clk);
701
iounmap(mxs_dma->base);
703
release_mem_region(iores->start, resource_size(iores));
709
static struct platform_device_id mxs_dma_type[] = {
711
.name = "mxs-dma-apbh",
712
.driver_data = MXS_DMA_APBH,
714
.name = "mxs-dma-apbx",
715
.driver_data = MXS_DMA_APBX,
721
static struct platform_driver mxs_dma_driver = {
725
.id_table = mxs_dma_type,
728
static int __init mxs_dma_module_init(void)
730
return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
732
subsys_initcall(mxs_dma_module_init);