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/******************************************************************************
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Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
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This program is free software; you can redistribute it and/or modify it
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under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59
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Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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The full GNU General Public License is included in this distribution in the
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Intel Linux Wireless <ilw@linux.intel.com>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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******************************************************************************/
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#define WEXT_USECHANNELS 1
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/ethtool.h>
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#include <linux/skbuff.h>
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#include <linux/etherdevice.h>
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#include <linux/delay.h>
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#include <linux/random.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <linux/wireless.h>
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#include <linux/jiffies.h>
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#include <net/lib80211.h>
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#include <net/ieee80211_radiotap.h>
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#define DRV_NAME "ipw2200"
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#include <linux/workqueue.h>
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/* Authentication and Association States */
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enum connection_manager_assoc_states {
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#define IPW_WAIT (1<<0)
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#define IPW_QUIET (1<<1)
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#define IPW_ROAMING (1<<2)
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#define IPW_POWER_MODE_CAM 0x00 //(always on)
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#define IPW_POWER_INDEX_1 0x01
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#define IPW_POWER_INDEX_2 0x02
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#define IPW_POWER_INDEX_3 0x03
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#define IPW_POWER_INDEX_4 0x04
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#define IPW_POWER_INDEX_5 0x05
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#define IPW_POWER_AC 0x06
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#define IPW_POWER_BATTERY 0x07
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#define IPW_POWER_LIMIT 0x07
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#define IPW_POWER_MASK 0x0F
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#define IPW_POWER_ENABLED 0x10
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#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
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#define IPW_CMD_HOST_COMPLETE 2
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#define IPW_CMD_POWER_DOWN 4
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#define IPW_CMD_SYSTEM_CONFIG 6
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#define IPW_CMD_MULTICAST_ADDRESS 7
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#define IPW_CMD_SSID 8
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#define IPW_CMD_ADAPTER_ADDRESS 11
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#define IPW_CMD_PORT_TYPE 12
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#define IPW_CMD_RTS_THRESHOLD 15
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#define IPW_CMD_FRAG_THRESHOLD 16
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#define IPW_CMD_POWER_MODE 17
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#define IPW_CMD_WEP_KEY 18
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#define IPW_CMD_TGI_TX_KEY 19
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#define IPW_CMD_SCAN_REQUEST 20
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#define IPW_CMD_ASSOCIATE 21
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#define IPW_CMD_SUPPORTED_RATES 22
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#define IPW_CMD_SCAN_ABORT 23
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#define IPW_CMD_TX_FLUSH 24
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#define IPW_CMD_QOS_PARAMETERS 25
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#define IPW_CMD_SCAN_REQUEST_EXT 26
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#define IPW_CMD_DINO_CONFIG 30
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#define IPW_CMD_RSN_CAPABILITIES 31
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#define IPW_CMD_RX_KEY 32
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#define IPW_CMD_CARD_DISABLE 33
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#define IPW_CMD_SEED_NUMBER 34
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#define IPW_CMD_TX_POWER 35
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#define IPW_CMD_COUNTRY_INFO 36
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#define IPW_CMD_AIRONET_INFO 37
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#define IPW_CMD_AP_TX_POWER 38
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#define IPW_CMD_CCKM_INFO 39
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#define IPW_CMD_CCX_VER_INFO 40
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#define IPW_CMD_SET_CALIBRATION 41
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#define IPW_CMD_SENSITIVITY_CALIB 42
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#define IPW_CMD_RETRY_LIMIT 51
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#define IPW_CMD_IPW_PRE_POWER_DOWN 58
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#define IPW_CMD_VAP_BEACON_TEMPLATE 60
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#define IPW_CMD_VAP_DTIM_PERIOD 61
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#define IPW_CMD_EXT_SUPPORTED_RATES 62
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#define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
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#define IPW_CMD_VAP_QUIET_INTERVALS 64
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#define IPW_CMD_VAP_CHANNEL_SWITCH 65
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#define IPW_CMD_VAP_MANDATORY_CHANNELS 66
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#define IPW_CMD_VAP_CELL_PWR_LIMIT 67
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#define IPW_CMD_VAP_CF_PARAM_SET 68
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#define IPW_CMD_VAP_SET_BEACONING_STATE 69
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#define IPW_CMD_MEASUREMENT 80
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#define IPW_CMD_POWER_CAPABILITY 81
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#define IPW_CMD_SUPPORTED_CHANNELS 82
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#define IPW_CMD_TPC_REPORT 83
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#define IPW_CMD_WME_INFO 84
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#define IPW_CMD_PRODUCTION_COMMAND 85
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#define IPW_CMD_LINKSYS_EOU_INFO 90
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#define NUM_TFD_CHUNKS 6
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#define TX_QUEUE_SIZE 32
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#define RX_QUEUE_SIZE 32
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#define DINO_CMD_WEP_KEY 0x08
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#define DINO_CMD_TX 0x0B
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#define DCT_ANTENNA_A 0x01
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#define DCT_ANTENNA_B 0x02
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* TX Queue Flag Definitions
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/* tx wep key definition */
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#define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
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#define DCT_WEP_KEY_64Bit 0x40
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#define DCT_WEP_KEY_128Bit 0x80
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#define DCT_WEP_KEY_128bitIV 0xC0
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#define DCT_WEP_KEY_SIZE_MASK 0xC0
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#define DCT_WEP_KEY_INDEX_MASK 0x0F
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#define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
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/* abort attempt if mgmt frame is rx'd */
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#define DCT_FLAG_ABORT_MGMT 0x01
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#define DCT_FLAG_CTS_REQUIRED 0x02
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/* use short preamble */
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#define DCT_FLAG_LONG_PREAMBLE 0x00
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#define DCT_FLAG_SHORT_PREAMBLE 0x04
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#define DCT_FLAG_RTS_REQD 0x08
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/* dont calculate duration field */
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#define DCT_FLAG_DUR_SET 0x10
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/* even if MAC WEP set (allows pre-encrypt) */
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#define DCT_FLAG_NO_WEP 0x20
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/* overwrite TSF field */
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#define DCT_FLAG_TSF_REQD 0x40
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/* ACK rx is expected to follow */
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#define DCT_FLAG_ACK_REQD 0x80
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/* TX flags extension */
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#define DCT_FLAG_EXT_MODE_CCK 0x01
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#define DCT_FLAG_EXT_MODE_OFDM 0x00
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#define DCT_FLAG_EXT_SECURITY_WEP 0x00
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#define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP
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#define DCT_FLAG_EXT_SECURITY_CKIP 0x04
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#define DCT_FLAG_EXT_SECURITY_CCM 0x08
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#define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
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#define DCT_FLAG_EXT_SECURITY_MASK 0x0C
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#define DCT_FLAG_EXT_QOS_ENABLED 0x10
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#define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
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#define DCT_FLAG_EXT_HC_SIFS 0x20
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#define DCT_FLAG_EXT_HC_PIFS 0x40
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#define TX_RX_TYPE_MASK 0xFF
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#define TX_FRAME_TYPE 0x00
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#define TX_HOST_COMMAND_TYPE 0x01
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#define RX_FRAME_TYPE 0x09
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#define RX_HOST_NOTIFICATION_TYPE 0x03
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#define RX_HOST_CMD_RESPONSE_TYPE 0x04
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#define RX_TX_FRAME_RESPONSE_TYPE 0x05
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#define TFD_NEED_IRQ_MASK 0x04
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#define HOST_CMD_DINO_CONFIG 30
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#define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
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#define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
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#define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
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#define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
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#define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
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#define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
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#define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
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#define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
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#define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
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#define HOST_NOTIFICATION_TX_STATUS 19
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#define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
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#define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
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#define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
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#define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
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#define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
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#define HOST_NOTIFICATION_NOISE_STATS 25
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#define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
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#define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
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#define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
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#define IPW_MB_SCAN_CANCEL_THRESHOLD 3
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#define IPW_MB_ROAMING_THRESHOLD_MIN 1
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#define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
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#define IPW_MB_ROAMING_THRESHOLD_MAX 30
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#define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 3*IPW_MB_ROAMING_THRESHOLD_DEFAULT
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#define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
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#define MACADRR_BYTE_LEN 6
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#define DCR_TYPE_AP 0x01
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#define DCR_TYPE_WLAP 0x02
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#define DCR_TYPE_MU_ESS 0x03
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#define DCR_TYPE_MU_IBSS 0x04
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#define DCR_TYPE_MU_PIBSS 0x05
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#define DCR_TYPE_SNIFFER 0x06
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#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
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/* QoS definitions */
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#define CW_MIN_OFDM 15
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#define CW_MAX_OFDM 1023
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#define CW_MIN_CCK 31
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#define CW_MAX_CCK 1023
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#define QOS_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
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#define QOS_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
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#define QOS_TX2_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
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#define QOS_TX3_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/4 - 1)
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#define QOS_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
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#define QOS_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
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#define QOS_TX2_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
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#define QOS_TX3_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/4 - 1)
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#define QOS_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
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#define QOS_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
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#define QOS_TX2_CW_MAX_OFDM cpu_to_le16(CW_MIN_OFDM)
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#define QOS_TX3_CW_MAX_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
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#define QOS_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
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#define QOS_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
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#define QOS_TX2_CW_MAX_CCK cpu_to_le16(CW_MIN_CCK)
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#define QOS_TX3_CW_MAX_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
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#define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)
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#define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)
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#define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)
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#define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)
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#define QOS_TX0_ACM 0
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#define QOS_TX1_ACM 0
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#define QOS_TX2_ACM 0
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#define QOS_TX3_ACM 0
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#define QOS_TX0_TXOP_LIMIT_CCK 0
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#define QOS_TX1_TXOP_LIMIT_CCK 0
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#define QOS_TX2_TXOP_LIMIT_CCK cpu_to_le16(6016)
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#define QOS_TX3_TXOP_LIMIT_CCK cpu_to_le16(3264)
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#define QOS_TX0_TXOP_LIMIT_OFDM 0
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#define QOS_TX1_TXOP_LIMIT_OFDM 0
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#define QOS_TX2_TXOP_LIMIT_OFDM cpu_to_le16(3008)
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#define QOS_TX3_TXOP_LIMIT_OFDM cpu_to_le16(1504)
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#define DEF_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
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#define DEF_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
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#define DEF_TX2_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
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#define DEF_TX3_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
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#define DEF_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
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#define DEF_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
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#define DEF_TX2_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
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#define DEF_TX3_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
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#define DEF_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
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#define DEF_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
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#define DEF_TX2_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
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#define DEF_TX3_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
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#define DEF_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
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#define DEF_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
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#define DEF_TX2_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
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#define DEF_TX3_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
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#define DEF_TX0_AIFS 0
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#define DEF_TX1_AIFS 0
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#define DEF_TX2_AIFS 0
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#define DEF_TX3_AIFS 0
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#define DEF_TX0_ACM 0
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#define DEF_TX1_ACM 0
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#define DEF_TX2_ACM 0
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#define DEF_TX3_ACM 0
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#define DEF_TX0_TXOP_LIMIT_CCK 0
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#define DEF_TX1_TXOP_LIMIT_CCK 0
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#define DEF_TX2_TXOP_LIMIT_CCK 0
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#define DEF_TX3_TXOP_LIMIT_CCK 0
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#define DEF_TX0_TXOP_LIMIT_OFDM 0
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#define DEF_TX1_TXOP_LIMIT_OFDM 0
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#define DEF_TX2_TXOP_LIMIT_OFDM 0
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#define DEF_TX3_TXOP_LIMIT_OFDM 0
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#define QOS_QOS_SETS 3
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#define QOS_PARAM_SET_ACTIVE 0
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#define QOS_PARAM_SET_DEF_CCK 1
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#define QOS_PARAM_SET_DEF_OFDM 2
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#define CTRL_QOS_NO_ACK (0x0020)
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#define IPW_TX_QUEUE_1 1
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#define IPW_TX_QUEUE_2 2
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#define IPW_TX_QUEUE_3 3
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#define IPW_TX_QUEUE_4 4
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struct ipw_qos_info {
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struct libipw_qos_parameters *def_qos_parm_OFDM;
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struct libipw_qos_parameters *def_qos_parm_CCK;
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u32 burst_duration_CCK;
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u32 burst_duration_OFDM;
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/**************************************************************/
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* Generic queue structure
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* Contains common data for Rx and Tx queues
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int n_bd; /**< number of BDs in this queue */
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int first_empty; /**< 1-st empty entry (index) */
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int last_used; /**< last used entry (index) */
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u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
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u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
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dma_addr_t dma_addr; /**< physical addr for BD's */
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int low_mark; /**< low watermark, resume queue if free space more than this */
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int high_mark; /**< high watermark, stop queue if free space less than this */
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} __packed; /* XXX */
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__le16 duration; // watch out for endians!
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u8 addr1[MACADRR_BYTE_LEN];
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u8 addr2[MACADRR_BYTE_LEN];
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u8 addr3[MACADRR_BYTE_LEN];
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__le16 seq_ctrl; // more endians!
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u8 addr4[MACADRR_BYTE_LEN];
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__le16 duration; // watch out for endians!
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u8 addr1[MACADRR_BYTE_LEN];
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u8 addr2[MACADRR_BYTE_LEN];
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u8 addr3[MACADRR_BYTE_LEN];
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__le16 seq_ctrl; // more endians!
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u8 addr4[MACADRR_BYTE_LEN];
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__le16 duration; // watch out for endians!
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u8 addr1[MACADRR_BYTE_LEN];
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u8 addr2[MACADRR_BYTE_LEN];
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u8 addr3[MACADRR_BYTE_LEN];
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__le16 seq_ctrl; // more endians!
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__le16 duration; // watch out for endians!
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u8 addr1[MACADRR_BYTE_LEN];
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u8 addr2[MACADRR_BYTE_LEN];
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u8 addr3[MACADRR_BYTE_LEN];
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__le16 seq_ctrl; // more endians!
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// TX TFD with 32 byte MAC Header
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struct machdr32 mchdr; // 32
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__le32 uivplaceholder[2]; // 8
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// TX TFD with 30 byte MAC Header
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struct machdr30 mchdr; // 30
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__le32 uivplaceholder[2]; // 8
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// tx tfd with 26 byte mac header
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struct machdr26 mchdr; // 26
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u8 reserved1[2]; // 2
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__le32 uivplaceholder[2]; // 8
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u8 reserved2[4]; // 4
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// tx tfd with 24 byte mac header
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struct machdr24 mchdr; // 24
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__le32 uivplaceholder[2]; // 8
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#define DCT_WEP_KEY_FIELD_LENGTH 16
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__le32 work_area_ptr;
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u8 station_number; /* 0 for BSS */
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u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
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__le16 next_packet_duration;
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__le16 next_frag_len;
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__le16 back_off_counter; //////txop;
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/* 802.11 MAC Header */
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struct tx_tfd_24 tfd_24;
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struct tx_tfd_26 tfd_26;
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struct tx_tfd_30 tfd_30;
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struct tx_tfd_32 tfd_32;
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/* Payload DMA info */
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__le32 chunk_ptr[NUM_TFD_CHUNKS];
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__le16 chunk_len[NUM_TFD_CHUNKS];
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struct txrx_control_flags {
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#define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
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struct txrx_control_flags control_flags;
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struct tfd_data data;
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struct tfd_command cmd;
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u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
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typedef void destructor_func(const void *);
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* Tx Queue for DMA. Queue consists of circular buffer of
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* BD's and required locking structures.
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struct clx2_tx_queue {
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struct tfd_frame *bd;
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struct libipw_txb **txb;
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* RX related structures and functions
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#define RX_FREE_BUFFERS 32
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#define RX_LOW_WATERMARK 8
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#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
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#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
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#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
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// Used for passing to driver number of successes and failures per rate
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struct rate_histogram {
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__le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
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__le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
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__le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
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__le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
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__le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
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__le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
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/* statistics command response */
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struct ipw_cmd_stats {
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__le16 bad_mac_header;
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__le16 reserved_frame_types;
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__le16 long_distance_ina_fina;
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__le16 dsp_silence_unreachable;
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__le16 accumulated_rssi;
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__le16 rx_ovfl_frame_tossed;
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__le16 rssi_silence_threshold;
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__le16 rx_ovfl_frame_supplied;
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__le16 last_rx_frame_signal;
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__le16 last_rx_frame_noise;
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__le16 rx_autodetec_no_ofdm;
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__le16 rx_autodetec_no_barker;
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struct notif_channel_result {
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struct ipw_cmd_stats stats;
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#define SCAN_COMPLETED_STATUS_COMPLETE 1
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#define SCAN_COMPLETED_STATUS_ABORTED 2
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struct notif_scan_complete {
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struct notif_frag_length {
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struct notif_beacon_state {
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struct notif_tgi_tx_key {
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#define SILENCE_OVER_THRESH (1)
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#define SILENCE_UNDER_THRESH (2)
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struct notif_link_deterioration {
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struct ipw_cmd_stats stats;
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struct rate_histogram histogram;
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u8 silence_notification_type; /* SILENCE_OVER/UNDER_THRESH */
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__le16 silence_count;
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struct notif_association {
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struct notif_authenticate {
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struct machdr24 addr;
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struct notif_calibration {
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struct ipw_rx_notification {
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struct notif_association assoc;
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struct notif_authenticate auth;
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struct notif_channel_result channel_result;
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struct notif_scan_complete scan_complete;
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struct notif_frag_length frag_len;
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struct notif_beacon_state beacon_state;
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struct notif_tgi_tx_key tgi_tx_key;
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struct notif_link_deterioration link_deterioration;
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struct notif_calibration calibration;
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struct notif_noise noise;
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struct ipw_rx_frame {
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u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
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u8 received_channel; // The channel that this frame was received on.
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// Note that for .11b this does not have to be
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// the same as the channel that it was sent.
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u8 control; // control bit should be on in bg
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u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
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u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
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struct ipw_rx_header {
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struct ipw_rx_packet {
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struct ipw_rx_header header;
708
struct ipw_rx_frame frame;
709
struct ipw_rx_notification notification;
713
#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
714
#define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \
715
sizeof(struct ipw_rx_frame))
717
struct ipw_rx_mem_buffer {
720
struct list_head list;
721
}; /* Not transferred over network, so not __packed */
723
struct ipw_rx_queue {
724
struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
725
struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
726
u32 processed; /* Internal index to last handled Rx packet */
727
u32 read; /* Shared index to newest available Rx buffer */
728
u32 write; /* Shared index to oldest written Rx packet */
729
u32 free_count; /* Number of pre-allocated buffers in rx_free */
730
/* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
731
struct list_head rx_free; /* Own an SKBs */
732
struct list_head rx_used; /* No SKB allocated */
734
}; /* Not transferred over network, so not __packed */
736
struct alive_command_responce {
739
__le16 software_revision;
740
u8 device_identifier;
744
__le16 clock_settle_time;
745
__le16 powerup_settle_time;
747
u8 time_stamp[5]; /* month, day, year, hours, minutes */
751
#define IPW_MAX_RATES 12
755
u8 rates[IPW_MAX_RATES];
758
struct command_block {
759
unsigned int control;
765
#define CB_NUMBER_OF_ELEMENTS_SMALL 64
766
struct fw_image_desc {
767
unsigned long last_cb_index;
768
unsigned long current_cb_index;
769
struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
771
unsigned long p_addr;
775
struct ipw_sys_config {
778
u8 answer_broadcast_ssid_probe;
779
u8 accept_all_data_frames;
780
u8 accept_non_directed_frames;
781
u8 exclude_unicast_unencrypted;
782
u8 disable_unicast_decryption;
783
u8 exclude_multicast_unencrypted;
784
u8 disable_multicast_decryption;
785
u8 antenna_diversity;
787
u8 dot11g_auto_detection;
788
u8 enable_cts_to_self;
789
u8 enable_multicast_filtering;
790
u8 bt_coexist_collision_thr;
791
u8 silence_threshold;
792
u8 accept_all_mgmt_bcpr;
793
u8 accept_all_mgmt_frames;
794
u8 pass_noise_stats_to_host;
798
struct ipw_multicast_addr {
799
u8 num_of_multicast_addresses;
807
#define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
808
#define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
810
#define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
811
#define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
812
#define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
814
#define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
815
#define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
816
#define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
817
#define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
818
//#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
828
struct ipw_tgi_tx_key {
834
__le32 tx_counter[2];
837
#define IPW_SCAN_CHANNELS 54
839
struct ipw_scan_request {
842
u8 channels_list[IPW_SCAN_CHANNELS];
843
u8 channels_reserved[3];
847
IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
848
IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
849
IPW_SCAN_ACTIVE_DIRECT_SCAN,
850
IPW_SCAN_ACTIVE_BROADCAST_SCAN,
851
IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
855
struct ipw_scan_request_ext {
856
__le32 full_scan_index;
857
u8 channels_list[IPW_SCAN_CHANNELS];
858
u8 scan_type[IPW_SCAN_CHANNELS / 2];
860
__le16 dwell_time[IPW_SCAN_TYPES];
863
static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
866
return scan->scan_type[index / 2] & 0x0F;
868
return (scan->scan_type[index / 2] & 0xF0) >> 4;
871
static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
872
u8 index, u8 scan_type)
875
scan->scan_type[index / 2] =
876
(scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
878
scan->scan_type[index / 2] =
879
(scan->scan_type[index / 2] & 0x0F) |
880
((scan_type & 0x0F) << 4);
883
struct ipw_associate {
885
#ifdef __LITTLE_ENDIAN_BITFIELD
886
u8 auth_type:4, auth_key:4;
888
u8 auth_key:4, auth_type:4;
892
__le16 policy_support;
896
__le32 assoc_tsf_msw;
897
__le32 assoc_tsf_lsw;
899
__le16 listen_interval;
900
__le16 beacon_interval;
908
struct ipw_supported_rates {
913
u8 supported_rates[IPW_MAX_RATES];
916
struct ipw_rts_threshold {
917
__le16 rts_threshold;
921
struct ipw_frag_threshold {
922
__le16 frag_threshold;
926
struct ipw_retry_limit {
927
u8 short_retry_limit;
932
struct ipw_dino_config {
933
__le32 dino_config_addr;
934
__le16 dino_config_size;
939
struct ipw_aironet_info {
951
u8 station_address[6];
956
struct ipw_country_channel_info {
962
struct ipw_country_info {
965
u8 country_str[IEEE80211_COUNTRY_STRING_LEN];
966
struct ipw_country_channel_info groups[7];
969
struct ipw_channel_tx_power {
974
#define SCAN_ASSOCIATED_INTERVAL (HZ)
975
#define SCAN_INTERVAL (HZ / 10)
976
#define MAX_A_CHANNELS 37
977
#define MAX_B_CHANNELS 14
979
struct ipw_tx_power {
982
struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
985
struct ipw_rsn_capabilities {
991
struct ipw_sensitivity_calib {
992
__le16 beacon_rssi_raw;
997
* Host command structure.
999
* On input, the following fields should be filled:
1003
* - param (if needed)
1006
* - \a status contains status;
1007
* - \a param filled with status parameters.
1009
struct ipw_cmd { /* XXX */
1010
u32 cmd; /**< Host command */
1011
u32 status;/**< Status */
1013
/**< How many 32 bit parameters in the status */
1014
u32 len; /**< incoming parameters length, bytes */
1016
* command parameters.
1017
* There should be enough space for incoming and
1018
* outcoming parameters.
1019
* Incoming parameters listed 1-st, followed by outcoming params.
1020
* nParams=(len+3)/4+status_len
1025
#define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
1027
#define STATUS_INT_ENABLED (1<<1)
1028
#define STATUS_RF_KILL_HW (1<<2)
1029
#define STATUS_RF_KILL_SW (1<<3)
1030
#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
1032
#define STATUS_INIT (1<<5)
1033
#define STATUS_AUTH (1<<6)
1034
#define STATUS_ASSOCIATED (1<<7)
1035
#define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
1037
#define STATUS_ASSOCIATING (1<<8)
1038
#define STATUS_DISASSOCIATING (1<<9)
1039
#define STATUS_ROAMING (1<<10)
1040
#define STATUS_EXIT_PENDING (1<<11)
1041
#define STATUS_DISASSOC_PENDING (1<<12)
1042
#define STATUS_STATE_PENDING (1<<13)
1044
#define STATUS_DIRECT_SCAN_PENDING (1<<19)
1045
#define STATUS_SCAN_PENDING (1<<20)
1046
#define STATUS_SCANNING (1<<21)
1047
#define STATUS_SCAN_ABORTING (1<<22)
1048
#define STATUS_SCAN_FORCED (1<<23)
1050
#define STATUS_LED_LINK_ON (1<<24)
1051
#define STATUS_LED_ACT_ON (1<<25)
1053
#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
1054
#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
1055
#define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
1057
#define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
1059
#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
1060
#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
1061
#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
1062
#define CFG_CUSTOM_MAC (1<<3)
1063
#define CFG_PREAMBLE_LONG (1<<4)
1064
#define CFG_ADHOC_PERSIST (1<<5)
1065
#define CFG_ASSOCIATE (1<<6)
1066
#define CFG_FIXED_RATE (1<<7)
1067
#define CFG_ADHOC_CREATE (1<<8)
1068
#define CFG_NO_LED (1<<9)
1069
#define CFG_BACKGROUND_SCAN (1<<10)
1070
#define CFG_SPEED_SCAN (1<<11)
1071
#define CFG_NET_STATS (1<<12)
1073
#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
1074
#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
1076
#define MAX_STATIONS 32
1077
#define IPW_INVALID_STATION (0xff)
1079
struct ipw_station_entry {
1080
u8 mac_addr[ETH_ALEN];
1085
#define AVG_ENTRIES 8
1087
s16 entries[AVG_ENTRIES];
1093
#define MAX_SPEED_SCAN 100
1094
#define IPW_IBSS_MAC_HASH_SIZE 31
1096
struct ipw_ibss_seq {
1100
unsigned long packet_time;
1101
struct list_head list;
1104
struct ipw_error_elem { /* XXX */
1114
struct ipw_event { /* XXX */
1120
struct ipw_fw_error { /* XXX */
1121
unsigned long jiffies;
1126
struct ipw_error_elem *elem;
1127
struct ipw_event *log;
1131
#ifdef CONFIG_IPW2200_PROMISCUOUS
1133
enum ipw_prom_filter {
1134
IPW_PROM_CTL_HEADER_ONLY = (1 << 0),
1135
IPW_PROM_MGMT_HEADER_ONLY = (1 << 1),
1136
IPW_PROM_DATA_HEADER_ONLY = (1 << 2),
1137
IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */
1138
IPW_PROM_NO_TX = (1 << 4),
1139
IPW_PROM_NO_RX = (1 << 5),
1140
IPW_PROM_NO_CTL = (1 << 6),
1141
IPW_PROM_NO_MGMT = (1 << 7),
1142
IPW_PROM_NO_DATA = (1 << 8),
1146
struct ipw_prom_priv {
1147
struct ipw_priv *priv;
1148
struct libipw_device *ieee;
1149
enum ipw_prom_filter filter;
1155
#if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS)
1156
/* Magic struct that slots into the radiotap header -- no reason
1157
* to build this manually element by element, we can write it much
1158
* more efficiently than we can parse it. ORDER MATTERS HERE
1160
* When sent to us via the simulated Rx interface in sysfs, the entire
1161
* structure is provided regardless of any bits unset.
1164
struct ieee80211_radiotap_header rt_hdr;
1165
u64 rt_tsf; /* TSF */ /* XXX */
1166
u8 rt_flags; /* radiotap packet flags */
1167
u8 rt_rate; /* rate in 500kb/s */
1168
__le16 rt_channel; /* channel in mhz */
1169
__le16 rt_chbitmask; /* channel bitfield */
1170
s8 rt_dbmsignal; /* signal in dbM, kluged to signed */
1172
u8 rt_antenna; /* antenna number */
1173
u8 payload[0]; /* payload... */
1178
/* ieee device used by generic ieee processing code */
1179
struct libipw_device *ieee;
1182
spinlock_t irq_lock;
1185
/* basic pci-network driver stuff */
1186
struct pci_dev *pci_dev;
1187
struct net_device *net_dev;
1189
#ifdef CONFIG_IPW2200_PROMISCUOUS
1190
/* Promiscuous mode */
1191
struct ipw_prom_priv *prom_priv;
1192
struct net_device *prom_net_dev;
1195
/* pci hardware address support */
1196
void __iomem *hw_base;
1197
unsigned long hw_len;
1199
struct fw_image_desc sram_desc;
1201
/* result of ucode download */
1202
struct alive_command_responce dino_alive;
1204
wait_queue_head_t wait_command_queue;
1205
wait_queue_head_t wait_state;
1207
/* Rx and Tx DMA processing queues */
1208
struct ipw_rx_queue *rxq;
1209
struct clx2_tx_queue txq_cmd;
1210
struct clx2_tx_queue txq[4];
1215
struct average average_missed_beacons;
1219
int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1220
int rx_pend_max; /**< maximum pending buffers for one IRQ */
1221
u32 hcmd_seq; /**< sequence number for hcmd */
1222
u32 disassociate_threshold;
1223
u32 roaming_threshold;
1225
struct ipw_associate assoc_request;
1226
struct libipw_network *assoc_network;
1228
unsigned long ts_scan_abort;
1229
struct ipw_supported_rates rates;
1230
struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1231
struct ipw_rates supp; /**< software defined */
1232
struct ipw_rates extended; /**< use for corresp. IE, AP only */
1234
struct notif_link_deterioration last_link_deterioration; /** for statistics */
1235
struct ipw_cmd *hcmd; /**< host command currently executed */
1237
wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1238
u32 tsf_bcn[2]; /**< TSF from latest beacon */
1240
struct notif_calibration calib; /**< last calibration */
1242
/* ordinal interface with firmware */
1250
/* context information */
1251
u8 essid[IW_ESSID_MAX_SIZE];
1253
u8 nick[IW_ESSID_MAX_SIZE];
1256
struct ipw_sys_config sys_config;
1260
u8 mac_addr[ETH_ALEN];
1262
u8 stations[MAX_STATIONS][ETH_ALEN];
1263
u8 short_retry_limit;
1264
u8 long_retry_limit;
1266
u32 notif_missed_beacons;
1268
/* Statistics and counters normalized with each association */
1269
u32 last_missed_beacons;
1270
u32 last_tx_packets;
1271
u32 last_rx_packets;
1272
u32 last_tx_failures;
1276
u32 missed_adhoc_beacons;
1282
u8 speed_scan[MAX_SPEED_SCAN];
1287
unsigned long last_packet_time;
1288
struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];
1291
u8 eeprom[0x100]; /* 256 bytes of eeprom */
1295
struct iw_statistics wstats;
1297
struct iw_public_data wireless_data;
1299
int user_requested_scan;
1300
u8 direct_scan_ssid[IW_ESSID_MAX_SIZE];
1301
u8 direct_scan_ssid_len;
1303
struct delayed_work adhoc_check;
1304
struct work_struct associate;
1305
struct work_struct disassociate;
1306
struct work_struct system_config;
1307
struct work_struct rx_replenish;
1308
struct delayed_work request_scan;
1309
struct delayed_work request_direct_scan;
1310
struct delayed_work request_passive_scan;
1311
struct delayed_work scan_event;
1312
struct work_struct adapter_restart;
1313
struct delayed_work rf_kill;
1314
struct work_struct up;
1315
struct work_struct down;
1316
struct delayed_work gather_stats;
1317
struct work_struct abort_scan;
1318
struct work_struct roam;
1319
struct delayed_work scan_check;
1320
struct work_struct link_up;
1321
struct work_struct link_down;
1323
struct tasklet_struct irq_tasklet;
1325
/* LED related variables and work_struct */
1327
u32 led_activity_on;
1328
u32 led_activity_off;
1329
u32 led_association_on;
1330
u32 led_association_off;
1334
struct delayed_work led_link_on;
1335
struct delayed_work led_link_off;
1336
struct delayed_work led_act_off;
1337
struct work_struct merge_networks;
1339
struct ipw_cmd_log *cmdlog;
1343
#define IPW_2200BG 1
1344
#define IPW_2915ABG 2
1349
/* Track time in suspend */
1350
unsigned long suspend_at;
1351
unsigned long suspend_time;
1357
struct ipw_fw_error *error;
1361
/* Used to pass the current INTA value from ISR to Tasklet */
1365
struct ipw_qos_info qos_data;
1366
struct work_struct qos_activate;
1367
/*********************************/
1369
/* debugging info */
1377
/* Debug and printf string expansion helpers for printing bitfields */
1378
#define BIT_FMT8 "%c%c%c%c-%c%c%c%c"
1379
#define BIT_FMT16 BIT_FMT8 ":" BIT_FMT8
1380
#define BIT_FMT32 BIT_FMT16 " " BIT_FMT16
1382
#define BITC(x,y) (((x>>y)&1)?'1':'0')
1383
#define BIT_ARG8(x) \
1384
BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\
1385
BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)
1387
#define BIT_ARG16(x) \
1388
BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\
1389
BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\
1392
#define BIT_ARG32(x) \
1393
BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\
1394
BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\
1395
BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\
1396
BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\
1400
#define IPW_DEBUG(level, fmt, args...) \
1401
do { if (ipw_debug_level & (level)) \
1402
printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1403
in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1405
#ifdef CONFIG_IPW2200_DEBUG
1406
#define IPW_LL_DEBUG(level, fmt, args...) \
1407
do { if (ipw_debug_level & (level)) \
1408
printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1409
in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1411
#define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)
1412
#endif /* CONFIG_IPW2200_DEBUG */
1415
* To use the debug system;
1417
* If you are defining a new debug classification, simply add it to the #define
1418
* list here in the form of:
1420
* #define IPW_DL_xxxx VALUE
1422
* shifting value to the left one bit from the previous entry. xxxx should be
1423
* the name of the classification (for example, WEP)
1425
* You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1426
* classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1427
* to send output to that classification.
1429
* To add your debug level to the list of levels seen when you perform
1431
* % cat /proc/net/ipw/debug_level
1433
* you simply need to add your entry to the ipw_debug_levels array.
1435
* If you do not see debug_level in /proc/net/ipw then you do not have
1436
* CONFIG_IPW2200_DEBUG defined in your kernel configuration
1440
#define IPW_DL_ERROR (1<<0)
1441
#define IPW_DL_WARNING (1<<1)
1442
#define IPW_DL_INFO (1<<2)
1443
#define IPW_DL_WX (1<<3)
1444
#define IPW_DL_HOST_COMMAND (1<<5)
1445
#define IPW_DL_STATE (1<<6)
1447
#define IPW_DL_NOTIF (1<<10)
1448
#define IPW_DL_SCAN (1<<11)
1449
#define IPW_DL_ASSOC (1<<12)
1450
#define IPW_DL_DROP (1<<13)
1451
#define IPW_DL_IOCTL (1<<14)
1453
#define IPW_DL_MANAGE (1<<15)
1454
#define IPW_DL_FW (1<<16)
1455
#define IPW_DL_RF_KILL (1<<17)
1456
#define IPW_DL_FW_ERRORS (1<<18)
1458
#define IPW_DL_LED (1<<19)
1460
#define IPW_DL_ORD (1<<20)
1462
#define IPW_DL_FRAG (1<<21)
1463
#define IPW_DL_WEP (1<<22)
1464
#define IPW_DL_TX (1<<23)
1465
#define IPW_DL_RX (1<<24)
1466
#define IPW_DL_ISR (1<<25)
1467
#define IPW_DL_FW_INFO (1<<26)
1468
#define IPW_DL_IO (1<<27)
1469
#define IPW_DL_TRACE (1<<28)
1471
#define IPW_DL_STATS (1<<29)
1472
#define IPW_DL_MERGE (1<<30)
1473
#define IPW_DL_QOS (1<<31)
1475
#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1476
#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1477
#define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1479
#define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1480
#define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1481
#define IPW_DEBUG_TRACE(f, a...) IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a)
1482
#define IPW_DEBUG_RX(f, a...) IPW_LL_DEBUG(IPW_DL_RX, f, ## a)
1483
#define IPW_DEBUG_TX(f, a...) IPW_LL_DEBUG(IPW_DL_TX, f, ## a)
1484
#define IPW_DEBUG_ISR(f, a...) IPW_LL_DEBUG(IPW_DL_ISR, f, ## a)
1485
#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1486
#define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a)
1487
#define IPW_DEBUG_WEP(f, a...) IPW_LL_DEBUG(IPW_DL_WEP, f, ## a)
1488
#define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1489
#define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a)
1490
#define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a)
1491
#define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1492
#define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1493
#define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a)
1494
#define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a)
1495
#define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a)
1496
#define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1497
#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1498
#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1499
#define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a)
1500
#define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a)
1501
#define IPW_DEBUG_QOS(f, a...) IPW_LL_DEBUG(IPW_DL_QOS, f, ## a)
1503
#include <linux/ctype.h>
1506
* Register bit definitions
1509
#define IPW_INTA_RW 0x00000008
1510
#define IPW_INTA_MASK_R 0x0000000C
1511
#define IPW_INDIRECT_ADDR 0x00000010
1512
#define IPW_INDIRECT_DATA 0x00000014
1513
#define IPW_AUTOINC_ADDR 0x00000018
1514
#define IPW_AUTOINC_DATA 0x0000001C
1515
#define IPW_RESET_REG 0x00000020
1516
#define IPW_GP_CNTRL_RW 0x00000024
1518
#define IPW_READ_INT_REGISTER 0xFF4
1520
#define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
1522
#define IPW_REGISTER_DOMAIN1_END 0x00001000
1523
#define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
1525
#define IPW_SHARED_LOWER_BOUND 0x00000200
1526
#define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1528
#define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
1529
#define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
1531
#define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1532
#define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1533
#define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1536
* RESET Register Bit Indexes
1538
#define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1539
#define IPW_START_STANDBY (1<<2)
1540
#define IPW_ACTIVITY_LED (1<<4)
1541
#define IPW_ASSOCIATED_LED (1<<5)
1542
#define IPW_OFDM_LED (1<<6)
1543
#define IPW_RESET_REG_SW_RESET (1<<7)
1544
#define IPW_RESET_REG_MASTER_DISABLED (1<<8)
1545
#define IPW_RESET_REG_STOP_MASTER (1<<9)
1546
#define IPW_GATE_ODMA (1<<25)
1547
#define IPW_GATE_IDMA (1<<26)
1548
#define IPW_ARC_KESHET_CONFIG (1<<27)
1549
#define IPW_GATE_ADMA (1<<29)
1551
#define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1552
#define IPW_DOMAIN_0_END 0x1000
1553
#define CLX_MEM_BAR_SIZE 0x1000
1555
/* Dino/baseband control registers bits */
1557
#define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
1558
#define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
1559
#define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
1560
#define IPW_BASEBAND_CONTROL_STATUS 0X00200000
1561
#define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
1562
#define IPW_BASEBAND_RX_FIFO_READ 0X00200004
1563
#define IPW_BASEBAND_CONTROL_STORE 0X00200010
1565
#define IPW_INTERNAL_CMD_EVENT 0X00300004
1566
#define IPW_BASEBAND_POWER_DOWN 0x00000001
1568
#define IPW_MEM_HALT_AND_RESET 0x003000e0
1570
/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1571
#define IPW_BIT_HALT_RESET_ON 0x80000000
1572
#define IPW_BIT_HALT_RESET_OFF 0x00000000
1574
#define CB_LAST_VALID 0x20000000
1575
#define CB_INT_ENABLED 0x40000000
1576
#define CB_VALID 0x80000000
1577
#define CB_SRC_LE 0x08000000
1578
#define CB_DEST_LE 0x04000000
1579
#define CB_SRC_AUTOINC 0x00800000
1580
#define CB_SRC_IO_GATED 0x00400000
1581
#define CB_DEST_AUTOINC 0x00080000
1582
#define CB_SRC_SIZE_LONG 0x00200000
1583
#define CB_DEST_SIZE_LONG 0x00020000
1587
#define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1588
#define DMA_CB_STOP_AND_ABORT 0x00000C00
1589
#define DMA_CB_START 0x00000100
1591
#define IPW_SHARED_SRAM_SIZE 0x00030000
1592
#define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
1593
#define CB_MAX_LENGTH 0x1FFF
1595
#define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1596
#define IPW_EEPROM_IMAGE_SIZE 0x100
1599
#define IPW_DMA_I_CURRENT_CB 0x003000D0
1600
#define IPW_DMA_O_CURRENT_CB 0x003000D4
1601
#define IPW_DMA_I_DMA_CONTROL 0x003000A4
1602
#define IPW_DMA_I_CB_BASE 0x003000A0
1604
#define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
1605
#define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
1606
#define IPW_TX_QUEUE_0_BD_BASE 0x00000208
1607
#define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
1608
#define IPW_TX_QUEUE_1_BD_BASE 0x00000210
1609
#define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
1610
#define IPW_TX_QUEUE_2_BD_BASE 0x00000218
1611
#define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
1612
#define IPW_TX_QUEUE_3_BD_BASE 0x00000220
1613
#define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
1614
#define IPW_RX_BD_BASE 0x00000240
1615
#define IPW_RX_BD_SIZE 0x00000244
1616
#define IPW_RFDS_TABLE_LOWER 0x00000500
1618
#define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
1619
#define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
1620
#define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
1621
#define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
1622
#define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
1623
#define IPW_RX_READ_INDEX (0x000002A0)
1625
#define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1626
#define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1627
#define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1628
#define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1629
#define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1630
#define IPW_RX_WRITE_INDEX (0x00000FA0)
1633
* EEPROM Related Definitions
1636
#define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1637
#define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
1638
#define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
1639
#define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
1640
#define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
1642
#define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
1643
#define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
1644
#define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
1645
#define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
1646
#define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
1647
#define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
1651
#define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1653
#define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1654
( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1656
/* EEPROM access by BYTE */
1657
#define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1658
#define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1659
#define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1660
#define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1661
#define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1662
#define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1663
#define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1664
#define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1665
#define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1666
#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1668
/* NIC type as found in the one byte EEPROM_NIC_TYPE offset */
1669
#define EEPROM_NIC_TYPE_0 0
1670
#define EEPROM_NIC_TYPE_1 1
1671
#define EEPROM_NIC_TYPE_2 2
1672
#define EEPROM_NIC_TYPE_3 3
1673
#define EEPROM_NIC_TYPE_4 4
1675
/* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */
1676
#define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
1677
#define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
1678
#define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
1680
#define FW_MEM_REG_LOWER_BOUND 0x00300000
1681
#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1682
#define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
1683
#define EEPROM_BIT_SK (1<<0)
1684
#define EEPROM_BIT_CS (1<<1)
1685
#define EEPROM_BIT_DI (1<<2)
1686
#define EEPROM_BIT_DO (1<<4)
1688
#define EEPROM_CMD_READ 0x2
1690
/* Interrupts masks */
1691
#define IPW_INTA_NONE 0x00000000
1693
#define IPW_INTA_BIT_RX_TRANSFER 0x00000002
1694
#define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
1695
#define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1698
#define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
1699
#define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
1700
#define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
1701
#define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
1702
#define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
1704
#define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1706
#define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1707
#define IPW_INTA_BIT_POWER_DOWN 0x00200000
1709
#define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1710
#define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1711
#define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
1712
#define IPW_INTA_BIT_FATAL_ERROR 0x40000000
1713
#define IPW_INTA_BIT_PARITY_ERROR 0x80000000
1715
/* Interrupts enabled at init time. */
1716
#define IPW_INTA_MASK_ALL \
1717
(IPW_INTA_BIT_TX_QUEUE_1 | \
1718
IPW_INTA_BIT_TX_QUEUE_2 | \
1719
IPW_INTA_BIT_TX_QUEUE_3 | \
1720
IPW_INTA_BIT_TX_QUEUE_4 | \
1721
IPW_INTA_BIT_TX_CMD_QUEUE | \
1722
IPW_INTA_BIT_RX_TRANSFER | \
1723
IPW_INTA_BIT_FATAL_ERROR | \
1724
IPW_INTA_BIT_PARITY_ERROR | \
1725
IPW_INTA_BIT_STATUS_CHANGE | \
1726
IPW_INTA_BIT_FW_INITIALIZATION_DONE | \
1727
IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1728
IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1729
IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1730
IPW_INTA_BIT_POWER_DOWN | \
1731
IPW_INTA_BIT_RF_KILL_DONE )
1733
/* FW event log definitions */
1734
#define EVENT_ELEM_SIZE (3 * sizeof(u32))
1735
#define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1737
/* FW error log definitions */
1738
#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1739
#define ERROR_START_OFFSET (1 * sizeof(u32))
1741
/* TX power level (dbm) */
1742
#define IPW_TX_POWER_MIN -12
1743
#define IPW_TX_POWER_MAX 20
1744
#define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX
1747
IPW_FW_ERROR_OK = 0,
1749
IPW_FW_ERROR_MEMORY_UNDERFLOW,
1750
IPW_FW_ERROR_MEMORY_OVERFLOW,
1751
IPW_FW_ERROR_BAD_PARAM,
1752
IPW_FW_ERROR_BAD_CHECKSUM,
1753
IPW_FW_ERROR_NMI_INTERRUPT,
1754
IPW_FW_ERROR_BAD_DATABASE,
1755
IPW_FW_ERROR_ALLOC_FAIL,
1756
IPW_FW_ERROR_DMA_UNDERRUN,
1757
IPW_FW_ERROR_DMA_STATUS,
1758
IPW_FW_ERROR_DINO_ERROR,
1759
IPW_FW_ERROR_EEPROM_ERROR,
1760
IPW_FW_ERROR_SYSASSERT,
1761
IPW_FW_ERROR_FATAL_ERROR
1765
#define AUTH_SHARED_KEY 1
1767
#define AUTH_IGNORE 3
1769
#define HC_ASSOCIATE 0
1770
#define HC_REASSOCIATE 1
1771
#define HC_DISASSOCIATE 2
1772
#define HC_IBSS_START 3
1773
#define HC_IBSS_RECONF 4
1774
#define HC_DISASSOC_QUIET 5
1776
#define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01)
1778
#define IPW_RATE_CAPABILITIES 1
1779
#define IPW_RATE_CONNECT 0
1782
* Rate values and masks
1784
#define IPW_TX_RATE_1MB 0x0A
1785
#define IPW_TX_RATE_2MB 0x14
1786
#define IPW_TX_RATE_5MB 0x37
1787
#define IPW_TX_RATE_6MB 0x0D
1788
#define IPW_TX_RATE_9MB 0x0F
1789
#define IPW_TX_RATE_11MB 0x6E
1790
#define IPW_TX_RATE_12MB 0x05
1791
#define IPW_TX_RATE_18MB 0x07
1792
#define IPW_TX_RATE_24MB 0x09
1793
#define IPW_TX_RATE_36MB 0x0B
1794
#define IPW_TX_RATE_48MB 0x01
1795
#define IPW_TX_RATE_54MB 0x03
1797
#define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1798
#define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1800
#define IPW_ORD_TABLE_0_MASK 0x0000F000
1801
#define IPW_ORD_TABLE_1_MASK 0x0000F100
1802
#define IPW_ORD_TABLE_2_MASK 0x0000F200
1803
#define IPW_ORD_TABLE_3_MASK 0x0000F300
1804
#define IPW_ORD_TABLE_4_MASK 0x0000F400
1805
#define IPW_ORD_TABLE_5_MASK 0x0000F500
1806
#define IPW_ORD_TABLE_6_MASK 0x0000F600
1807
#define IPW_ORD_TABLE_7_MASK 0x0000F700
1810
* Table 0 Entries (all entries are 32 bits)
1813
IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1814
IPW_ORD_STAT_FRAG_TRESHOLD,
1815
IPW_ORD_STAT_RTS_THRESHOLD,
1816
IPW_ORD_STAT_TX_HOST_REQUESTS,
1817
IPW_ORD_STAT_TX_HOST_COMPLETE,
1818
IPW_ORD_STAT_TX_DIR_DATA,
1819
IPW_ORD_STAT_TX_DIR_DATA_B_1,
1820
IPW_ORD_STAT_TX_DIR_DATA_B_2,
1821
IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1822
IPW_ORD_STAT_TX_DIR_DATA_B_11,
1825
IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1826
IPW_ORD_STAT_TX_DIR_DATA_G_2,
1827
IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1828
IPW_ORD_STAT_TX_DIR_DATA_G_6,
1829
IPW_ORD_STAT_TX_DIR_DATA_G_9,
1830
IPW_ORD_STAT_TX_DIR_DATA_G_11,
1831
IPW_ORD_STAT_TX_DIR_DATA_G_12,
1832
IPW_ORD_STAT_TX_DIR_DATA_G_18,
1833
IPW_ORD_STAT_TX_DIR_DATA_G_24,
1834
IPW_ORD_STAT_TX_DIR_DATA_G_36,
1835
IPW_ORD_STAT_TX_DIR_DATA_G_48,
1836
IPW_ORD_STAT_TX_DIR_DATA_G_54,
1837
IPW_ORD_STAT_TX_NON_DIR_DATA,
1838
IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1839
IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1840
IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1841
IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1844
IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1845
IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1846
IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1847
IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1848
IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1849
IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1850
IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1851
IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1852
IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1853
IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1854
IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1855
IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1856
IPW_ORD_STAT_TX_RETRY,
1857
IPW_ORD_STAT_TX_FAILURE,
1858
IPW_ORD_STAT_RX_ERR_CRC,
1859
IPW_ORD_STAT_RX_ERR_ICV,
1860
IPW_ORD_STAT_RX_NO_BUFFER,
1861
IPW_ORD_STAT_FULL_SCANS,
1862
IPW_ORD_STAT_PARTIAL_SCANS,
1863
IPW_ORD_STAT_TGH_ABORTED_SCANS,
1864
IPW_ORD_STAT_TX_TOTAL_BYTES,
1865
IPW_ORD_STAT_CURR_RSSI_RAW,
1866
IPW_ORD_STAT_RX_BEACON,
1867
IPW_ORD_STAT_MISSED_BEACONS,
1868
IPW_ORD_TABLE_0_LAST
1871
#define IPW_RSSI_TO_DBM 112
1876
IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1882
* FW_VERSION: 16 byte string
1883
* FW_DATE: 16 byte string (only 14 bytes used)
1884
* UCODE_VERSION: 4 byte version code
1885
* UCODE_DATE: 5 bytes code code
1886
* ADDAPTER_MAC: 6 byte MAC address
1890
IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1891
IPW_ORD_STAT_FW_DATE,
1892
IPW_ORD_STAT_UCODE_VERSION,
1893
IPW_ORD_STAT_UCODE_DATE,
1894
IPW_ORD_STAT_ADAPTER_MAC,
1896
IPW_ORD_TABLE_2_LAST
1901
IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1902
IPW_ORD_STAT_TX_PACKET_FAILURE,
1903
IPW_ORD_STAT_TX_PACKET_SUCCESS,
1904
IPW_ORD_STAT_TX_PACKET_ABORTED,
1905
IPW_ORD_TABLE_3_LAST
1910
IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1915
IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1916
IPW_ORD_STAT_AP_ASSNS,
1918
IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1919
IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1920
IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1921
IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1922
IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1923
IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1924
IPW_ORD_STAT_LINK_UP,
1925
IPW_ORD_STAT_LINK_DOWN,
1926
IPW_ORD_ANTENNA_DIVERSITY,
1928
IPW_ORD_TABLE_5_LAST
1933
IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1936
IPW_ORD_TABLE_6_LAST
1941
IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1942
IPW_ORD_STAT_PERCENT_TX_RETRIES,
1943
IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1944
IPW_ORD_STAT_CURR_RSSI_DBM,
1945
IPW_ORD_TABLE_7_LAST
1948
#define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
1949
#define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
1950
#define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
1951
#define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
1952
#define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
1953
#define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
1954
#define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
1956
struct ipw_fixed_rate {
1961
#define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1968
} __packed; /* XXX */
1970
struct cmdlog_host_cmd {
1977
struct ipw_cmd_log {
1978
unsigned long jiffies;
1980
struct cmdlog_host_cmd cmd;
1983
/* SysConfig command parameters ... */
1984
/* bt_coexistence param */
1985
#define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
1986
#define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
1987
#define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
1988
#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
1989
#define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
1991
/* clear-to-send to self param */
1992
#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00
1993
#define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x01
1994
#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1996
/* Antenna diversity param (h/w can select best antenna, based on signal) */
1997
#define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
1998
#define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
1999
#define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
2000
#define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */
2003
* The definitions below were lifted off the ipw2100 driver, which only
2004
* supports 'b' mode, so I'm sure these are not exactly correct.
2006
* Somebody fix these!!
2008
#define REG_MIN_CHANNEL 0
2009
#define REG_MAX_CHANNEL 14
2011
#define REG_CHANNEL_MASK 0x00003FFF
2012
#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
2014
#define IPW_MAX_CONFIG_RETRIES 10
2016
#endif /* __ipw2200_h__ */