2
comedi/drivers/gsc_hpdi.c
3
This is a driver for the General Standards Corporation High
4
Speed Parallel Digital Interface rs485 boards.
6
Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7
Copyright (C) 2003 Coherent Imaging Systems
9
COMEDI - Linux Control and Measurement Device Interface
10
Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12
This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
14
the Free Software Foundation; either version 2 of the License, or
15
(at your option) any later version.
17
This program is distributed in the hope that it will be useful,
18
but WITHOUT ANY WARRANTY; without even the implied warranty of
19
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20
GNU General Public License for more details.
22
You should have received a copy of the GNU General Public License
23
along with this program; if not, write to the Free Software
24
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26
************************************************************************/
31
Description: General Standards Corporation High
32
Speed Parallel Digital Interface rs485 boards
33
Author: Frank Mori Hess <fmhess@users.sourceforge.net>
34
Status: only receive mode works, transmit not supported
36
Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
39
Configuration options:
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[0] - PCI bus of device (optional)
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[1] - PCI slot of device (optional)
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There are some additional hpdi models available from GSC for which
44
support could be added to this driver.
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#include <linux/interrupt.h>
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#include "../comedidev.h"
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#include <linux/delay.h>
52
#include "comedi_pci.h"
54
#include "comedi_fc.h"
56
static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it);
57
static int hpdi_detach(struct comedi_device *dev);
58
static void abort_dma(struct comedi_device *dev, unsigned int channel);
59
static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
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static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
61
struct comedi_cmd *cmd);
62
static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
63
static irqreturn_t handle_interrupt(int irq, void *d);
64
static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
66
#undef HPDI_DEBUG /* disable debugging messages */
67
/* #define HPDI_DEBUG enable debugging code */
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#define DEBUG_PRINT(format, args...) printk(format , ## args)
72
#define DEBUG_PRINT(format, args...)
75
#define TIMER_BASE 50 /* 20MHz master clock */
76
#define DMA_BUFFER_SIZE 0x10000
77
#define NUM_DMA_BUFFERS 4
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#define NUM_DMA_DESCRIPTORS 256
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/* indices of base address regions */
81
enum base_address_regions {
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PLX9080_BADDRINDEX = 0,
87
FIRMWARE_REV_REG = 0x0,
88
BOARD_CONTROL_REG = 0x4,
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BOARD_STATUS_REG = 0x8,
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TX_PROG_ALMOST_REG = 0xc,
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RX_PROG_ALMOST_REG = 0x10,
94
TX_STATUS_COUNT_REG = 0x1c,
95
TX_LINE_VALID_COUNT_REG = 0x20,
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TX_LINE_INVALID_COUNT_REG = 0x24,
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RX_STATUS_COUNT_REG = 0x28,
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RX_LINE_COUNT_REG = 0x2c,
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INTERRUPT_CONTROL_REG = 0x30,
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INTERRUPT_STATUS_REG = 0x34,
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TX_CLOCK_DIVIDER_REG = 0x38,
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TX_FIFO_SIZE_REG = 0x40,
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RX_FIFO_SIZE_REG = 0x44,
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TX_FIFO_WORDS_REG = 0x48,
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RX_FIFO_WORDS_REG = 0x4c,
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INTERRUPT_EDGE_LEVEL_REG = 0x50,
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INTERRUPT_POLARITY_REG = 0x54,
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int command_channel_valid(unsigned int channel)
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if (channel == 0 || channel > 6) {
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"gsc_hpdi: bug! invalid cable command channel\n");
120
/* bit definitions */
122
enum firmware_revision_bits {
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FEATURES_REG_PRESENT_BIT = 0x8000,
125
int firmware_revision(uint32_t fwr_bits)
127
return fwr_bits & 0xff;
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int pcb_revision(uint32_t fwr_bits)
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return (fwr_bits >> 8) & 0xff;
135
int hpdi_subid(uint32_t fwr_bits)
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return (fwr_bits >> 16) & 0xff;
140
enum board_control_bits {
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BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
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TX_FIFO_RESET_BIT = 0x2,
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RX_FIFO_RESET_BIT = 0x4,
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TX_ENABLE_BIT = 0x10,
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RX_ENABLE_BIT = 0x20,
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DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
147
/* for ch 0, ch 1 can only transmit (when present) */
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LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
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CABLE_THROTTLE_ENABLE_BIT = 0x20,
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TEST_MODE_ENABLE_BIT = 0x80000000,
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uint32_t command_discrete_output_bits(unsigned int channel, int output,
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if (command_channel_valid(channel) == 0)
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bits |= 0x1 << (16 + channel);
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bits |= 0x1 << (24 + channel);
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bits |= 0x1 << (24 + channel);
170
enum board_status_bits {
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COMMAND_LINE_STATUS_MASK = 0x7f,
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TX_IN_PROGRESS_BIT = 0x80,
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TX_NOT_EMPTY_BIT = 0x100,
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TX_NOT_ALMOST_EMPTY_BIT = 0x200,
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TX_NOT_ALMOST_FULL_BIT = 0x400,
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TX_NOT_FULL_BIT = 0x800,
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RX_NOT_EMPTY_BIT = 0x1000,
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RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
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RX_NOT_ALMOST_FULL_BIT = 0x4000,
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RX_NOT_FULL_BIT = 0x8000,
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BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
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BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
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TX_OVERRUN_BIT = 0x200000,
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RX_UNDERRUN_BIT = 0x400000,
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RX_OVERRUN_BIT = 0x800000,
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uint32_t almost_full_bits(unsigned int num_words)
190
/* XXX need to add or subtract one? */
191
return (num_words << 16) & 0xff0000;
194
uint32_t almost_empty_bits(unsigned int num_words)
196
return num_words & 0xffff;
199
unsigned int almost_full_num_words(uint32_t bits)
201
/* XXX need to add or subtract one? */
202
return (bits >> 16) & 0xffff;
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unsigned int almost_empty_num_words(uint32_t bits)
207
return bits & 0xffff;
211
FIFO_SIZE_PRESENT_BIT = 0x1,
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FIFO_WORDS_PRESENT_BIT = 0x2,
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LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
214
GPIO_SUPPORTED_BIT = 0x8,
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PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
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OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
219
enum interrupt_sources {
220
FRAME_VALID_START_INTR = 0,
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FRAME_VALID_END_INTR = 1,
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TX_FIFO_EMPTY_INTR = 8,
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TX_FIFO_ALMOST_EMPTY_INTR = 9,
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TX_FIFO_ALMOST_FULL_INTR = 10,
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TX_FIFO_FULL_INTR = 11,
227
RX_ALMOST_EMPTY_INTR = 13,
228
RX_ALMOST_FULL_INTR = 14,
231
int command_intr_source(unsigned int channel)
233
if (command_channel_valid(channel) == 0)
238
uint32_t intr_bit(int interrupt_source)
240
return 0x1 << interrupt_source;
243
uint32_t tx_clock_divisor_bits(unsigned int divisor)
245
return divisor & 0xff;
248
unsigned int fifo_size(uint32_t fifo_size_bits)
250
return fifo_size_bits & 0xfffff;
253
unsigned int fifo_words(uint32_t fifo_words_bits)
255
return fifo_words_bits & 0xfffff;
258
uint32_t intr_edge_bit(int interrupt_source)
260
return 0x1 << interrupt_source;
263
uint32_t intr_active_high_bit(int interrupt_source)
265
return 0x1 << interrupt_source;
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int device_id; /* pci device id */
272
int subdevice_id; /* pci subdevice id */
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static const struct hpdi_board hpdi_boards[] = {
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.name = "pci-hpdi32",
278
.device_id = PCI_DEVICE_ID_PLX_9080,
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.subdevice_id = 0x2400,
283
.name = "pxi-hpdi32",
285
.subdevice_id = 0x2705,
290
static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = {
292
PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
297
MODULE_DEVICE_TABLE(pci, hpdi_pci_table);
299
static inline struct hpdi_board *board(const struct comedi_device *dev)
301
return (struct hpdi_board *)dev->board_ptr;
304
struct hpdi_private {
306
struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
307
/* base addresses (physical) */
308
resource_size_t plx9080_phys_iobase;
309
resource_size_t hpdi_phys_iobase;
310
/* base addresses (ioremapped) */
311
void *plx9080_iobase;
313
uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
314
/* physical addresses of dma buffers */
315
dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
316
/* array of dma descriptors read by plx9080, allocated to get proper
318
struct plx_dma_desc *dma_desc;
319
/* physical address of dma descriptor array */
320
dma_addr_t dma_desc_phys_addr;
321
unsigned int num_dma_descriptors;
322
/* pointer to start of buffers indexed by descriptor */
323
uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
324
/* index of the dma descriptor that is currently being used */
325
volatile unsigned int dma_desc_index;
326
unsigned int tx_fifo_size;
327
unsigned int rx_fifo_size;
328
volatile unsigned long dio_count;
329
/* software copies of values written to hpdi registers */
330
volatile uint32_t bits[24];
331
/* number of bytes at which to generate COMEDI_CB_BLOCK events */
332
volatile unsigned int block_size;
333
unsigned dio_config_output:1;
336
static inline struct hpdi_private *priv(struct comedi_device *dev)
341
static struct comedi_driver driver_hpdi = {
342
.driver_name = "gsc_hpdi",
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.module = THIS_MODULE,
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.attach = hpdi_attach,
345
.detach = hpdi_detach,
348
static int __devinit driver_hpdi_pci_probe(struct pci_dev *dev,
349
const struct pci_device_id *ent)
351
return comedi_pci_auto_config(dev, driver_hpdi.driver_name);
354
static void __devexit driver_hpdi_pci_remove(struct pci_dev *dev)
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comedi_pci_auto_unconfig(dev);
359
static struct pci_driver driver_hpdi_pci_driver = {
360
.id_table = hpdi_pci_table,
361
.probe = &driver_hpdi_pci_probe,
362
.remove = __devexit_p(&driver_hpdi_pci_remove)
365
static int __init driver_hpdi_init_module(void)
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retval = comedi_driver_register(&driver_hpdi);
373
driver_hpdi_pci_driver.name = (char *)driver_hpdi.driver_name;
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return pci_register_driver(&driver_hpdi_pci_driver);
377
static void __exit driver_hpdi_cleanup_module(void)
379
pci_unregister_driver(&driver_hpdi_pci_driver);
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comedi_driver_unregister(&driver_hpdi);
383
module_init(driver_hpdi_init_module);
384
module_exit(driver_hpdi_cleanup_module);
386
static int dio_config_insn(struct comedi_device *dev,
387
struct comedi_subdevice *s, struct comedi_insn *insn,
391
case INSN_CONFIG_DIO_OUTPUT:
392
priv(dev)->dio_config_output = 1;
395
case INSN_CONFIG_DIO_INPUT:
396
priv(dev)->dio_config_output = 0;
399
case INSN_CONFIG_DIO_QUERY:
401
priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
404
case INSN_CONFIG_BLOCK_SIZE:
405
return dio_config_block_size(dev, data);
414
static void disable_plx_interrupts(struct comedi_device *dev)
416
writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
419
/* initialize plx9080 chip */
420
static void init_plx9080(struct comedi_device *dev)
423
void *plx_iobase = priv(dev)->plx9080_iobase;
426
DEBUG_PRINT(" plx interrupt status 0x%x\n",
427
readl(plx_iobase + PLX_INTRCS_REG));
428
DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
429
DEBUG_PRINT(" plx control reg 0x%x\n",
430
readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
432
DEBUG_PRINT(" plx revision 0x%x\n",
433
readl(plx_iobase + PLX_REVISION_REG));
434
DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
435
readl(plx_iobase + PLX_DMA0_MODE_REG));
436
DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
437
readl(plx_iobase + PLX_DMA1_MODE_REG));
438
DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
439
readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
440
DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
441
readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
442
DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
443
readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
444
DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
445
readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
446
DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
447
readb(plx_iobase + PLX_DMA0_CS_REG));
448
DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
449
readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
450
DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
452
bits = BIGEND_DMA0 | BIGEND_DMA1;
456
writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
458
disable_plx_interrupts(dev);
463
/* configure dma0 mode */
465
/* enable ready input */
466
bits |= PLX_DMA_EN_READYIN_BIT;
467
/* enable dma chaining */
468
bits |= PLX_EN_CHAIN_BIT;
469
/* enable interrupt on dma done
470
* (probably don't need this, since chain never finishes) */
471
bits |= PLX_EN_DMA_DONE_INTR_BIT;
472
/* don't increment local address during transfers
473
* (we are transferring from a fixed fifo register) */
474
bits |= PLX_LOCAL_ADDR_CONST_BIT;
475
/* route dma interrupt to pci bus */
476
bits |= PLX_DMA_INTR_PCI_BIT;
477
/* enable demand mode */
478
bits |= PLX_DEMAND_MODE_BIT;
479
/* enable local burst mode */
480
bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
481
bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
482
writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
485
/* Allocate and initialize the subdevice structures.
487
static int setup_subdevices(struct comedi_device *dev)
489
struct comedi_subdevice *s;
491
if (alloc_subdevices(dev, 1) < 0)
494
s = dev->subdevices + 0;
495
/* analog input subdevice */
496
dev->read_subdev = s;
497
/* dev->write_subdev = s; */
498
s->type = COMEDI_SUBD_DIO;
500
SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
502
s->len_chanlist = 32;
504
s->range_table = &range_digital;
505
s->insn_config = dio_config_insn;
506
s->do_cmd = hpdi_cmd;
507
s->do_cmdtest = hpdi_cmd_test;
508
s->cancel = hpdi_cancel;
513
static int init_hpdi(struct comedi_device *dev)
515
uint32_t plx_intcsr_bits;
517
writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
520
writel(almost_empty_bits(32) | almost_full_bits(32),
521
priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
522
writel(almost_empty_bits(32) | almost_full_bits(32),
523
priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
525
priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
527
priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
530
writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
532
/* enable interrupts */
534
ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
536
writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
541
/* setup dma descriptors so a link completes every 'transfer_size' bytes */
542
static int setup_dma_descriptors(struct comedi_device *dev,
543
unsigned int transfer_size)
545
unsigned int buffer_index, buffer_offset;
546
uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
547
PLX_XFER_LOCAL_TO_PCI;
550
if (transfer_size > DMA_BUFFER_SIZE)
551
transfer_size = DMA_BUFFER_SIZE;
552
transfer_size -= transfer_size % sizeof(uint32_t);
553
if (transfer_size == 0)
556
DEBUG_PRINT(" transfer_size %i\n", transfer_size);
557
DEBUG_PRINT(" descriptors at 0x%lx\n",
558
(unsigned long)priv(dev)->dma_desc_phys_addr);
562
for (i = 0; i < NUM_DMA_DESCRIPTORS &&
563
buffer_index < NUM_DMA_BUFFERS; i++) {
564
priv(dev)->dma_desc[i].pci_start_addr =
565
cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] +
567
priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
568
priv(dev)->dma_desc[i].transfer_size =
569
cpu_to_le32(transfer_size);
570
priv(dev)->dma_desc[i].next =
571
cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
573
sizeof(priv(dev)->dma_desc[0])) | next_bits);
575
priv(dev)->desc_dio_buffer[i] =
576
priv(dev)->dio_buffer[buffer_index] +
577
(buffer_offset / sizeof(uint32_t));
579
buffer_offset += transfer_size;
580
if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
585
DEBUG_PRINT(" desc %i\n", i);
586
DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
587
priv(dev)->desc_dio_buffer[i],
588
(unsigned long)priv(dev)->dma_desc[i].
590
DEBUG_PRINT(" next 0x%lx\n",
591
(unsigned long)priv(dev)->dma_desc[i].next);
593
priv(dev)->num_dma_descriptors = i;
594
/* fix last descriptor to point back to first */
595
priv(dev)->dma_desc[i - 1].next =
596
cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
597
DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
598
(unsigned long)priv(dev)->dma_desc[i - 1].next);
600
priv(dev)->block_size = transfer_size;
602
return transfer_size;
605
static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it)
607
struct pci_dev *pcidev;
611
printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor);
613
if (alloc_private(dev, sizeof(struct hpdi_private)) < 0)
617
for (i = 0; i < ARRAY_SIZE(hpdi_boards) &&
618
dev->board_ptr == NULL; i++) {
620
pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
621
hpdi_boards[i].device_id,
623
hpdi_boards[i].subdevice_id,
625
/* was a particular bus/slot requested? */
626
if (it->options[0] || it->options[1]) {
627
/* are we on the wrong bus/slot? */
628
if (pcidev->bus->number != it->options[0] ||
629
PCI_SLOT(pcidev->devfn) != it->options[1])
633
priv(dev)->hw_dev = pcidev;
634
dev->board_ptr = hpdi_boards + i;
637
} while (pcidev != NULL);
639
if (dev->board_ptr == NULL) {
640
printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n");
645
"gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
646
pcidev->bus->number, PCI_SLOT(pcidev->devfn));
648
if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) {
650
" failed enable PCI device and request regions\n");
653
pci_set_master(pcidev);
655
/* Initialize dev->board_name */
656
dev->board_name = board(dev)->name;
658
priv(dev)->plx9080_phys_iobase =
659
pci_resource_start(pcidev, PLX9080_BADDRINDEX);
660
priv(dev)->hpdi_phys_iobase =
661
pci_resource_start(pcidev, HPDI_BADDRINDEX);
663
/* remap, won't work with 2.0 kernels but who cares */
664
priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
665
pci_resource_len(pcidev,
666
PLX9080_BADDRINDEX));
667
priv(dev)->hpdi_iobase =
668
ioremap(priv(dev)->hpdi_phys_iobase,
669
pci_resource_len(pcidev, HPDI_BADDRINDEX));
670
if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
671
printk(KERN_WARNING " failed to remap io memory\n");
675
DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
676
DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
681
if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
682
driver_hpdi.driver_name, dev)) {
684
" unable to allocate irq %u\n", pcidev->irq);
687
dev->irq = pcidev->irq;
689
printk(KERN_WARNING " irq %u\n", dev->irq);
691
/* alocate pci dma buffers */
692
for (i = 0; i < NUM_DMA_BUFFERS; i++) {
693
priv(dev)->dio_buffer[i] =
694
pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
695
&priv(dev)->dio_buffer_phys_addr[i]);
696
DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
697
priv(dev)->dio_buffer[i],
698
(unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
700
/* allocate dma descriptors */
701
priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
702
sizeof(struct plx_dma_desc) *
706
if (priv(dev)->dma_desc_phys_addr & 0xf) {
708
" dma descriptors not quad-word aligned (bug)\n");
712
retval = setup_dma_descriptors(dev, 0x1000);
716
retval = setup_subdevices(dev);
720
return init_hpdi(dev);
723
static int hpdi_detach(struct comedi_device *dev)
727
printk(KERN_WARNING "comedi%d: gsc_hpdi: remove\n", dev->minor);
730
free_irq(dev->irq, dev);
731
if ((priv(dev)) && (priv(dev)->hw_dev)) {
732
if (priv(dev)->plx9080_iobase) {
733
disable_plx_interrupts(dev);
734
iounmap((void *)priv(dev)->plx9080_iobase);
736
if (priv(dev)->hpdi_iobase)
737
iounmap((void *)priv(dev)->hpdi_iobase);
738
/* free pci dma buffers */
739
for (i = 0; i < NUM_DMA_BUFFERS; i++) {
740
if (priv(dev)->dio_buffer[i])
741
pci_free_consistent(priv(dev)->hw_dev,
746
(dev)->dio_buffer_phys_addr
749
/* free dma descriptors */
750
if (priv(dev)->dma_desc)
751
pci_free_consistent(priv(dev)->hw_dev,
752
sizeof(struct plx_dma_desc)
753
* NUM_DMA_DESCRIPTORS,
757
if (priv(dev)->hpdi_phys_iobase)
758
comedi_pci_disable(priv(dev)->hw_dev);
759
pci_dev_put(priv(dev)->hw_dev);
764
static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
766
unsigned int requested_block_size;
769
requested_block_size = data[1];
771
retval = setup_dma_descriptors(dev, requested_block_size);
780
static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
781
struct comedi_cmd *cmd)
787
/* step 1: make sure trigger sources are trivially valid */
789
tmp = cmd->start_src;
790
cmd->start_src &= TRIG_NOW;
791
if (!cmd->start_src || tmp != cmd->start_src)
794
tmp = cmd->scan_begin_src;
795
cmd->scan_begin_src &= TRIG_EXT;
796
if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
799
tmp = cmd->convert_src;
800
cmd->convert_src &= TRIG_NOW;
801
if (!cmd->convert_src || tmp != cmd->convert_src)
804
tmp = cmd->scan_end_src;
805
cmd->scan_end_src &= TRIG_COUNT;
806
if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
810
cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
811
if (!cmd->stop_src || tmp != cmd->stop_src)
817
/* step 2: make sure trigger sources are unique and mutually
820
/* uniqueness check */
821
if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
827
/* step 3: make sure arguments are trivially compatible */
829
if (!cmd->chanlist_len) {
830
cmd->chanlist_len = 32;
833
if (cmd->scan_end_arg != cmd->chanlist_len) {
834
cmd->scan_end_arg = cmd->chanlist_len;
838
switch (cmd->stop_src) {
840
if (!cmd->stop_arg) {
846
if (cmd->stop_arg != 0) {
858
/* step 4: fix up any arguments */
866
for (i = 1; i < cmd->chanlist_len; i++) {
867
if (CR_CHAN(cmd->chanlist[i]) != i) {
868
/* XXX could support 8 or 16 channels */
870
"chanlist must be ch 0 to 31 in order");
882
static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
883
struct comedi_cmd *cmd)
885
if (priv(dev)->dio_config_output)
888
return di_cmd_test(dev, s, cmd);
891
static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
894
writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
895
priv(dev)->hpdi_iobase + offset);
898
static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
902
struct comedi_async *async = s->async;
903
struct comedi_cmd *cmd = &async->cmd;
905
hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
907
DEBUG_PRINT("hpdi: in di_cmd\n");
911
priv(dev)->dma_desc_index = 0;
913
/* These register are supposedly unused during chained dma,
914
* but I have found that left over values from last operation
915
* occasionally cause problems with transfer of first dma
916
* block. Initializing them to zero seems to fix the problem. */
917
writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
918
writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
919
writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
920
/* give location of first dma descriptor */
922
priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
923
PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
924
writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
926
/* spinlock for plx dma control/status reg */
927
spin_lock_irqsave(&dev->spinlock, flags);
928
/* enable dma transfer */
929
writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
930
priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
931
spin_unlock_irqrestore(&dev->spinlock, flags);
933
if (cmd->stop_src == TRIG_COUNT)
934
priv(dev)->dio_count = cmd->stop_arg;
936
priv(dev)->dio_count = 1;
938
/* clear over/under run status flags */
939
writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
940
priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
941
/* enable interrupts */
942
writel(intr_bit(RX_FULL_INTR),
943
priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
945
DEBUG_PRINT("hpdi: starting rx\n");
946
hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
951
static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
953
if (priv(dev)->dio_config_output)
956
return di_cmd(dev, s);
959
static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
961
struct comedi_async *async = dev->read_subdev->async;
962
uint32_t next_transfer_addr;
969
priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
972
priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
974
/* loop until we have read all the full buffers */
976
for (next_transfer_addr = readl(pci_addr_reg);
977
(next_transfer_addr <
978
le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
980
|| next_transfer_addr >=
981
le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
982
pci_start_addr) + priv(dev)->block_size)
983
&& j < priv(dev)->num_dma_descriptors; j++) {
984
/* transfer data from dma buffer to comedi buffer */
985
num_samples = priv(dev)->block_size / sizeof(uint32_t);
986
if (async->cmd.stop_src == TRIG_COUNT) {
987
if (num_samples > priv(dev)->dio_count)
988
num_samples = priv(dev)->dio_count;
989
priv(dev)->dio_count -= num_samples;
991
cfc_write_array_to_buffer(dev->read_subdev,
992
priv(dev)->desc_dio_buffer[priv(dev)->
994
num_samples * sizeof(uint32_t));
995
priv(dev)->dma_desc_index++;
996
priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
998
DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
999
priv(dev)->dma_desc[priv(dev)->dma_desc_index].
1001
DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
1003
/* XXX check for buffer overrun somehow */
1006
static irqreturn_t handle_interrupt(int irq, void *d)
1008
struct comedi_device *dev = d;
1009
struct comedi_subdevice *s = dev->read_subdev;
1010
struct comedi_async *async = s->async;
1011
uint32_t hpdi_intr_status, hpdi_board_status;
1012
uint32_t plx_status;
1014
uint8_t dma0_status, dma1_status;
1015
unsigned long flags;
1020
plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1021
if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
1024
hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
1025
hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
1029
if (hpdi_intr_status) {
1030
DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
1031
writel(hpdi_intr_status,
1032
priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
1034
/* spin lock makes sure no one else changes plx dma control reg */
1035
spin_lock_irqsave(&dev->spinlock, flags);
1036
dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
1037
if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
1038
writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
1039
priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
1041
DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
1042
if (dma0_status & PLX_DMA_EN_BIT)
1043
drain_dma_buffers(dev, 0);
1044
DEBUG_PRINT(" cleared dma ch0 interrupt\n");
1046
spin_unlock_irqrestore(&dev->spinlock, flags);
1048
/* spin lock makes sure no one else changes plx dma control reg */
1049
spin_lock_irqsave(&dev->spinlock, flags);
1050
dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
1051
if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
1052
writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
1053
priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
1054
DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
1056
DEBUG_PRINT(" cleared dma ch1 interrupt\n");
1058
spin_unlock_irqrestore(&dev->spinlock, flags);
1060
/* clear possible plx9080 interrupt sources */
1061
if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
1062
plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1063
writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1064
DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
1067
if (hpdi_board_status & RX_OVERRUN_BIT) {
1068
comedi_error(dev, "rx fifo overrun");
1069
async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1070
DEBUG_PRINT("dma0_status 0x%x\n",
1071
(int)readb(priv(dev)->plx9080_iobase +
1075
if (hpdi_board_status & RX_UNDERRUN_BIT) {
1076
comedi_error(dev, "rx fifo underrun");
1077
async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1080
if (priv(dev)->dio_count == 0)
1081
async->events |= COMEDI_CB_EOA;
1083
DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
1084
DEBUG_PRINT("plx status 0x%x\n", plx_status);
1086
DEBUG_PRINT(" events 0x%x\n", async->events);
1088
cfc_handle_events(dev, s);
1093
static void abort_dma(struct comedi_device *dev, unsigned int channel)
1095
unsigned long flags;
1097
/* spinlock for plx dma control/status reg */
1098
spin_lock_irqsave(&dev->spinlock, flags);
1100
plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
1102
spin_unlock_irqrestore(&dev->spinlock, flags);
1105
static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1107
hpdi_writel(dev, 0, BOARD_CONTROL_REG);
1109
writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
1116
MODULE_AUTHOR("Comedi http://www.comedi.org");
1117
MODULE_DESCRIPTION("Comedi low-level driver");
1118
MODULE_LICENSE("GPL");