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Viewing changes to drivers/net/wireless/rtlwifi/rtl8192ce/def.h

  • Committer: Package Import Robot
  • Author(s): Alessio Igor Bogani
  • Date: 2011-10-26 11:13:05 UTC
  • Revision ID: package-import@ubuntu.com-20111026111305-tz023xykf0i6eosh
Tags: upstream-3.2.0
Import upstream version 3.2.0

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drivers/net/wireless/rtlwifi/rtl8192ce/def.h
 
1
/******************************************************************************
 
2
 *
 
3
 * Copyright(c) 2009-2010  Realtek Corporation.
 
4
 *
 
5
 * This program is free software; you can redistribute it and/or modify it
 
6
 * under the terms of version 2 of the GNU General Public License as
 
7
 * published by the Free Software Foundation.
 
8
 *
 
9
 * This program is distributed in the hope that it will be useful, but WITHOUT
 
10
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
11
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 
12
 * more details.
 
13
 *
 
14
 * You should have received a copy of the GNU General Public License along with
 
15
 * this program; if not, write to the Free Software Foundation, Inc.,
 
16
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 
17
 *
 
18
 * The full GNU General Public License is included in this distribution in the
 
19
 * file called LICENSE.
 
20
 *
 
21
 * Contact Information:
 
22
 * wlanfae <wlanfae@realtek.com>
 
23
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 
24
 * Hsinchu 300, Taiwan.
 
25
 *
 
26
 * Larry Finger <Larry.Finger@lwfinger.net>
 
27
 *
 
28
 *****************************************************************************/
 
29
 
 
30
#ifndef __RTL92C_DEF_H__
 
31
#define __RTL92C_DEF_H__
 
32
 
 
33
#define HAL_RETRY_LIMIT_INFRA                           48
 
34
#define HAL_RETRY_LIMIT_AP_ADHOC                        7
 
35
 
 
36
#define PHY_RSSI_SLID_WIN_MAX                           100
 
37
#define PHY_LINKQUALITY_SLID_WIN_MAX                    20
 
38
#define PHY_BEACON_RSSI_SLID_WIN_MAX                    10
 
39
 
 
40
#define RESET_DELAY_8185                                20
 
41
 
 
42
#define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
 
43
#define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
 
44
 
 
45
#define NUM_OF_FIRMWARE_QUEUE                           10
 
46
#define NUM_OF_PAGES_IN_FW                              0x100
 
47
#define NUM_OF_PAGE_IN_FW_QUEUE_BK                      0x07
 
48
#define NUM_OF_PAGE_IN_FW_QUEUE_BE                      0x07
 
49
#define NUM_OF_PAGE_IN_FW_QUEUE_VI                      0x07
 
50
#define NUM_OF_PAGE_IN_FW_QUEUE_VO                      0x07
 
51
#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                    0x0
 
52
#define NUM_OF_PAGE_IN_FW_QUEUE_CMD                     0x0
 
53
#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                    0x02
 
54
#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                    0x02
 
55
#define NUM_OF_PAGE_IN_FW_QUEUE_BCN                     0x2
 
56
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB                     0xA1
 
57
 
 
58
#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                  0x026
 
59
#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                  0x048
 
60
#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                  0x048
 
61
#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                  0x026
 
62
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                 0x00
 
63
 
 
64
#define MAX_LINES_HWCONFIG_TXT                          1000
 
65
#define MAX_BYTES_LINE_HWCONFIG_TXT                     256
 
66
 
 
67
#define SW_THREE_WIRE                                   0
 
68
#define HW_THREE_WIRE                                   2
 
69
 
 
70
#define BT_DEMO_BOARD                                   0
 
71
#define BT_QA_BOARD                                     1
 
72
#define BT_FPGA                                         2
 
73
 
 
74
#define RX_SMOOTH_FACTOR                                20
 
75
 
 
76
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE                 0
 
77
#define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 
78
#define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 
79
 
 
80
#define MAX_H2C_QUEUE_NUM                               10
 
81
 
 
82
#define RX_MPDU_QUEUE                                   0
 
83
#define RX_CMD_QUEUE                                    1
 
84
#define RX_MAX_QUEUE                                    2
 
85
#define AC2QUEUEID(_AC)                                 (_AC)
 
86
 
 
87
#define C2H_RX_CMD_HDR_LEN                              8
 
88
#define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
 
89
        LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
 
90
#define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
 
91
        LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
 
92
#define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
 
93
        LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
 
94
#define GET_C2H_CMD_CONTINUE(__prxhdr)          \
 
95
        LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
 
96
#define GET_C2H_CMD_CONTENT(__prxhdr)           \
 
97
        ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
 
98
 
 
99
#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
 
100
        LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
 
101
#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)       \
 
102
        LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
 
103
#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
 
104
        LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
 
105
#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
 
106
        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
 
107
#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)     \
 
108
        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
 
109
#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 
110
        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 
111
#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)       \
 
112
        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 
113
#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)      \
 
114
        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 
115
#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)       \
 
116
        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 
117
 
 
118
#define CHIP_VER_B                      BIT(4)
 
119
#define CHIP_92C_BITMASK                BIT(0)
 
120
#define CHIP_92C_1T2R                   0x03
 
121
#define CHIP_92C                        0x01
 
122
#define CHIP_88C                        0x00
 
123
 
 
124
enum version_8192c {
 
125
        VERSION_A_CHIP_92C = 0x01,
 
126
        VERSION_A_CHIP_88C = 0x00,
 
127
        VERSION_B_CHIP_92C = 0x11,
 
128
        VERSION_B_CHIP_88C = 0x10,
 
129
        VERSION_TEST_CHIP_88C = 0x00,
 
130
        VERSION_TEST_CHIP_92C = 0x01,
 
131
        VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
 
132
        VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
 
133
        VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
 
134
        VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
 
135
        VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
 
136
        VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
 
137
        VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
 
138
        VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
 
139
        VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
 
140
        VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
 
141
        VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
 
142
        VERSION_UNKNOWN = 0x88,
 
143
};
 
144
 
 
145
#define CUT_VERSION_MASK                (BIT(6)|BIT(7))
 
146
#define CHIP_VENDOR_UMC                 BIT(5)
 
147
#define CHIP_VENDOR_UMC_B_CUT           BIT(6) /* Chip version for ECO */
 
148
#define IS_VENDOR_UMC_A_CUT(version)    ((IS_CHIP_VENDOR_UMC(version)) ? \
 
149
        ((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
 
150
#define IS_CHIP_VER_B(version)  ((version & CHIP_VER_B) ? true : false)
 
151
#define IS_VENDOR_UMC_A_CUT(version)    ((IS_CHIP_VENDOR_UMC(version)) ? \
 
152
        ((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
 
153
#define IS_92C_SERIAL(version)  ((version & CHIP_92C_BITMASK) ? true : false)
 
154
#define IS_CHIP_VENDOR_UMC(version)             \
 
155
        ((version & CHIP_VENDOR_UMC) ? true : false)
 
156
#define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
 
157
#define IS_81xxC_VENDOR_UMC_B_CUT(version)              \
 
158
        ((IS_CHIP_VENDOR_UMC(version)) ? \
 
159
        ((GET_CVID_CUT_VERSION(version) == CHIP_VENDOR_UMC_B_CUT) ?     \
 
160
        true : false) : false)
 
161
 
 
162
enum rtl819x_loopback_e {
 
163
        RTL819X_NO_LOOPBACK = 0,
 
164
        RTL819X_MAC_LOOPBACK = 1,
 
165
        RTL819X_DMA_LOOPBACK = 2,
 
166
        RTL819X_CCK_LOOPBACK = 3,
 
167
};
 
168
 
 
169
enum rf_optype {
 
170
        RF_OP_BY_SW_3WIRE = 0,
 
171
        RF_OP_BY_FW,
 
172
        RF_OP_MAX
 
173
};
 
174
 
 
175
enum rf_power_state {
 
176
        RF_ON,
 
177
        RF_OFF,
 
178
        RF_SLEEP,
 
179
        RF_SHUT_DOWN,
 
180
};
 
181
 
 
182
enum power_save_mode {
 
183
        POWER_SAVE_MODE_ACTIVE,
 
184
        POWER_SAVE_MODE_SAVE,
 
185
};
 
186
 
 
187
enum power_polocy_config {
 
188
        POWERCFG_MAX_POWER_SAVINGS,
 
189
        POWERCFG_GLOBAL_POWER_SAVINGS,
 
190
        POWERCFG_LOCAL_POWER_SAVINGS,
 
191
        POWERCFG_LENOVO,
 
192
};
 
193
 
 
194
enum interface_select_pci {
 
195
        INTF_SEL1_MINICARD = 0,
 
196
        INTF_SEL0_PCIE = 1,
 
197
        INTF_SEL2_RSV = 2,
 
198
        INTF_SEL3_RSV = 3,
 
199
};
 
200
 
 
201
enum hal_fw_c2h_cmd_id {
 
202
        HAL_FW_C2H_CMD_Read_MACREG = 0,
 
203
        HAL_FW_C2H_CMD_Read_BBREG = 1,
 
204
        HAL_FW_C2H_CMD_Read_RFREG = 2,
 
205
        HAL_FW_C2H_CMD_Read_EEPROM = 3,
 
206
        HAL_FW_C2H_CMD_Read_EFUSE = 4,
 
207
        HAL_FW_C2H_CMD_Read_CAM = 5,
 
208
        HAL_FW_C2H_CMD_Get_BasicRate = 6,
 
209
        HAL_FW_C2H_CMD_Get_DataRate = 7,
 
210
        HAL_FW_C2H_CMD_Survey = 8,
 
211
        HAL_FW_C2H_CMD_SurveyDone = 9,
 
212
        HAL_FW_C2H_CMD_JoinBss = 10,
 
213
        HAL_FW_C2H_CMD_AddSTA = 11,
 
214
        HAL_FW_C2H_CMD_DelSTA = 12,
 
215
        HAL_FW_C2H_CMD_AtimDone = 13,
 
216
        HAL_FW_C2H_CMD_TX_Report = 14,
 
217
        HAL_FW_C2H_CMD_CCX_Report = 15,
 
218
        HAL_FW_C2H_CMD_DTM_Report = 16,
 
219
        HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
 
220
        HAL_FW_C2H_CMD_C2HLBK = 18,
 
221
        HAL_FW_C2H_CMD_C2HDBG = 19,
 
222
        HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
 
223
        HAL_FW_C2H_CMD_MAX
 
224
};
 
225
 
 
226
enum rtl_desc_qsel {
 
227
        QSLT_BK = 0x2,
 
228
        QSLT_BE = 0x0,
 
229
        QSLT_VI = 0x5,
 
230
        QSLT_VO = 0x7,
 
231
        QSLT_BEACON = 0x10,
 
232
        QSLT_HIGH = 0x11,
 
233
        QSLT_MGNT = 0x12,
 
234
        QSLT_CMD = 0x13,
 
235
};
 
236
 
 
237
struct phy_sts_cck_8192s_t {
 
238
        u8 adc_pwdb_X[4];
 
239
        u8 sq_rpt;
 
240
        u8 cck_agc_rpt;
 
241
};
 
242
 
 
243
struct h2c_cmd_8192c {
 
244
        u8 element_id;
 
245
        u32 cmd_len;
 
246
        u8 *p_cmdbuffer;
 
247
};
 
248
 
 
249
#endif