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  • Committer: Package Import Robot
  • Author(s): Alessio Igor Bogani
  • Date: 2011-10-26 11:13:05 UTC
  • Revision ID: package-import@ubuntu.com-20111026111305-tz023xykf0i6eosh
Tags: upstream-3.2.0
Import upstream version 3.2.0

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arch/arm/mach-s5p64x0/clock-s5p6450.c
 
1
/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
 
2
 *
 
3
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 
4
 *              http://www.samsung.com
 
5
 *
 
6
 * S5P6450 - Clock support
 
7
 *
 
8
 * This program is free software; you can redistribute it and/or modify
 
9
 * it under the terms of the GNU General Public License version 2 as
 
10
 * published by the Free Software Foundation.
 
11
*/
 
12
 
 
13
#include <linux/init.h>
 
14
#include <linux/module.h>
 
15
#include <linux/kernel.h>
 
16
#include <linux/list.h>
 
17
#include <linux/errno.h>
 
18
#include <linux/err.h>
 
19
#include <linux/clk.h>
 
20
#include <linux/sysdev.h>
 
21
#include <linux/io.h>
 
22
 
 
23
#include <mach/hardware.h>
 
24
#include <mach/map.h>
 
25
#include <mach/regs-clock.h>
 
26
#include <mach/s5p64x0-clock.h>
 
27
 
 
28
#include <plat/cpu-freq.h>
 
29
#include <plat/clock.h>
 
30
#include <plat/cpu.h>
 
31
#include <plat/pll.h>
 
32
#include <plat/s5p-clock.h>
 
33
#include <plat/clock-clksrc.h>
 
34
#include <plat/s5p6450.h>
 
35
 
 
36
static struct clksrc_clk clk_mout_dpll = {
 
37
        .clk    = {
 
38
                .name           = "mout_dpll",
 
39
        },
 
40
        .sources        = &clk_src_dpll,
 
41
        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
 
42
};
 
43
 
 
44
static u32 epll_div[][5] = {
 
45
        { 133000000,    27307,  55, 2, 2 },
 
46
        { 100000000,    43691,  41, 2, 2 },
 
47
        { 480000000,    0,      80, 2, 0 },
 
48
};
 
49
 
 
50
static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
 
51
{
 
52
        unsigned int epll_con, epll_con_k;
 
53
        unsigned int i;
 
54
 
 
55
        if (clk->rate == rate)  /* Return if nothing changed */
 
56
                return 0;
 
57
 
 
58
        epll_con = __raw_readl(S5P64X0_EPLL_CON);
 
59
        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
 
60
 
 
61
        epll_con_k &= ~(PLL90XX_KDIV_MASK);
 
62
        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
 
63
 
 
64
        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
 
65
                 if (epll_div[i][0] == rate) {
 
66
                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
 
67
                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
 
68
                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
 
69
                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
 
70
                        break;
 
71
                }
 
72
        }
 
73
 
 
74
        if (i == ARRAY_SIZE(epll_div)) {
 
75
                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
 
76
                return -EINVAL;
 
77
        }
 
78
 
 
79
        __raw_writel(epll_con, S5P64X0_EPLL_CON);
 
80
        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
 
81
 
 
82
        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
 
83
                        clk->rate, rate);
 
84
 
 
85
        clk->rate = rate;
 
86
 
 
87
        return 0;
 
88
}
 
89
 
 
90
static struct clk_ops s5p6450_epll_ops = {
 
91
        .get_rate = s5p_epll_get_rate,
 
92
        .set_rate = s5p6450_epll_set_rate,
 
93
};
 
94
 
 
95
static struct clksrc_clk clk_dout_epll = {
 
96
        .clk    = {
 
97
                .name           = "dout_epll",
 
98
                .parent         = &clk_mout_epll.clk,
 
99
        },
 
100
        .reg_div        = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
 
101
};
 
102
 
 
103
static struct clksrc_clk clk_mout_hclk_sel = {
 
104
        .clk    = {
 
105
                .name           = "mout_hclk_sel",
 
106
        },
 
107
        .sources        = &clkset_hclk_low,
 
108
        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
 
109
};
 
110
 
 
111
static struct clk *clkset_hclk_list[] = {
 
112
        &clk_mout_hclk_sel.clk,
 
113
        &clk_armclk.clk,
 
114
};
 
115
 
 
116
static struct clksrc_sources clkset_hclk = {
 
117
        .sources        = clkset_hclk_list,
 
118
        .nr_sources     = ARRAY_SIZE(clkset_hclk_list),
 
119
};
 
120
 
 
121
static struct clksrc_clk clk_hclk = {
 
122
        .clk    = {
 
123
                .name           = "clk_hclk",
 
124
        },
 
125
        .sources        = &clkset_hclk,
 
126
        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
 
127
        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
 
128
};
 
129
 
 
130
static struct clksrc_clk clk_pclk = {
 
131
        .clk    = {
 
132
                .name           = "clk_pclk",
 
133
                .parent         = &clk_hclk.clk,
 
134
        },
 
135
        .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
 
136
};
 
137
static struct clksrc_clk clk_dout_pwm_ratio0 = {
 
138
        .clk    = {
 
139
                .name           = "clk_dout_pwm_ratio0",
 
140
                .parent         = &clk_mout_hclk_sel.clk,
 
141
        },
 
142
        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
 
143
};
 
144
 
 
145
static struct clksrc_clk clk_pclk_to_wdt_pwm = {
 
146
        .clk    = {
 
147
                .name           = "clk_pclk_to_wdt_pwm",
 
148
                .parent         = &clk_dout_pwm_ratio0.clk,
 
149
        },
 
150
        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
 
151
};
 
152
 
 
153
static struct clksrc_clk clk_hclk_low = {
 
154
        .clk    = {
 
155
                .name           = "clk_hclk_low",
 
156
        },
 
157
        .sources        = &clkset_hclk_low,
 
158
        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
 
159
        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
 
160
};
 
161
 
 
162
static struct clksrc_clk clk_pclk_low = {
 
163
        .clk    = {
 
164
                .name           = "clk_pclk_low",
 
165
                .parent         = &clk_hclk_low.clk,
 
166
        },
 
167
        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
 
168
};
 
169
 
 
170
/*
 
171
 * The following clocks will be disabled during clock initialization. It is
 
172
 * recommended to keep the following clocks disabled until the driver requests
 
173
 * for enabling the clock.
 
174
 */
 
175
static struct clk init_clocks_off[] = {
 
176
        {
 
177
                .name           = "usbhost",
 
178
                .parent         = &clk_hclk_low.clk,
 
179
                .enable         = s5p64x0_hclk0_ctrl,
 
180
                .ctrlbit        = (1 << 3),
 
181
        }, {
 
182
                .name           = "dma",
 
183
                .devname        = "dma-pl330",
 
184
                .parent         = &clk_hclk_low.clk,
 
185
                .enable         = s5p64x0_hclk0_ctrl,
 
186
                .ctrlbit        = (1 << 12),
 
187
        }, {
 
188
                .name           = "hsmmc",
 
189
                .devname        = "s3c-sdhci.0",
 
190
                .parent         = &clk_hclk_low.clk,
 
191
                .enable         = s5p64x0_hclk0_ctrl,
 
192
                .ctrlbit        = (1 << 17),
 
193
        }, {
 
194
                .name           = "hsmmc",
 
195
                .devname        = "s3c-sdhci.1",
 
196
                .parent         = &clk_hclk_low.clk,
 
197
                .enable         = s5p64x0_hclk0_ctrl,
 
198
                .ctrlbit        = (1 << 18),
 
199
        }, {
 
200
                .name           = "hsmmc",
 
201
                .devname        = "s3c-sdhci.2",
 
202
                .parent         = &clk_hclk_low.clk,
 
203
                .enable         = s5p64x0_hclk0_ctrl,
 
204
                .ctrlbit        = (1 << 19),
 
205
        }, {
 
206
                .name           = "usbotg",
 
207
                .parent         = &clk_hclk_low.clk,
 
208
                .enable         = s5p64x0_hclk0_ctrl,
 
209
                .ctrlbit        = (1 << 20),
 
210
        }, {
 
211
                .name           = "lcd",
 
212
                .parent         = &clk_h,
 
213
                .enable         = s5p64x0_hclk1_ctrl,
 
214
                .ctrlbit        = (1 << 1),
 
215
        }, {
 
216
                .name           = "watchdog",
 
217
                .parent         = &clk_pclk_low.clk,
 
218
                .enable         = s5p64x0_pclk_ctrl,
 
219
                .ctrlbit        = (1 << 5),
 
220
        }, {
 
221
                .name           = "rtc",
 
222
                .parent         = &clk_pclk_low.clk,
 
223
                .enable         = s5p64x0_pclk_ctrl,
 
224
                .ctrlbit        = (1 << 6),
 
225
        }, {
 
226
                .name           = "adc",
 
227
                .parent         = &clk_pclk_low.clk,
 
228
                .enable         = s5p64x0_pclk_ctrl,
 
229
                .ctrlbit        = (1 << 12),
 
230
        }, {
 
231
                .name           = "i2c",
 
232
                .devname        = "s3c2440-i2c.0",
 
233
                .parent         = &clk_pclk_low.clk,
 
234
                .enable         = s5p64x0_pclk_ctrl,
 
235
                .ctrlbit        = (1 << 17),
 
236
        }, {
 
237
                .name           = "spi",
 
238
                .devname        = "s3c64xx-spi.0",
 
239
                .parent         = &clk_pclk_low.clk,
 
240
                .enable         = s5p64x0_pclk_ctrl,
 
241
                .ctrlbit        = (1 << 21),
 
242
        }, {
 
243
                .name           = "spi",
 
244
                .devname        = "s3c64xx-spi.1",
 
245
                .parent         = &clk_pclk_low.clk,
 
246
                .enable         = s5p64x0_pclk_ctrl,
 
247
                .ctrlbit        = (1 << 22),
 
248
        }, {
 
249
                .name           = "iis",
 
250
                .devname        = "samsung-i2s.0",
 
251
                .parent         = &clk_pclk_low.clk,
 
252
                .enable         = s5p64x0_pclk_ctrl,
 
253
                .ctrlbit        = (1 << 26),
 
254
        }, {
 
255
                .name           = "iis",
 
256
                .devname        = "samsung-i2s.1",
 
257
                .parent         = &clk_pclk_low.clk,
 
258
                .enable         = s5p64x0_pclk_ctrl,
 
259
                .ctrlbit        = (1 << 15),
 
260
        }, {
 
261
                .name           = "iis",
 
262
                .devname        = "samsung-i2s.2",
 
263
                .parent         = &clk_pclk_low.clk,
 
264
                .enable         = s5p64x0_pclk_ctrl,
 
265
                .ctrlbit        = (1 << 16),
 
266
        }, {
 
267
                .name           = "i2c",
 
268
                .devname        = "s3c2440-i2c.1",
 
269
                .parent         = &clk_pclk_low.clk,
 
270
                .enable         = s5p64x0_pclk_ctrl,
 
271
                .ctrlbit        = (1 << 27),
 
272
        }, {
 
273
                .name           = "dmc0",
 
274
                .parent         = &clk_pclk.clk,
 
275
                .enable         = s5p64x0_pclk_ctrl,
 
276
                .ctrlbit        = (1 << 30),
 
277
        }
 
278
};
 
279
 
 
280
/*
 
281
 * The following clocks will be enabled during clock initialization.
 
282
 */
 
283
static struct clk init_clocks[] = {
 
284
        {
 
285
                .name           = "intc",
 
286
                .parent         = &clk_hclk.clk,
 
287
                .enable         = s5p64x0_hclk0_ctrl,
 
288
                .ctrlbit        = (1 << 1),
 
289
        }, {
 
290
                .name           = "mem",
 
291
                .parent         = &clk_hclk.clk,
 
292
                .enable         = s5p64x0_hclk0_ctrl,
 
293
                .ctrlbit        = (1 << 21),
 
294
        }, {
 
295
                .name           = "uart",
 
296
                .devname        = "s3c6400-uart.0",
 
297
                .parent         = &clk_pclk_low.clk,
 
298
                .enable         = s5p64x0_pclk_ctrl,
 
299
                .ctrlbit        = (1 << 1),
 
300
        }, {
 
301
                .name           = "uart",
 
302
                .devname        = "s3c6400-uart.1",
 
303
                .parent         = &clk_pclk_low.clk,
 
304
                .enable         = s5p64x0_pclk_ctrl,
 
305
                .ctrlbit        = (1 << 2),
 
306
        }, {
 
307
                .name           = "uart",
 
308
                .devname        = "s3c6400-uart.2",
 
309
                .parent         = &clk_pclk_low.clk,
 
310
                .enable         = s5p64x0_pclk_ctrl,
 
311
                .ctrlbit        = (1 << 3),
 
312
        }, {
 
313
                .name           = "uart",
 
314
                .devname        = "s3c6400-uart.3",
 
315
                .parent         = &clk_pclk_low.clk,
 
316
                .enable         = s5p64x0_pclk_ctrl,
 
317
                .ctrlbit        = (1 << 4),
 
318
        }, {
 
319
                .name           = "timers",
 
320
                .parent         = &clk_pclk_to_wdt_pwm.clk,
 
321
                .enable         = s5p64x0_pclk_ctrl,
 
322
                .ctrlbit        = (1 << 7),
 
323
        }, {
 
324
                .name           = "gpio",
 
325
                .parent         = &clk_pclk_low.clk,
 
326
                .enable         = s5p64x0_pclk_ctrl,
 
327
                .ctrlbit        = (1 << 18),
 
328
        },
 
329
};
 
330
 
 
331
static struct clk *clkset_uart_list[] = {
 
332
        &clk_dout_epll.clk,
 
333
        &clk_dout_mpll.clk,
 
334
};
 
335
 
 
336
static struct clksrc_sources clkset_uart = {
 
337
        .sources        = clkset_uart_list,
 
338
        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 
339
};
 
340
 
 
341
static struct clk *clkset_mali_list[] = {
 
342
        &clk_mout_epll.clk,
 
343
        &clk_mout_apll.clk,
 
344
        &clk_mout_mpll.clk,
 
345
};
 
346
 
 
347
static struct clksrc_sources clkset_mali = {
 
348
        .sources        = clkset_mali_list,
 
349
        .nr_sources     = ARRAY_SIZE(clkset_mali_list),
 
350
};
 
351
 
 
352
static struct clk *clkset_group2_list[] = {
 
353
        &clk_dout_epll.clk,
 
354
        &clk_dout_mpll.clk,
 
355
        &clk_ext_xtal_mux,
 
356
};
 
357
 
 
358
static struct clksrc_sources clkset_group2 = {
 
359
        .sources        = clkset_group2_list,
 
360
        .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 
361
};
 
362
 
 
363
static struct clk *clkset_dispcon_list[] = {
 
364
        &clk_dout_epll.clk,
 
365
        &clk_dout_mpll.clk,
 
366
        &clk_ext_xtal_mux,
 
367
        &clk_mout_dpll.clk,
 
368
};
 
369
 
 
370
static struct clksrc_sources clkset_dispcon = {
 
371
        .sources        = clkset_dispcon_list,
 
372
        .nr_sources     = ARRAY_SIZE(clkset_dispcon_list),
 
373
};
 
374
 
 
375
static struct clk *clkset_hsmmc44_list[] = {
 
376
        &clk_dout_epll.clk,
 
377
        &clk_dout_mpll.clk,
 
378
        &clk_ext_xtal_mux,
 
379
        &s5p_clk_27m,
 
380
        &clk_48m,
 
381
};
 
382
 
 
383
static struct clksrc_sources clkset_hsmmc44 = {
 
384
        .sources        = clkset_hsmmc44_list,
 
385
        .nr_sources     = ARRAY_SIZE(clkset_hsmmc44_list),
 
386
};
 
387
 
 
388
static struct clk *clkset_sclk_audio0_list[] = {
 
389
        [0] = &clk_dout_epll.clk,
 
390
        [1] = &clk_dout_mpll.clk,
 
391
        [2] = &clk_ext_xtal_mux,
 
392
        [3] = NULL,
 
393
        [4] = NULL,
 
394
};
 
395
 
 
396
static struct clksrc_sources clkset_sclk_audio0 = {
 
397
        .sources        = clkset_sclk_audio0_list,
 
398
        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 
399
};
 
400
 
 
401
static struct clksrc_clk clk_sclk_audio0 = {
 
402
        .clk            = {
 
403
                .name           = "audio-bus",
 
404
                .enable         = s5p64x0_sclk_ctrl,
 
405
                .ctrlbit        = (1 << 8),
 
406
                .parent         = &clk_dout_epll.clk,
 
407
        },
 
408
        .sources        = &clkset_sclk_audio0,
 
409
        .reg_src        = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
 
410
        .reg_div        = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
 
411
};
 
412
 
 
413
static struct clksrc_clk clksrcs[] = {
 
414
        {
 
415
                .clk    = {
 
416
                        .name           = "sclk_mmc",
 
417
                        .devname        = "s3c-sdhci.0",
 
418
                        .ctrlbit        = (1 << 24),
 
419
                        .enable         = s5p64x0_sclk_ctrl,
 
420
                },
 
421
                .sources = &clkset_group2,
 
422
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
 
423
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
 
424
        }, {
 
425
                .clk    = {
 
426
                        .name           = "sclk_mmc",
 
427
                        .devname        = "s3c-sdhci.1",
 
428
                        .ctrlbit        = (1 << 25),
 
429
                        .enable         = s5p64x0_sclk_ctrl,
 
430
                },
 
431
                .sources = &clkset_group2,
 
432
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
 
433
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
 
434
        }, {
 
435
                .clk    = {
 
436
                        .name           = "sclk_mmc",
 
437
                        .devname        = "s3c-sdhci.2",
 
438
                        .ctrlbit        = (1 << 26),
 
439
                        .enable         = s5p64x0_sclk_ctrl,
 
440
                },
 
441
                .sources = &clkset_group2,
 
442
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
 
443
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
 
444
        }, {
 
445
                .clk    = {
 
446
                        .name           = "uclk1",
 
447
                        .ctrlbit        = (1 << 5),
 
448
                        .enable         = s5p64x0_sclk_ctrl,
 
449
                },
 
450
                .sources = &clkset_uart,
 
451
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
 
452
                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
 
453
        }, {
 
454
                .clk    = {
 
455
                        .name           = "sclk_spi",
 
456
                        .devname        = "s3c64xx-spi.0",
 
457
                        .ctrlbit        = (1 << 20),
 
458
                        .enable         = s5p64x0_sclk_ctrl,
 
459
                },
 
460
                .sources = &clkset_group2,
 
461
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
 
462
                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
 
463
        }, {
 
464
                .clk    = {
 
465
                        .name           = "sclk_spi",
 
466
                        .devname        = "s3c64xx-spi.1",
 
467
                        .ctrlbit        = (1 << 21),
 
468
                        .enable         = s5p64x0_sclk_ctrl,
 
469
                },
 
470
                .sources = &clkset_group2,
 
471
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
 
472
                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
 
473
        }, {
 
474
                .clk    = {
 
475
                        .name           = "sclk_fimc",
 
476
                        .ctrlbit        = (1 << 10),
 
477
                        .enable         = s5p64x0_sclk_ctrl,
 
478
                },
 
479
                .sources = &clkset_group2,
 
480
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
 
481
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
 
482
        }, {
 
483
                .clk    = {
 
484
                        .name           = "aclk_mali",
 
485
                        .ctrlbit        = (1 << 2),
 
486
                        .enable         = s5p64x0_sclk1_ctrl,
 
487
                },
 
488
                .sources = &clkset_mali,
 
489
                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
 
490
                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
 
491
        }, {
 
492
                .clk    = {
 
493
                        .name           = "sclk_2d",
 
494
                        .ctrlbit        = (1 << 12),
 
495
                        .enable         = s5p64x0_sclk_ctrl,
 
496
                },
 
497
                .sources = &clkset_mali,
 
498
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
 
499
                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
 
500
        }, {
 
501
                .clk    = {
 
502
                        .name           = "sclk_usi",
 
503
                        .ctrlbit        = (1 << 7),
 
504
                        .enable         = s5p64x0_sclk_ctrl,
 
505
                },
 
506
                .sources = &clkset_group2,
 
507
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
 
508
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
 
509
        }, {
 
510
                .clk    = {
 
511
                        .name           = "sclk_camif",
 
512
                        .ctrlbit        = (1 << 6),
 
513
                        .enable         = s5p64x0_sclk_ctrl,
 
514
                },
 
515
                .sources = &clkset_group2,
 
516
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
 
517
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
 
518
        }, {
 
519
                .clk    = {
 
520
                        .name           = "sclk_dispcon",
 
521
                        .ctrlbit        = (1 << 1),
 
522
                        .enable         = s5p64x0_sclk1_ctrl,
 
523
                },
 
524
                .sources = &clkset_dispcon,
 
525
                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
 
526
                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
 
527
        }, {
 
528
                .clk    = {
 
529
                        .name           = "sclk_hsmmc44",
 
530
                        .ctrlbit        = (1 << 30),
 
531
                        .enable         = s5p64x0_sclk_ctrl,
 
532
                },
 
533
                .sources = &clkset_hsmmc44,
 
534
                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
 
535
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
 
536
        },
 
537
};
 
538
 
 
539
/* Clock initialization code */
 
540
static struct clksrc_clk *sysclks[] = {
 
541
        &clk_mout_apll,
 
542
        &clk_mout_epll,
 
543
        &clk_dout_epll,
 
544
        &clk_mout_mpll,
 
545
        &clk_dout_mpll,
 
546
        &clk_armclk,
 
547
        &clk_mout_hclk_sel,
 
548
        &clk_dout_pwm_ratio0,
 
549
        &clk_pclk_to_wdt_pwm,
 
550
        &clk_hclk,
 
551
        &clk_pclk,
 
552
        &clk_hclk_low,
 
553
        &clk_pclk_low,
 
554
        &clk_sclk_audio0,
 
555
};
 
556
 
 
557
static struct clk dummy_apb_pclk = {
 
558
        .name           = "apb_pclk",
 
559
        .id             = -1,
 
560
};
 
561
 
 
562
void __init_or_cpufreq s5p6450_setup_clocks(void)
 
563
{
 
564
        struct clk *xtal_clk;
 
565
 
 
566
        unsigned long xtal;
 
567
        unsigned long fclk;
 
568
        unsigned long hclk;
 
569
        unsigned long hclk_low;
 
570
        unsigned long pclk;
 
571
        unsigned long pclk_low;
 
572
 
 
573
        unsigned long apll;
 
574
        unsigned long mpll;
 
575
        unsigned long epll;
 
576
        unsigned long dpll;
 
577
        unsigned int ptr;
 
578
 
 
579
        /* Set S5P6450 functions for clk_fout_epll */
 
580
 
 
581
        clk_fout_epll.enable = s5p_epll_enable;
 
582
        clk_fout_epll.ops = &s5p6450_epll_ops;
 
583
 
 
584
        clk_48m.enable = s5p64x0_clk48m_ctrl;
 
585
 
 
586
        xtal_clk = clk_get(NULL, "ext_xtal");
 
587
        BUG_ON(IS_ERR(xtal_clk));
 
588
 
 
589
        xtal = clk_get_rate(xtal_clk);
 
590
        clk_put(xtal_clk);
 
591
 
 
592
        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
 
593
        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
 
594
        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
 
595
                                __raw_readl(S5P64X0_EPLL_CON_K));
 
596
        dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
 
597
                                __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
 
598
 
 
599
        clk_fout_apll.rate = apll;
 
600
        clk_fout_mpll.rate = mpll;
 
601
        clk_fout_epll.rate = epll;
 
602
        clk_fout_dpll.rate = dpll;
 
603
 
 
604
        printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 
605
                        " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
 
606
                        print_mhz(apll), print_mhz(mpll), print_mhz(epll),
 
607
                        print_mhz(dpll));
 
608
 
 
609
        fclk = clk_get_rate(&clk_armclk.clk);
 
610
        hclk = clk_get_rate(&clk_hclk.clk);
 
611
        pclk = clk_get_rate(&clk_pclk.clk);
 
612
        hclk_low = clk_get_rate(&clk_hclk_low.clk);
 
613
        pclk_low = clk_get_rate(&clk_pclk_low.clk);
 
614
 
 
615
        printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 
616
                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 
617
                        print_mhz(hclk), print_mhz(hclk_low),
 
618
                        print_mhz(pclk), print_mhz(pclk_low));
 
619
 
 
620
        clk_f.rate = fclk;
 
621
        clk_h.rate = hclk;
 
622
        clk_p.rate = pclk;
 
623
 
 
624
        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 
625
                s3c_set_clksrc(&clksrcs[ptr], true);
 
626
}
 
627
 
 
628
void __init s5p6450_register_clocks(void)
 
629
{
 
630
        int ptr;
 
631
 
 
632
        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 
633
                s3c_register_clksrc(sysclks[ptr], 1);
 
634
 
 
635
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 
636
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
637
 
 
638
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
639
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
640
 
 
641
        s3c24xx_register_clock(&dummy_apb_pclk);
 
642
 
 
643
        s3c_pwmclk_init();
 
644
}