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Viewing changes to arch/arm/mach-bcmring/dma_device.c

  • Committer: Package Import Robot
  • Author(s): Alessio Igor Bogani
  • Date: 2011-10-26 11:13:05 UTC
  • Revision ID: package-import@ubuntu.com-20111026111305-tz023xykf0i6eosh
Tags: upstream-3.2.0
Import upstream version 3.2.0

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arch/arm/mach-bcmring/dma_device.c
 
1
/*****************************************************************************
 
2
* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
 
3
*
 
4
* Unless you and Broadcom execute a separate written software license
 
5
* agreement governing use of this software, this software is licensed to you
 
6
* under the terms of the GNU General Public License version 2, available at
 
7
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
 
8
*
 
9
* Notwithstanding the above, under no circumstances may you combine this
 
10
* software in any way with any other Broadcom software provided under a
 
11
* license other than the GPL, without Broadcom's express prior written
 
12
* consent.
 
13
*****************************************************************************/
 
14
 
 
15
/****************************************************************************/
 
16
/**
 
17
*   @file   dma_device.c
 
18
*
 
19
*   @brief  private array of DMA_DeviceAttribute_t
 
20
*/
 
21
/****************************************************************************/
 
22
 
 
23
DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
 
24
        [DMA_DEVICE_MEM_TO_MEM] =       /* MEM 2 MEM */
 
25
        {
 
26
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
 
27
         .name = "mem-to-mem",
 
28
         .config = {
 
29
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
30
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
31
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
 
32
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
33
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
34
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
35
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
36
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
37
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
38
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
39
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
40
 
 
41
                    },
 
42
         },
 
43
        [DMA_DEVICE_VPM_MEM_TO_MEM] =   /* VPM */
 
44
        {
 
45
         .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
 
46
         .name = "vpm",
 
47
         .dedicatedController = 0,
 
48
         .dedicatedChannel = 0,
 
49
         /* reserve DMA0:0 for VPM */
 
50
         },
 
51
        [DMA_DEVICE_NAND_MEM_TO_MEM] =  /* NAND */
 
52
        {
 
53
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
 
54
         .name = "nand",
 
55
         .config = {
 
56
                    .srcPeripheralPort = 0,
 
57
                    .dstPeripheralPort = 0,
 
58
                    .srcStatusRegisterAddress = 0x00000000,
 
59
                    .dstStatusRegisterAddress = 0x00000000,
 
60
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
 
61
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
62
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
63
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
64
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
65
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
66
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
67
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
68
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
69
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
 
70
                    },
 
71
         },
 
72
        [DMA_DEVICE_PIF_MEM_TO_DEV] =   /* PIF TX */
 
73
        {
 
74
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
 
75
         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
 
76
         | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
 
77
         .name = "pif_tx",
 
78
         .dmacPort = {14, 5},
 
79
         .config = {
 
80
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
81
                    /* dstPeripheralPort          = 5 or 14 */
 
82
                    .srcStatusRegisterAddress = 0x00000000,
 
83
                    .dstStatusRegisterAddress = 0x00000000,
 
84
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
85
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
86
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
87
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
88
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
 
89
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
90
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
91
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
92
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
93
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
94
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
 
95
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
 
96
                    .maxDataPerBlock = 16256,
 
97
                    },
 
98
         },
 
99
        [DMA_DEVICE_PIF_DEV_TO_MEM] =   /* PIF RX */
 
100
        {
 
101
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
 
102
         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
 
103
         /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
 
104
         | DMA_DEVICE_FLAG_PORT_PER_DMAC,
 
105
         .name = "pif_rx",
 
106
         .dmacPort = {14, 5},
 
107
         .config = {
 
108
                    /* srcPeripheralPort          = 5 or 14 */
 
109
                    .dstPeripheralPort = 0,     /* DST: memory */
 
110
                    .srcStatusRegisterAddress = 0x00000000,
 
111
                    .dstStatusRegisterAddress = 0x00000000,
 
112
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
113
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
114
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
115
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
116
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
117
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
118
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
119
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
120
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
121
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
122
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
 
123
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
 
124
                    .maxDataPerBlock = 16256,
 
125
                    },
 
126
         },
 
127
        [DMA_DEVICE_I2S0_DEV_TO_MEM] =  /* I2S RX */
 
128
        {
 
129
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
130
         .name = "i2s0_rx",
 
131
         .config = {
 
132
                    .srcPeripheralPort = 0,     /* SRC: I2S0 */
 
133
                    .dstPeripheralPort = 0,     /* DST: memory */
 
134
                    .srcStatusRegisterAddress = 0,
 
135
                    .dstStatusRegisterAddress = 0,
 
136
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
137
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
138
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
139
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
 
140
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
141
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
142
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
 
143
                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
144
                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
145
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
146
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
147
                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
 
148
                    },
 
149
         },
 
150
        [DMA_DEVICE_I2S0_MEM_TO_DEV] =  /* I2S TX */
 
151
        {
 
152
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
153
         .name = "i2s0_tx",
 
154
         .config = {
 
155
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
156
                    .dstPeripheralPort = 1,     /* DST: I2S0 */
 
157
                    .srcStatusRegisterAddress = 0,
 
158
                    .dstStatusRegisterAddress = 0,
 
159
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
160
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
161
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
162
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
163
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
 
164
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
 
165
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
166
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
167
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
168
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
169
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
170
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
171
                    },
 
172
         },
 
173
        [DMA_DEVICE_I2S1_DEV_TO_MEM] =  /* I2S1 RX */
 
174
        {
 
175
         .flags = DMA_DEVICE_FLAG_ON_DMA1,
 
176
         .name = "i2s1_rx",
 
177
         .config = {
 
178
                    .srcPeripheralPort = 2,     /* SRC: I2S1 */
 
179
                    .dstPeripheralPort = 0,     /* DST: memory */
 
180
                    .srcStatusRegisterAddress = 0,
 
181
                    .dstStatusRegisterAddress = 0,
 
182
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
183
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
184
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
185
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
 
186
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
187
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
188
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
 
189
                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
190
                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
191
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
192
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
193
                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
 
194
                    },
 
195
         },
 
196
        [DMA_DEVICE_I2S1_MEM_TO_DEV] =  /* I2S1 TX */
 
197
        {
 
198
         .flags = DMA_DEVICE_FLAG_ON_DMA1,
 
199
         .name = "i2s1_tx",
 
200
         .config = {
 
201
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
202
                    .dstPeripheralPort = 3,     /* DST: I2S1 */
 
203
                    .srcStatusRegisterAddress = 0,
 
204
                    .dstStatusRegisterAddress = 0,
 
205
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
206
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
207
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
208
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
209
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
 
210
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
 
211
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
212
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
213
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
214
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
215
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
216
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
217
                    },
 
218
         },
 
219
        [DMA_DEVICE_ESW_MEM_TO_DEV] =   /* ESW TX */
 
220
        {
 
221
         .name = "esw_tx",
 
222
         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
 
223
         .dedicatedController = 1,
 
224
         .dedicatedChannel = 3,
 
225
         .config = {
 
226
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
227
                    .dstPeripheralPort = 1,     /* DST: ESW (MTP) */
 
228
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
229
                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
 
230
                    /* DMAx_AHB_SSTATARy */
 
231
                    .srcStatusRegisterAddress = 0x00000000,
 
232
                    /* DMAx_AHB_DSTATARy */
 
233
                    .dstStatusRegisterAddress = 0x30490010,
 
234
                    /* DMAx_AHB_CFGy */
 
235
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
236
                    /* DMAx_AHB_CTLy */
 
237
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
238
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
239
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
240
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
 
241
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
 
242
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
243
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
244
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
245
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
246
                    },
 
247
         },
 
248
        [DMA_DEVICE_ESW_DEV_TO_MEM] =   /* ESW RX */
 
249
        {
 
250
         .name = "esw_rx",
 
251
         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
 
252
         .dedicatedController = 1,
 
253
         .dedicatedChannel = 2,
 
254
         .config = {
 
255
                    .srcPeripheralPort = 0,     /* SRC: ESW (PTM) */
 
256
                    .dstPeripheralPort = 0,     /* DST: memory */
 
257
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
258
                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
 
259
                    /* DMAx_AHB_SSTATARy */
 
260
                    .srcStatusRegisterAddress = 0x30480010,
 
261
                    /* DMAx_AHB_DSTATARy */
 
262
                    .dstStatusRegisterAddress = 0x00000000,
 
263
                    /* DMAx_AHB_CFGy */
 
264
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
265
                    /* DMAx_AHB_CTLy */
 
266
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
267
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
268
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
269
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
 
270
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
 
271
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
272
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
273
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
274
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
275
                    },
 
276
         },
 
277
        [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =   /* APM Codec A Ingress */
 
278
        {
 
279
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
280
         .name = "apm_a_rx",
 
281
         .config = {
 
282
                    .srcPeripheralPort = 2,     /* SRC: Codec A Ingress FIFO */
 
283
                    .dstPeripheralPort = 0,     /* DST: memory */
 
284
                    .srcStatusRegisterAddress = 0x00000000,
 
285
                    .dstStatusRegisterAddress = 0x00000000,
 
286
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
287
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
288
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
289
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
290
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
291
                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
292
                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
293
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
294
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
295
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
296
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
297
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
298
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
299
                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
 
300
                    },
 
301
         },
 
302
        [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =   /* APM Codec A Egress */
 
303
        {
 
304
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
305
         .name = "apm_a_tx",
 
306
         .config = {
 
307
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
308
                    .dstPeripheralPort = 3,     /* DST: Codec A Egress FIFO */
 
309
                    .srcStatusRegisterAddress = 0x00000000,
 
310
                    .dstStatusRegisterAddress = 0x00000000,
 
311
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
312
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
313
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
314
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
315
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
 
316
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
317
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
318
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
319
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
320
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
321
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
322
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
323
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
324
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
325
                    },
 
326
         },
 
327
        [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =   /* APM Codec B Ingress */
 
328
        {
 
329
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
330
         .name = "apm_b_rx",
 
331
         .config = {
 
332
                    .srcPeripheralPort = 4,     /* SRC: Codec B Ingress FIFO */
 
333
                    .dstPeripheralPort = 0,     /* DST: memory */
 
334
                    .srcStatusRegisterAddress = 0x00000000,
 
335
                    .dstStatusRegisterAddress = 0x00000000,
 
336
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
337
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
338
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
339
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
340
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
341
                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
342
                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
343
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
344
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
345
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
346
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
347
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
348
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
349
                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
 
350
                    },
 
351
         },
 
352
        [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =   /* APM Codec B Egress */
 
353
        {
 
354
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
355
         .name = "apm_b_tx",
 
356
         .config = {
 
357
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
358
                    .dstPeripheralPort = 5,     /* DST: Codec B Egress FIFO */
 
359
                    .srcStatusRegisterAddress = 0x00000000,
 
360
                    .dstStatusRegisterAddress = 0x00000000,
 
361
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
362
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
363
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
364
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
365
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
 
366
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
367
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
368
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
369
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
370
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
371
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
372
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
373
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
374
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
375
                    },
 
376
         },
 
377
        [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =   /* APM Codec C Ingress */
 
378
        {
 
379
         .flags = DMA_DEVICE_FLAG_ON_DMA1,
 
380
         .name = "apm_c_rx",
 
381
         .config = {
 
382
                    .srcPeripheralPort = 4,     /* SRC: Codec C Ingress FIFO */
 
383
                    .dstPeripheralPort = 0,     /* DST: memory */
 
384
                    .srcStatusRegisterAddress = 0x00000000,
 
385
                    .dstStatusRegisterAddress = 0x00000000,
 
386
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
387
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
388
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
389
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
390
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
391
                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
392
                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
393
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
394
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
395
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
396
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
397
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
398
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
399
                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
 
400
                    },
 
401
         },
 
402
        [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =      /* PCM0 RX */
 
403
        {
 
404
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
405
         .name = "pcm0_rx",
 
406
         .config = {
 
407
                    .srcPeripheralPort = 12,    /* SRC: PCM0 */
 
408
                    .dstPeripheralPort = 0,     /* DST: memory */
 
409
                    .srcStatusRegisterAddress = 0,
 
410
                    .dstStatusRegisterAddress = 0,
 
411
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
412
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
413
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
414
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
415
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
416
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
 
417
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
418
                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
419
                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
420
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
421
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
422
                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
 
423
                    },
 
424
         },
 
425
        [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =      /* PCM0 TX */
 
426
        {
 
427
         .flags = DMA_DEVICE_FLAG_ON_DMA0,
 
428
         .name = "pcm0_tx",
 
429
         .config = {
 
430
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
431
                    .dstPeripheralPort = 13,    /* DST: PCM0 */
 
432
                    .srcStatusRegisterAddress = 0,
 
433
                    .dstStatusRegisterAddress = 0,
 
434
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
435
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
436
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
 
437
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
438
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
439
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
440
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
 
441
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
442
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
443
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
444
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
445
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
446
                    },
 
447
         },
 
448
        [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =      /* PCM1 RX */
 
449
        {
 
450
         .flags = DMA_DEVICE_FLAG_ON_DMA1,
 
451
         .name = "pcm1_rx",
 
452
         .config = {
 
453
                    .srcPeripheralPort = 14,    /* SRC: PCM1 */
 
454
                    .dstPeripheralPort = 0,     /* DST: memory */
 
455
                    .srcStatusRegisterAddress = 0,
 
456
                    .dstStatusRegisterAddress = 0,
 
457
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
458
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
459
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
460
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
461
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
462
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
 
463
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
 
464
                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
465
                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
466
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
467
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
468
                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
 
469
                    },
 
470
         },
 
471
        [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =      /* PCM1 TX */
 
472
        {
 
473
         .flags = DMA_DEVICE_FLAG_ON_DMA1,
 
474
         .name = "pcm1_tx",
 
475
         .config = {
 
476
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
477
                    .dstPeripheralPort = 15,    /* DST: PCM1 */
 
478
                    .srcStatusRegisterAddress = 0,
 
479
                    .dstStatusRegisterAddress = 0,
 
480
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
481
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
482
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
 
483
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
484
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
485
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
 
486
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
 
487
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
488
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
489
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
490
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
491
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
492
                    },
 
493
         },
 
494
        [DMA_DEVICE_SPUM_DEV_TO_MEM] =  /* SPUM RX */
 
495
        {
 
496
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
 
497
         .name = "spum_rx",
 
498
         .config = {
 
499
                    .srcPeripheralPort = 6,     /* SRC: Codec A Ingress FIFO */
 
500
                    .dstPeripheralPort = 0,     /* DST: memory */
 
501
                    .srcStatusRegisterAddress = 0x00000000,
 
502
                    .dstStatusRegisterAddress = 0x00000000,
 
503
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
504
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
505
                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
 
506
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
507
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
508
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
509
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
510
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
511
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
512
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
513
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
514
                    /* Busrt size **MUST** be 16 for SPUM to work */
 
515
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
 
516
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
 
517
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
518
                    /* on the RX side, SPU needs to be the flow controller */
 
519
                    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
 
520
                    },
 
521
         },
 
522
        [DMA_DEVICE_SPUM_MEM_TO_DEV] =  /* SPUM TX */
 
523
        {
 
524
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
 
525
         .name = "spum_tx",
 
526
         .config = {
 
527
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
528
                    .dstPeripheralPort = 7,     /* DST: SPUM */
 
529
                    .srcStatusRegisterAddress = 0x00000000,
 
530
                    .dstStatusRegisterAddress = 0x00000000,
 
531
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
532
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
533
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
 
534
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
535
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
 
536
                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
 
537
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
538
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
539
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
540
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
 
541
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
 
542
                    /* Busrt size **MUST** be 16 for SPUM to work */
 
543
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
 
544
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
 
545
                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
 
546
                    },
 
547
         },
 
548
        [DMA_DEVICE_MEM_TO_VRAM] =      /* MEM 2 VRAM */
 
549
        {
 
550
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
 
551
         .name = "mem-to-vram",
 
552
         .config = {
 
553
                    .srcPeripheralPort = 0,     /* SRC: memory */
 
554
                    .srcStatusRegisterAddress = 0x00000000,
 
555
                    .dstStatusRegisterAddress = 0x00000000,
 
556
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
557
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
558
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
 
559
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
 
560
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
 
561
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
562
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
563
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
564
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
565
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
566
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
 
567
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
 
568
                    },
 
569
         },
 
570
        [DMA_DEVICE_VRAM_TO_MEM] =      /* VRAM 2 MEM */
 
571
        {
 
572
         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
 
573
         .name = "vram-to-mem",
 
574
         .config = {
 
575
                    .dstPeripheralPort = 0,     /* DST: memory */
 
576
                    .srcStatusRegisterAddress = 0x00000000,
 
577
                    .dstStatusRegisterAddress = 0x00000000,
 
578
                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
 
579
                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
 
580
                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
 
581
                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
 
582
                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
 
583
                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
 
584
                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
 
585
                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
 
586
                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
 
587
                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
 
588
                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
 
589
                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
 
590
                    },
 
591
         },
 
592
};
 
593
EXPORT_SYMBOL(DMA_gDeviceAttribute);    /* primarily for dma-test.c */