2
* Copyright 2009-2010 Pengutronix
3
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
5
* loosely based on an earlier driver that has
6
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
8
* This program is free software; you can redistribute it and/or modify it under
9
* the terms of the GNU General Public License version 2 as published by the
10
* Free Software Foundation.
13
#include <linux/slab.h>
14
#include <linux/module.h>
15
#include <linux/platform_device.h>
16
#include <linux/mutex.h>
17
#include <linux/interrupt.h>
18
#include <linux/spi/spi.h>
19
#include <linux/mfd/core.h>
20
#include <linux/mfd/mc13xxx.h>
23
struct spi_device *spidev;
27
irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
28
void *irqdata[MC13XXX_NUM_IRQ];
33
#define MC13XXX_IRQSTAT0 0
34
#define MC13XXX_IRQSTAT0_ADCDONEI (1 << 0)
35
#define MC13XXX_IRQSTAT0_ADCBISDONEI (1 << 1)
36
#define MC13XXX_IRQSTAT0_TSI (1 << 2)
37
#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
38
#define MC13783_IRQSTAT0_WLOWI (1 << 4)
39
#define MC13XXX_IRQSTAT0_CHGDETI (1 << 6)
40
#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
41
#define MC13XXX_IRQSTAT0_CHGREVI (1 << 8)
42
#define MC13XXX_IRQSTAT0_CHGSHORTI (1 << 9)
43
#define MC13XXX_IRQSTAT0_CCCVI (1 << 10)
44
#define MC13XXX_IRQSTAT0_CHGCURRI (1 << 11)
45
#define MC13XXX_IRQSTAT0_BPONI (1 << 12)
46
#define MC13XXX_IRQSTAT0_LOBATLI (1 << 13)
47
#define MC13XXX_IRQSTAT0_LOBATHI (1 << 14)
48
#define MC13783_IRQSTAT0_UDPI (1 << 15)
49
#define MC13783_IRQSTAT0_USBI (1 << 16)
50
#define MC13783_IRQSTAT0_IDI (1 << 19)
51
#define MC13783_IRQSTAT0_SE1I (1 << 21)
52
#define MC13783_IRQSTAT0_CKDETI (1 << 22)
53
#define MC13783_IRQSTAT0_UDMI (1 << 23)
55
#define MC13XXX_IRQMASK0 1
56
#define MC13XXX_IRQMASK0_ADCDONEM MC13XXX_IRQSTAT0_ADCDONEI
57
#define MC13XXX_IRQMASK0_ADCBISDONEM MC13XXX_IRQSTAT0_ADCBISDONEI
58
#define MC13XXX_IRQMASK0_TSM MC13XXX_IRQSTAT0_TSI
59
#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
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#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
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#define MC13XXX_IRQMASK0_CHGDETM MC13XXX_IRQSTAT0_CHGDETI
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#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
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#define MC13XXX_IRQMASK0_CHGREVM MC13XXX_IRQSTAT0_CHGREVI
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#define MC13XXX_IRQMASK0_CHGSHORTM MC13XXX_IRQSTAT0_CHGSHORTI
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#define MC13XXX_IRQMASK0_CCCVM MC13XXX_IRQSTAT0_CCCVI
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#define MC13XXX_IRQMASK0_CHGCURRM MC13XXX_IRQSTAT0_CHGCURRI
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#define MC13XXX_IRQMASK0_BPONM MC13XXX_IRQSTAT0_BPONI
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#define MC13XXX_IRQMASK0_LOBATLM MC13XXX_IRQSTAT0_LOBATLI
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#define MC13XXX_IRQMASK0_LOBATHM MC13XXX_IRQSTAT0_LOBATHI
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#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
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#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
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#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
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#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
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#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
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#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
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#define MC13XXX_IRQSTAT1 3
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#define MC13XXX_IRQSTAT1_1HZI (1 << 0)
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#define MC13XXX_IRQSTAT1_TODAI (1 << 1)
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#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
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#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
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#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
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#define MC13XXX_IRQSTAT1_SYSRSTI (1 << 6)
84
#define MC13XXX_IRQSTAT1_RTCRSTI (1 << 7)
85
#define MC13XXX_IRQSTAT1_PCI (1 << 8)
86
#define MC13XXX_IRQSTAT1_WARMI (1 << 9)
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#define MC13XXX_IRQSTAT1_MEMHLDI (1 << 10)
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#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
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#define MC13XXX_IRQSTAT1_THWARNLI (1 << 12)
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#define MC13XXX_IRQSTAT1_THWARNHI (1 << 13)
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#define MC13XXX_IRQSTAT1_CLKI (1 << 14)
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#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
93
#define MC13783_IRQSTAT1_MC2BI (1 << 17)
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#define MC13783_IRQSTAT1_HSDETI (1 << 18)
95
#define MC13783_IRQSTAT1_HSLI (1 << 19)
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#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
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#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
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#define MC13XXX_IRQMASK1 4
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#define MC13XXX_IRQMASK1_1HZM MC13XXX_IRQSTAT1_1HZI
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#define MC13XXX_IRQMASK1_TODAM MC13XXX_IRQSTAT1_TODAI
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#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
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#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
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#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
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#define MC13XXX_IRQMASK1_SYSRSTM MC13XXX_IRQSTAT1_SYSRSTI
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#define MC13XXX_IRQMASK1_RTCRSTM MC13XXX_IRQSTAT1_RTCRSTI
107
#define MC13XXX_IRQMASK1_PCM MC13XXX_IRQSTAT1_PCI
108
#define MC13XXX_IRQMASK1_WARMM MC13XXX_IRQSTAT1_WARMI
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#define MC13XXX_IRQMASK1_MEMHLDM MC13XXX_IRQSTAT1_MEMHLDI
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#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
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#define MC13XXX_IRQMASK1_THWARNLM MC13XXX_IRQSTAT1_THWARNLI
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#define MC13XXX_IRQMASK1_THWARNHM MC13XXX_IRQSTAT1_THWARNHI
113
#define MC13XXX_IRQMASK1_CLKM MC13XXX_IRQSTAT1_CLKI
114
#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
115
#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
116
#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
117
#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
118
#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
119
#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
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#define MC13XXX_REVISION 7
122
#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
123
#define MC13XXX_REVISION_REVFULL (0x03 << 3)
124
#define MC13XXX_REVISION_ICID (0x07 << 6)
125
#define MC13XXX_REVISION_FIN (0x03 << 9)
126
#define MC13XXX_REVISION_FAB (0x03 << 11)
127
#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
129
#define MC13XXX_ADC1 44
130
#define MC13XXX_ADC1_ADEN (1 << 0)
131
#define MC13XXX_ADC1_RAND (1 << 1)
132
#define MC13XXX_ADC1_ADSEL (1 << 3)
133
#define MC13XXX_ADC1_ASC (1 << 20)
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#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
136
#define MC13XXX_ADC2 45
138
#define MC13XXX_NUMREGS 0x3f
140
void mc13xxx_lock(struct mc13xxx *mc13xxx)
142
if (!mutex_trylock(&mc13xxx->lock)) {
143
dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
144
__func__, __builtin_return_address(0));
146
mutex_lock(&mc13xxx->lock);
148
dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
149
__func__, __builtin_return_address(0));
151
EXPORT_SYMBOL(mc13xxx_lock);
153
void mc13xxx_unlock(struct mc13xxx *mc13xxx)
155
dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
156
__func__, __builtin_return_address(0));
157
mutex_unlock(&mc13xxx->lock);
159
EXPORT_SYMBOL(mc13xxx_unlock);
161
#define MC13XXX_REGOFFSET_SHIFT 25
162
int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
164
struct spi_transfer t;
165
struct spi_message m;
168
BUG_ON(!mutex_is_locked(&mc13xxx->lock));
170
if (offset > MC13XXX_NUMREGS)
173
*val = offset << MC13XXX_REGOFFSET_SHIFT;
175
memset(&t, 0, sizeof(t));
181
spi_message_init(&m);
182
spi_message_add_tail(&t, &m);
184
ret = spi_sync(mc13xxx->spidev, &m);
186
/* error in message.status implies error return from spi_sync */
187
BUG_ON(!ret && m.status);
194
dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
198
EXPORT_SYMBOL(mc13xxx_reg_read);
200
int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
203
struct spi_transfer t;
204
struct spi_message m;
207
BUG_ON(!mutex_is_locked(&mc13xxx->lock));
209
dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
211
if (offset > MC13XXX_NUMREGS || val > 0xffffff)
214
buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
216
memset(&t, 0, sizeof(t));
222
spi_message_init(&m);
223
spi_message_add_tail(&t, &m);
225
ret = spi_sync(mc13xxx->spidev, &m);
227
BUG_ON(!ret && m.status);
234
EXPORT_SYMBOL(mc13xxx_reg_write);
236
int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
244
ret = mc13xxx_reg_read(mc13xxx, offset, &valread);
248
valread = (valread & ~mask) | val;
250
return mc13xxx_reg_write(mc13xxx, offset, valread);
252
EXPORT_SYMBOL(mc13xxx_reg_rmw);
254
int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
257
unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
258
u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
261
if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
264
ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
272
return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
274
EXPORT_SYMBOL(mc13xxx_irq_mask);
276
int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
279
unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
280
u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
283
if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
286
ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
290
if (!(mask & irqbit))
291
/* already unmasked */
294
return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
296
EXPORT_SYMBOL(mc13xxx_irq_unmask);
298
int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
299
int *enabled, int *pending)
302
unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
303
unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
304
u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
306
if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
312
ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
316
*enabled = mask & irqbit;
322
ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
326
*pending = stat & irqbit;
331
EXPORT_SYMBOL(mc13xxx_irq_status);
333
int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
335
unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
336
unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
338
BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
340
return mc13xxx_reg_write(mc13xxx, offstat, val);
342
EXPORT_SYMBOL(mc13xxx_irq_ack);
344
int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
345
irq_handler_t handler, const char *name, void *dev)
347
BUG_ON(!mutex_is_locked(&mc13xxx->lock));
350
if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
353
if (mc13xxx->irqhandler[irq])
356
mc13xxx->irqhandler[irq] = handler;
357
mc13xxx->irqdata[irq] = dev;
361
EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
363
int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
364
irq_handler_t handler, const char *name, void *dev)
368
ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
372
ret = mc13xxx_irq_unmask(mc13xxx, irq);
374
mc13xxx->irqhandler[irq] = NULL;
375
mc13xxx->irqdata[irq] = NULL;
381
EXPORT_SYMBOL(mc13xxx_irq_request);
383
int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
386
BUG_ON(!mutex_is_locked(&mc13xxx->lock));
388
if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
389
mc13xxx->irqdata[irq] != dev)
392
ret = mc13xxx_irq_mask(mc13xxx, irq);
396
mc13xxx->irqhandler[irq] = NULL;
397
mc13xxx->irqdata[irq] = NULL;
401
EXPORT_SYMBOL(mc13xxx_irq_free);
403
static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
405
return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
409
* returns: number of handled irqs or negative error
410
* locking: holds mc13xxx->lock
412
static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
413
unsigned int offstat, unsigned int offmask, int baseirq)
416
int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
422
ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
426
while (stat & ~mask) {
427
int irq = __ffs(stat & ~mask);
431
if (likely(mc13xxx->irqhandler[baseirq + irq])) {
434
handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
435
if (handled == IRQ_HANDLED)
438
dev_err(&mc13xxx->spidev->dev,
439
"BUG: irq %u but no handler\n",
444
ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
451
static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
453
struct mc13xxx *mc13xxx = data;
457
mc13xxx_lock(mc13xxx);
459
ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
460
MC13XXX_IRQMASK0, 0);
464
ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
465
MC13XXX_IRQMASK1, 24);
469
mc13xxx_unlock(mc13xxx);
471
return IRQ_RETVAL(handled);
480
static const char *mc13xxx_chipname[] = {
481
[MC13XXX_ID_MC13783] = "mc13783",
482
[MC13XXX_ID_MC13892] = "mc13892",
485
#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
486
static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
493
ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
497
icid = (icid >> 6) & 0x7;
501
*id = MC13XXX_ID_MC13783;
505
*id = MC13XXX_ID_MC13892;
509
*id = MC13XXX_ID_INVALID;
513
if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
514
ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
518
dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
519
"fin: %d, fab: %d, icid: %d/%d\n",
520
mc13xxx_chipname[*id],
521
maskval(revision, MC13XXX_REVISION_REVFULL),
522
maskval(revision, MC13XXX_REVISION_REVMETAL),
523
maskval(revision, MC13XXX_REVISION_FIN),
524
maskval(revision, MC13XXX_REVISION_FAB),
525
maskval(revision, MC13XXX_REVISION_ICID),
526
maskval(revision, MC13XXX_REVISION_ICIDCODE));
529
if (*id != MC13XXX_ID_INVALID) {
530
const struct spi_device_id *devid =
531
spi_get_device_id(mc13xxx->spidev);
532
if (!devid || devid->driver_data != *id)
533
dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
534
"match auto detection!\n");
540
static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
542
const struct spi_device_id *devid =
543
spi_get_device_id(mc13xxx->spidev);
548
return mc13xxx_chipname[devid->driver_data];
551
int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
553
struct mc13xxx_platform_data *pdata =
554
dev_get_platdata(&mc13xxx->spidev->dev);
558
EXPORT_SYMBOL(mc13xxx_get_flags);
560
#define MC13XXX_ADC1_CHAN0_SHIFT 5
561
#define MC13XXX_ADC1_CHAN1_SHIFT 8
563
struct mc13xxx_adcdone_data {
564
struct mc13xxx *mc13xxx;
565
struct completion done;
568
static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
570
struct mc13xxx_adcdone_data *adcdone_data = data;
572
mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
574
complete_all(&adcdone_data->done);
579
#define MC13XXX_ADC_WORKING (1 << 0)
581
int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
582
unsigned int channel, unsigned int *sample)
584
u32 adc0, adc1, old_adc0;
586
struct mc13xxx_adcdone_data adcdone_data = {
589
init_completion(&adcdone_data.done);
591
dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
593
mc13xxx_lock(mc13xxx);
595
if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
600
mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
602
mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
604
adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
605
adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
608
adc1 |= MC13XXX_ADC1_ADSEL;
611
case MC13XXX_ADC_MODE_TS:
612
adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
614
adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
617
case MC13XXX_ADC_MODE_SINGLE_CHAN:
618
adc0 |= old_adc0 & MC13XXX_ADC0_TSMOD_MASK;
619
adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
620
adc1 |= MC13XXX_ADC1_RAND;
623
case MC13XXX_ADC_MODE_MULT_CHAN:
624
adc0 |= old_adc0 & MC13XXX_ADC0_TSMOD_MASK;
625
adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
629
mc13xxx_unlock(mc13xxx);
633
dev_dbg(&mc13xxx->spidev->dev, "%s: request irq\n", __func__);
634
mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
635
mc13xxx_handler_adcdone, __func__, &adcdone_data);
636
mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
638
mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
639
mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
641
mc13xxx_unlock(mc13xxx);
643
ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
648
mc13xxx_lock(mc13xxx);
650
mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
653
for (i = 0; i < 4; ++i) {
654
ret = mc13xxx_reg_read(mc13xxx,
655
MC13XXX_ADC2, &sample[i]);
660
if (mode == MC13XXX_ADC_MODE_TS)
662
mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
664
mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
666
mc13xxx_unlock(mc13xxx);
670
EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
672
static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
673
const char *format, void *pdata, size_t pdata_size)
676
const char *name = mc13xxx_get_chipname(mc13xxx);
678
struct mfd_cell cell = {
679
.platform_data = pdata,
680
.pdata_size = pdata_size,
683
/* there is no asnprintf in the kernel :-( */
684
if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
687
cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
691
return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
694
static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
696
return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
699
static int mc13xxx_probe(struct spi_device *spi)
701
struct mc13xxx *mc13xxx;
702
struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
707
dev_err(&spi->dev, "invalid platform data\n");
711
mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
715
dev_set_drvdata(&spi->dev, mc13xxx);
716
spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
717
spi->bits_per_word = 32;
720
mc13xxx->spidev = spi;
722
mutex_init(&mc13xxx->lock);
723
mc13xxx_lock(mc13xxx);
725
ret = mc13xxx_identify(mc13xxx, &id);
726
if (ret || id == MC13XXX_ID_INVALID)
730
ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
734
ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
738
ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
739
IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
744
mc13xxx_unlock(mc13xxx);
745
dev_set_drvdata(&spi->dev, NULL);
750
mc13xxx_unlock(mc13xxx);
752
if (pdata->flags & MC13XXX_USE_ADC)
753
mc13xxx_add_subdevice(mc13xxx, "%s-adc");
755
if (pdata->flags & MC13XXX_USE_CODEC)
756
mc13xxx_add_subdevice(mc13xxx, "%s-codec");
758
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
759
&pdata->regulators, sizeof(pdata->regulators));
761
if (pdata->flags & MC13XXX_USE_RTC)
762
mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
764
if (pdata->flags & MC13XXX_USE_TOUCHSCREEN)
765
mc13xxx_add_subdevice(mc13xxx, "%s-ts");
768
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
769
pdata->leds, sizeof(*pdata->leds));
772
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
773
pdata->buttons, sizeof(*pdata->buttons));
778
static int __devexit mc13xxx_remove(struct spi_device *spi)
780
struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
782
free_irq(mc13xxx->spidev->irq, mc13xxx);
784
mfd_remove_devices(&spi->dev);
791
static const struct spi_device_id mc13xxx_device_id[] = {
794
.driver_data = MC13XXX_ID_MC13783,
797
.driver_data = MC13XXX_ID_MC13892,
802
MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
804
static struct spi_driver mc13xxx_driver = {
805
.id_table = mc13xxx_device_id,
808
.bus = &spi_bus_type,
809
.owner = THIS_MODULE,
811
.probe = mc13xxx_probe,
812
.remove = __devexit_p(mc13xxx_remove),
815
static int __init mc13xxx_init(void)
817
return spi_register_driver(&mc13xxx_driver);
819
subsys_initcall(mc13xxx_init);
821
static void __exit mc13xxx_exit(void)
823
spi_unregister_driver(&mc13xxx_driver);
825
module_exit(mc13xxx_exit);
827
MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
828
MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
829
MODULE_LICENSE("GPL v2");