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* A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
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* Copyright (C) 2008-2009 ST-Ericsson AB
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* Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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* Initial version inspired by:
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* linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
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* Initial adoption to PL022 by:
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* Sachin Verma <sachin.verma@st.com>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/workqueue.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl022.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <linux/pm_runtime.h>
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* This macro is used to define some register default values.
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* reg is masked with mask, the OR:ed with an (again masked)
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* val shifted sb steps to the left.
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#define SSP_WRITE_BITS(reg, val, mask, sb) \
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((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
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* This macro is also used to define some default values.
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* It will just shift val by sb steps to the left and mask
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* the result with mask.
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#define GEN_MASK_BITS(val, mask, sb) \
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(((val)<<(sb)) & (mask))
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#define DO_NOT_DRIVE_TX 1
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#define DO_NOT_QUEUE_DMA 0
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* Macros to access SSP Registers with their offsets
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#define SSP_CR0(r) (r + 0x000)
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#define SSP_CR1(r) (r + 0x004)
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#define SSP_DR(r) (r + 0x008)
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#define SSP_SR(r) (r + 0x00C)
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#define SSP_CPSR(r) (r + 0x010)
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#define SSP_IMSC(r) (r + 0x014)
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#define SSP_RIS(r) (r + 0x018)
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#define SSP_MIS(r) (r + 0x01C)
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#define SSP_ICR(r) (r + 0x020)
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#define SSP_DMACR(r) (r + 0x024)
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#define SSP_ITCR(r) (r + 0x080)
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#define SSP_ITIP(r) (r + 0x084)
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#define SSP_ITOP(r) (r + 0x088)
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#define SSP_TDR(r) (r + 0x08C)
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#define SSP_PID0(r) (r + 0xFE0)
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#define SSP_PID1(r) (r + 0xFE4)
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#define SSP_PID2(r) (r + 0xFE8)
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#define SSP_PID3(r) (r + 0xFEC)
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#define SSP_CID0(r) (r + 0xFF0)
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#define SSP_CID1(r) (r + 0xFF4)
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#define SSP_CID2(r) (r + 0xFF8)
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#define SSP_CID3(r) (r + 0xFFC)
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* SSP Control Register 0 - SSP_CR0
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#define SSP_CR0_MASK_DSS (0x0FUL << 0)
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#define SSP_CR0_MASK_FRF (0x3UL << 4)
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#define SSP_CR0_MASK_SPO (0x1UL << 6)
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#define SSP_CR0_MASK_SPH (0x1UL << 7)
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#define SSP_CR0_MASK_SCR (0xFFUL << 8)
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* The ST version of this block moves som bits
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* in SSP_CR0 and extends it to 32 bits
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#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
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#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
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#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
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#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
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* SSP Control Register 0 - SSP_CR1
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#define SSP_CR1_MASK_LBM (0x1UL << 0)
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#define SSP_CR1_MASK_SSE (0x1UL << 1)
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#define SSP_CR1_MASK_MS (0x1UL << 2)
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#define SSP_CR1_MASK_SOD (0x1UL << 3)
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* The ST version of this block adds some bits
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#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
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#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
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#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
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#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
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#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
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/* This one is only in the PL023 variant */
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#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
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* SSP Status Register - SSP_SR
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#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
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#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
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#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
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#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
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#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
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* SSP Clock Prescale Register - SSP_CPSR
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#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
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* SSP Interrupt Mask Set/Clear Register - SSP_IMSC
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#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
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#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
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#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
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#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
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* SSP Raw Interrupt Status Register - SSP_RIS
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/* Receive Overrun Raw Interrupt status */
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#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
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/* Receive Timeout Raw Interrupt status */
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#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
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/* Receive FIFO Raw Interrupt status */
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#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
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/* Transmit FIFO Raw Interrupt status */
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#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
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* SSP Masked Interrupt Status Register - SSP_MIS
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/* Receive Overrun Masked Interrupt status */
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#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
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/* Receive Timeout Masked Interrupt status */
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#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
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/* Receive FIFO Masked Interrupt status */
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#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
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/* Transmit FIFO Masked Interrupt status */
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#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
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* SSP Interrupt Clear Register - SSP_ICR
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/* Receive Overrun Raw Clear Interrupt bit */
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#define SSP_ICR_MASK_RORIC (0x1UL << 0)
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/* Receive Timeout Clear Interrupt bit */
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#define SSP_ICR_MASK_RTIC (0x1UL << 1)
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* SSP DMA Control Register - SSP_DMACR
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/* Receive DMA Enable bit */
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#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
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/* Transmit DMA Enable bit */
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#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
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* SSP Integration Test control Register - SSP_ITCR
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#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
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#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
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* SSP Integration Test Input Register - SSP_ITIP
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#define ITIP_MASK_SSPRXD (0x1UL << 0)
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#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
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#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
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#define ITIP_MASK_RXDMAC (0x1UL << 3)
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#define ITIP_MASK_TXDMAC (0x1UL << 4)
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#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
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* SSP Integration Test output Register - SSP_ITOP
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#define ITOP_MASK_SSPTXD (0x1UL << 0)
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#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
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#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
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#define ITOP_MASK_SSPOEn (0x1UL << 3)
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#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
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#define ITOP_MASK_RORINTR (0x1UL << 5)
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#define ITOP_MASK_RTINTR (0x1UL << 6)
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#define ITOP_MASK_RXINTR (0x1UL << 7)
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#define ITOP_MASK_TXINTR (0x1UL << 8)
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#define ITOP_MASK_INTR (0x1UL << 9)
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#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
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#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
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#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
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#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
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* SSP Test Data Register - SSP_TDR
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#define TDR_MASK_TESTDATA (0xFFFFFFFF)
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* we use the spi_message.state (void *) pointer to
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* hold a single state value, that's why all this
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* (void *) casting is done here.
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#define STATE_START ((void *) 0)
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#define STATE_RUNNING ((void *) 1)
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#define STATE_DONE ((void *) 2)
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#define STATE_ERROR ((void *) -1)
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* SSP State - Whether Enabled or Disabled
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#define SSP_DISABLED (0)
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#define SSP_ENABLED (1)
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* SSP DMA State - Whether DMA Enabled or Disabled
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#define SSP_DMA_DISABLED (0)
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#define SSP_DMA_ENABLED (1)
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#define SSP_DEFAULT_CLKRATE 0x2
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#define SSP_DEFAULT_PRESCALE 0x40
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* SSP Clock Parameter ranges
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#define CPSDVR_MIN 0x02
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#define CPSDVR_MAX 0xFE
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* SSP Interrupt related Macros
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#define DEFAULT_SSP_REG_IMSC 0x0UL
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#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
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#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
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#define CLEAR_ALL_INTERRUPTS 0x3
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#define SPI_POLLING_TIMEOUT 1000
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* The type of reading going on on this chip
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* The type of writing going on on this chip
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* struct vendor_data - vendor-specific config parameters
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* for PL022 derivates
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* @fifodepth: depth of FIFOs (both)
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* @max_bpw: maximum number of bits per word
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* @unidir: supports unidirection transfers
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* @extended_cr: 32 bit wide control register 0 with extra
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* features and extra features in CR1 as found in the ST variants
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* @pl023: supports a subset of the ST extensions called "PL023"
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* struct pl022 - This is the private SSP driver data structure
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* @adev: AMBA device model hookup
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* @vendor: vendor data for the IP block
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* @phybase: the physical memory where the SSP device resides
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* @virtbase: the virtual memory where the SSP is mapped
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* @clk: outgoing clock "SPICLK" for the SPI bus
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* @master: SPI framework hookup
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* @master_info: controller-specific data from machine setup
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* @workqueue: a workqueue on which any spi_message request is queued
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* @pump_messages: work struct for scheduling work to the workqueue
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* @queue_lock: spinlock to syncronise access to message queue
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* @queue: message queue
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* @busy: workqueue is busy
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* @running: workqueue is running
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* @pump_transfers: Tasklet used in Interrupt Transfer mode
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* @cur_msg: Pointer to current spi_message being processed
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* @cur_transfer: Pointer to current spi_transfer
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* @cur_chip: pointer to current clients chip(assigned from controller_state)
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* @tx: current position in TX buffer to be read
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* @tx_end: end position in TX buffer to be read
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* @rx: current position in RX buffer to be written
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* @rx_end: end position in RX buffer to be written
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* @read: the type of read currently going on
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* @write: the type of write currently going on
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* @exp_fifo_level: expected FIFO level
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* @dma_rx_channel: optional channel for RX DMA
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* @dma_tx_channel: optional channel for TX DMA
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* @sgt_rx: scattertable for the RX transfer
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* @sgt_tx: scattertable for the TX transfer
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* @dummypage: a dummy page used for driving data on the bus with DMA
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struct amba_device *adev;
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struct vendor_data *vendor;
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resource_size_t phybase;
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void __iomem *virtbase;
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struct spi_master *master;
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struct pl022_ssp_controller *master_info;
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/* Driver message queue */
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struct workqueue_struct *workqueue;
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struct work_struct pump_messages;
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spinlock_t queue_lock;
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struct list_head queue;
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/* Message transfer pump */
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struct tasklet_struct pump_transfers;
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struct spi_message *cur_msg;
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struct spi_transfer *cur_transfer;
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struct chip_data *cur_chip;
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enum ssp_reading read;
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enum ssp_writing write;
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enum ssp_rx_level_trig rx_lev_trig;
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enum ssp_tx_level_trig tx_lev_trig;
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#ifdef CONFIG_DMA_ENGINE
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struct dma_chan *dma_rx_channel;
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struct dma_chan *dma_tx_channel;
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struct sg_table sgt_rx;
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struct sg_table sgt_tx;
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* struct chip_data - To maintain runtime state of SSP for each client chip
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* @cr0: Value of control register CR0 of SSP - on later ST variants this
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* register is 32 bits wide rather than just 16
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* @cr1: Value of control register CR1 of SSP
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* @dmacr: Value of DMA control Register of SSP
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* @cpsr: Value of Clock prescale register
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* @n_bytes: how many bytes(power of 2) reqd for a given data width of client
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* @enable_dma: Whether to enable DMA or not
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* @read: function ptr to be used to read when doing xfer for this chip
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* @write: function ptr to be used to write when doing xfer for this chip
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* @cs_control: chip select callback provided by chip
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* @xfer_type: polling/interrupt/DMA
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* Runtime state of the SSP controller, maintained per chip,
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* This would be set according to the current message that would be served
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enum ssp_reading read;
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enum ssp_writing write;
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void (*cs_control) (u32 command);
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* null_cs_control - Dummy chip select function
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* @command: select/delect the chip
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* If no chip select function is provided by client this is used as dummy
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static void null_cs_control(u32 command)
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pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
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* giveback - current spi_message is over, schedule next message and call
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* callback of this message. Assumes that caller already
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* set message->status; dma and pio irqs are blocked
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* @pl022: SSP driver private data structure
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static void giveback(struct pl022 *pl022)
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struct spi_transfer *last_transfer;
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struct spi_message *msg;
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void (*curr_cs_control) (u32 command);
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* This local reference to the chip select function
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* is needed because we set curr_chip to NULL
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* as a step toward termininating the message.
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curr_cs_control = pl022->cur_chip->cs_control;
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spin_lock_irqsave(&pl022->queue_lock, flags);
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msg = pl022->cur_msg;
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pl022->cur_msg = NULL;
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pl022->cur_transfer = NULL;
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pl022->cur_chip = NULL;
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queue_work(pl022->workqueue, &pl022->pump_messages);
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spin_unlock_irqrestore(&pl022->queue_lock, flags);
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last_transfer = list_entry(msg->transfers.prev,
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/* Delay if requested before any change in chip select */
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if (last_transfer->delay_usecs)
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* FIXME: This runs in interrupt context.
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* Is this really smart?
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udelay(last_transfer->delay_usecs);
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* Drop chip select UNLESS cs_change is true or we are returning
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* a message with an error, or next message is for another chip
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if (!last_transfer->cs_change)
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curr_cs_control(SSP_CHIP_DESELECT);
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struct spi_message *next_msg;
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/* Holding of cs was hinted, but we need to make sure
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* the next message is for the same chip. Don't waste
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* time with the following tests unless this was hinted.
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* We cannot postpone this until pump_messages, because
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* after calling msg->complete (below) the driver that
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* sent the current message could be unloaded, which
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* could invalidate the cs_control() callback...
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/* get a pointer to the next message, if any */
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spin_lock_irqsave(&pl022->queue_lock, flags);
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if (list_empty(&pl022->queue))
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next_msg = list_entry(pl022->queue.next,
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struct spi_message, queue);
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spin_unlock_irqrestore(&pl022->queue_lock, flags);
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/* see if the next and current messages point
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if (next_msg && next_msg->spi != msg->spi)
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if (!next_msg || msg->state == STATE_ERROR)
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curr_cs_control(SSP_CHIP_DESELECT);
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msg->complete(msg->context);
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/* This message is completed, so let's turn off the clocks & power */
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pm_runtime_put(&pl022->adev->dev);
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* flush - flush the FIFO to reach a clean state
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* @pl022: SSP driver private data structure
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static int flush(struct pl022 *pl022)
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unsigned long limit = loops_per_jiffy << 1;
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dev_dbg(&pl022->adev->dev, "flush\n");
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while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
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readw(SSP_DR(pl022->virtbase));
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} while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
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pl022->exp_fifo_level = 0;
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* restore_state - Load configuration of current chip
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* @pl022: SSP driver private data structure
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static void restore_state(struct pl022 *pl022)
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struct chip_data *chip = pl022->cur_chip;
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if (pl022->vendor->extended_cr)
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writel(chip->cr0, SSP_CR0(pl022->virtbase));
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writew(chip->cr0, SSP_CR0(pl022->virtbase));
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writew(chip->cr1, SSP_CR1(pl022->virtbase));
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writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
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writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
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writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
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writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
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* Default SSP Register Values
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#define DEFAULT_SSP_REG_CR0 ( \
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GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
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GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
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GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
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GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
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GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
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/* ST versions have slightly different bit layout */
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#define DEFAULT_SSP_REG_CR0_ST ( \
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GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
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GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
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GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
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GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
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GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
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GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
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GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
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/* The PL023 version is slightly different again */
580
#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
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GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
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GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
583
GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
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GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
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#define DEFAULT_SSP_REG_CR1 ( \
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GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
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GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
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GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
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GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
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/* ST versions extend this register to use all 16 bits */
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#define DEFAULT_SSP_REG_CR1_ST ( \
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DEFAULT_SSP_REG_CR1 | \
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GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
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GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
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GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
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GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
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GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
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* The PL023 variant has further differences: no loopback mode, no microwire
606
* support, and a new clock feedback delay setting.
608
#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
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GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
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GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
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GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
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GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
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GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
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GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
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GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
616
GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
619
#define DEFAULT_SSP_REG_CPSR ( \
620
GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
623
#define DEFAULT_SSP_REG_DMACR (\
624
GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
625
GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
629
* load_ssp_default_config - Load default configuration for SSP
630
* @pl022: SSP driver private data structure
632
static void load_ssp_default_config(struct pl022 *pl022)
634
if (pl022->vendor->pl023) {
635
writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
636
writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
637
} else if (pl022->vendor->extended_cr) {
638
writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
639
writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
641
writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
642
writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
644
writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
645
writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
646
writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
647
writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
651
* This will write to TX and read from RX according to the parameters
654
static void readwriter(struct pl022 *pl022)
658
* The FIFO depth is different between primecell variants.
659
* I believe filling in too much in the FIFO might cause
660
* errons in 8bit wide transfers on ARM variants (just 8 words
661
* FIFO, means only 8x8 = 64 bits in FIFO) at least.
663
* To prevent this issue, the TX FIFO is only filled to the
664
* unused RX FIFO fill length, regardless of what the TX
665
* FIFO status flag indicates.
667
dev_dbg(&pl022->adev->dev,
668
"%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
669
__func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
671
/* Read as much as you can */
672
while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
673
&& (pl022->rx < pl022->rx_end)) {
674
switch (pl022->read) {
676
readw(SSP_DR(pl022->virtbase));
679
*(u8 *) (pl022->rx) =
680
readw(SSP_DR(pl022->virtbase)) & 0xFFU;
683
*(u16 *) (pl022->rx) =
684
(u16) readw(SSP_DR(pl022->virtbase));
687
*(u32 *) (pl022->rx) =
688
readl(SSP_DR(pl022->virtbase));
691
pl022->rx += (pl022->cur_chip->n_bytes);
692
pl022->exp_fifo_level--;
695
* Write as much as possible up to the RX FIFO size
697
while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
698
&& (pl022->tx < pl022->tx_end)) {
699
switch (pl022->write) {
701
writew(0x0, SSP_DR(pl022->virtbase));
704
writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
707
writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
710
writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
713
pl022->tx += (pl022->cur_chip->n_bytes);
714
pl022->exp_fifo_level++;
716
* This inner reader takes care of things appearing in the RX
717
* FIFO as we're transmitting. This will happen a lot since the
718
* clock starts running when you put things into the TX FIFO,
719
* and then things are continuously clocked into the RX FIFO.
721
while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
722
&& (pl022->rx < pl022->rx_end)) {
723
switch (pl022->read) {
725
readw(SSP_DR(pl022->virtbase));
728
*(u8 *) (pl022->rx) =
729
readw(SSP_DR(pl022->virtbase)) & 0xFFU;
732
*(u16 *) (pl022->rx) =
733
(u16) readw(SSP_DR(pl022->virtbase));
736
*(u32 *) (pl022->rx) =
737
readl(SSP_DR(pl022->virtbase));
740
pl022->rx += (pl022->cur_chip->n_bytes);
741
pl022->exp_fifo_level--;
745
* When we exit here the TX FIFO should be full and the RX FIFO
751
* next_transfer - Move to the Next transfer in the current spi message
752
* @pl022: SSP driver private data structure
754
* This function moves though the linked list of spi transfers in the
755
* current spi message and returns with the state of current spi
756
* message i.e whether its last transfer is done(STATE_DONE) or
757
* Next transfer is ready(STATE_RUNNING)
759
static void *next_transfer(struct pl022 *pl022)
761
struct spi_message *msg = pl022->cur_msg;
762
struct spi_transfer *trans = pl022->cur_transfer;
764
/* Move to next transfer */
765
if (trans->transfer_list.next != &msg->transfers) {
766
pl022->cur_transfer =
767
list_entry(trans->transfer_list.next,
768
struct spi_transfer, transfer_list);
769
return STATE_RUNNING;
775
* This DMA functionality is only compiled in if we have
776
* access to the generic DMA devices/DMA engine.
778
#ifdef CONFIG_DMA_ENGINE
779
static void unmap_free_dma_scatter(struct pl022 *pl022)
781
/* Unmap and free the SG tables */
782
dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
783
pl022->sgt_tx.nents, DMA_TO_DEVICE);
784
dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
785
pl022->sgt_rx.nents, DMA_FROM_DEVICE);
786
sg_free_table(&pl022->sgt_rx);
787
sg_free_table(&pl022->sgt_tx);
790
static void dma_callback(void *data)
792
struct pl022 *pl022 = data;
793
struct spi_message *msg = pl022->cur_msg;
795
BUG_ON(!pl022->sgt_rx.sgl);
799
* Optionally dump out buffers to inspect contents, this is
800
* good if you want to convince yourself that the loopback
801
* read/write contents are the same, when adopting to a new
805
struct scatterlist *sg;
808
dma_sync_sg_for_cpu(&pl022->adev->dev,
813
for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
814
dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
815
print_hex_dump(KERN_ERR, "SPI RX: ",
823
for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
824
dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
825
print_hex_dump(KERN_ERR, "SPI TX: ",
836
unmap_free_dma_scatter(pl022);
838
/* Update total bytes transferred */
839
msg->actual_length += pl022->cur_transfer->len;
840
if (pl022->cur_transfer->cs_change)
842
cs_control(SSP_CHIP_DESELECT);
844
/* Move to next transfer */
845
msg->state = next_transfer(pl022);
846
tasklet_schedule(&pl022->pump_transfers);
849
static void setup_dma_scatter(struct pl022 *pl022,
852
struct sg_table *sgtab)
854
struct scatterlist *sg;
855
int bytesleft = length;
861
for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
863
* If there are less bytes left than what fits
864
* in the current page (plus page alignment offset)
865
* we just feed in this, else we stuff in as much
868
if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
869
mapbytes = bytesleft;
871
mapbytes = PAGE_SIZE - offset_in_page(bufp);
872
sg_set_page(sg, virt_to_page(bufp),
873
mapbytes, offset_in_page(bufp));
875
bytesleft -= mapbytes;
876
dev_dbg(&pl022->adev->dev,
877
"set RX/TX target page @ %p, %d bytes, %d left\n",
878
bufp, mapbytes, bytesleft);
881
/* Map the dummy buffer on every page */
882
for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
883
if (bytesleft < PAGE_SIZE)
884
mapbytes = bytesleft;
886
mapbytes = PAGE_SIZE;
887
sg_set_page(sg, virt_to_page(pl022->dummypage),
889
bytesleft -= mapbytes;
890
dev_dbg(&pl022->adev->dev,
891
"set RX/TX to dummy page %d bytes, %d left\n",
892
mapbytes, bytesleft);
900
* configure_dma - configures the channels for the next transfer
901
* @pl022: SSP driver's private data structure
903
static int configure_dma(struct pl022 *pl022)
905
struct dma_slave_config rx_conf = {
906
.src_addr = SSP_DR(pl022->phybase),
907
.direction = DMA_FROM_DEVICE,
909
struct dma_slave_config tx_conf = {
910
.dst_addr = SSP_DR(pl022->phybase),
911
.direction = DMA_TO_DEVICE,
915
int rx_sglen, tx_sglen;
916
struct dma_chan *rxchan = pl022->dma_rx_channel;
917
struct dma_chan *txchan = pl022->dma_tx_channel;
918
struct dma_async_tx_descriptor *rxdesc;
919
struct dma_async_tx_descriptor *txdesc;
921
/* Check that the channels are available */
922
if (!rxchan || !txchan)
926
* If supplied, the DMA burstsize should equal the FIFO trigger level.
927
* Notice that the DMA engine uses one-to-one mapping. Since we can
928
* not trigger on 2 elements this needs explicit mapping rather than
931
switch (pl022->rx_lev_trig) {
932
case SSP_RX_1_OR_MORE_ELEM:
933
rx_conf.src_maxburst = 1;
935
case SSP_RX_4_OR_MORE_ELEM:
936
rx_conf.src_maxburst = 4;
938
case SSP_RX_8_OR_MORE_ELEM:
939
rx_conf.src_maxburst = 8;
941
case SSP_RX_16_OR_MORE_ELEM:
942
rx_conf.src_maxburst = 16;
944
case SSP_RX_32_OR_MORE_ELEM:
945
rx_conf.src_maxburst = 32;
948
rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
952
switch (pl022->tx_lev_trig) {
953
case SSP_TX_1_OR_MORE_EMPTY_LOC:
954
tx_conf.dst_maxburst = 1;
956
case SSP_TX_4_OR_MORE_EMPTY_LOC:
957
tx_conf.dst_maxburst = 4;
959
case SSP_TX_8_OR_MORE_EMPTY_LOC:
960
tx_conf.dst_maxburst = 8;
962
case SSP_TX_16_OR_MORE_EMPTY_LOC:
963
tx_conf.dst_maxburst = 16;
965
case SSP_TX_32_OR_MORE_EMPTY_LOC:
966
tx_conf.dst_maxburst = 32;
969
tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
973
switch (pl022->read) {
975
/* Use the same as for writing */
976
rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
979
rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
982
rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
985
rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
989
switch (pl022->write) {
991
/* Use the same as for reading */
992
tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
995
tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
998
tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1001
tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1005
/* SPI pecularity: we need to read and write the same width */
1006
if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1007
rx_conf.src_addr_width = tx_conf.dst_addr_width;
1008
if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1009
tx_conf.dst_addr_width = rx_conf.src_addr_width;
1010
BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1012
dmaengine_slave_config(rxchan, &rx_conf);
1013
dmaengine_slave_config(txchan, &tx_conf);
1015
/* Create sglists for the transfers */
1016
pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1017
dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1019
ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1021
goto err_alloc_rx_sg;
1023
ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1025
goto err_alloc_tx_sg;
1027
/* Fill in the scatterlists for the RX+TX buffers */
1028
setup_dma_scatter(pl022, pl022->rx,
1029
pl022->cur_transfer->len, &pl022->sgt_rx);
1030
setup_dma_scatter(pl022, pl022->tx,
1031
pl022->cur_transfer->len, &pl022->sgt_tx);
1033
/* Map DMA buffers */
1034
rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1035
pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1039
tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1040
pl022->sgt_tx.nents, DMA_TO_DEVICE);
1044
/* Send both scatterlists */
1045
rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1049
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1053
txdesc = txchan->device->device_prep_slave_sg(txchan,
1057
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1061
/* Put the callback on the RX transfer only, that should finish last */
1062
rxdesc->callback = dma_callback;
1063
rxdesc->callback_param = pl022;
1065
/* Submit and fire RX and TX with TX last so we're ready to read! */
1066
dmaengine_submit(rxdesc);
1067
dmaengine_submit(txdesc);
1068
dma_async_issue_pending(rxchan);
1069
dma_async_issue_pending(txchan);
1074
dmaengine_terminate_all(txchan);
1076
dmaengine_terminate_all(rxchan);
1077
dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1078
pl022->sgt_tx.nents, DMA_TO_DEVICE);
1080
dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1081
pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1083
sg_free_table(&pl022->sgt_tx);
1085
sg_free_table(&pl022->sgt_rx);
1090
static int __init pl022_dma_probe(struct pl022 *pl022)
1092
dma_cap_mask_t mask;
1094
/* Try to acquire a generic DMA engine slave channel */
1096
dma_cap_set(DMA_SLAVE, mask);
1098
* We need both RX and TX channels to do DMA, else do none
1101
pl022->dma_rx_channel = dma_request_channel(mask,
1102
pl022->master_info->dma_filter,
1103
pl022->master_info->dma_rx_param);
1104
if (!pl022->dma_rx_channel) {
1105
dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1109
pl022->dma_tx_channel = dma_request_channel(mask,
1110
pl022->master_info->dma_filter,
1111
pl022->master_info->dma_tx_param);
1112
if (!pl022->dma_tx_channel) {
1113
dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1117
pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1118
if (!pl022->dummypage) {
1119
dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
1120
goto err_no_dummypage;
1123
dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1124
dma_chan_name(pl022->dma_rx_channel),
1125
dma_chan_name(pl022->dma_tx_channel));
1130
dma_release_channel(pl022->dma_tx_channel);
1132
dma_release_channel(pl022->dma_rx_channel);
1133
pl022->dma_rx_channel = NULL;
1135
dev_err(&pl022->adev->dev,
1136
"Failed to work in dma mode, work without dma!\n");
1140
static void terminate_dma(struct pl022 *pl022)
1142
struct dma_chan *rxchan = pl022->dma_rx_channel;
1143
struct dma_chan *txchan = pl022->dma_tx_channel;
1145
dmaengine_terminate_all(rxchan);
1146
dmaengine_terminate_all(txchan);
1147
unmap_free_dma_scatter(pl022);
1150
static void pl022_dma_remove(struct pl022 *pl022)
1153
terminate_dma(pl022);
1154
if (pl022->dma_tx_channel)
1155
dma_release_channel(pl022->dma_tx_channel);
1156
if (pl022->dma_rx_channel)
1157
dma_release_channel(pl022->dma_rx_channel);
1158
kfree(pl022->dummypage);
1162
static inline int configure_dma(struct pl022 *pl022)
1167
static inline int pl022_dma_probe(struct pl022 *pl022)
1172
static inline void pl022_dma_remove(struct pl022 *pl022)
1178
* pl022_interrupt_handler - Interrupt handler for SSP controller
1180
* This function handles interrupts generated for an interrupt based transfer.
1181
* If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1182
* current message's state as STATE_ERROR and schedule the tasklet
1183
* pump_transfers which will do the postprocessing of the current message by
1184
* calling giveback(). Otherwise it reads data from RX FIFO till there is no
1185
* more data, and writes data in TX FIFO till it is not full. If we complete
1186
* the transfer we move to the next transfer and schedule the tasklet.
1188
static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1190
struct pl022 *pl022 = dev_id;
1191
struct spi_message *msg = pl022->cur_msg;
1195
if (unlikely(!msg)) {
1196
dev_err(&pl022->adev->dev,
1197
"bad message state in interrupt handler");
1202
/* Read the Interrupt Status Register */
1203
irq_status = readw(SSP_MIS(pl022->virtbase));
1205
if (unlikely(!irq_status))
1209
* This handles the FIFO interrupts, the timeout
1210
* interrupts are flatly ignored, they cannot be
1213
if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1215
* Overrun interrupt - bail out since our Data has been
1218
dev_err(&pl022->adev->dev, "FIFO overrun\n");
1219
if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1220
dev_err(&pl022->adev->dev,
1221
"RXFIFO is full\n");
1222
if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1223
dev_err(&pl022->adev->dev,
1224
"TXFIFO is full\n");
1227
* Disable and clear interrupts, disable SSP,
1228
* mark message with bad status so it can be
1231
writew(DISABLE_ALL_INTERRUPTS,
1232
SSP_IMSC(pl022->virtbase));
1233
writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1234
writew((readw(SSP_CR1(pl022->virtbase)) &
1235
(~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1236
msg->state = STATE_ERROR;
1238
/* Schedule message queue handler */
1239
tasklet_schedule(&pl022->pump_transfers);
1245
if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1247
/* Disable Transmit interrupt */
1248
writew(readw(SSP_IMSC(pl022->virtbase)) &
1249
(~SSP_IMSC_MASK_TXIM),
1250
SSP_IMSC(pl022->virtbase));
1254
* Since all transactions must write as much as shall be read,
1255
* we can conclude the entire transaction once RX is complete.
1256
* At this point, all TX will always be finished.
1258
if (pl022->rx >= pl022->rx_end) {
1259
writew(DISABLE_ALL_INTERRUPTS,
1260
SSP_IMSC(pl022->virtbase));
1261
writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1262
if (unlikely(pl022->rx > pl022->rx_end)) {
1263
dev_warn(&pl022->adev->dev, "read %u surplus "
1264
"bytes (did you request an odd "
1265
"number of bytes on a 16bit bus?)\n",
1266
(u32) (pl022->rx - pl022->rx_end));
1268
/* Update total bytes transferred */
1269
msg->actual_length += pl022->cur_transfer->len;
1270
if (pl022->cur_transfer->cs_change)
1272
cs_control(SSP_CHIP_DESELECT);
1273
/* Move to next transfer */
1274
msg->state = next_transfer(pl022);
1275
tasklet_schedule(&pl022->pump_transfers);
1283
* This sets up the pointers to memory for the next message to
1284
* send out on the SPI bus.
1286
static int set_up_next_transfer(struct pl022 *pl022,
1287
struct spi_transfer *transfer)
1291
/* Sanity check the message for this bus width */
1292
residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1293
if (unlikely(residue != 0)) {
1294
dev_err(&pl022->adev->dev,
1295
"message of %u bytes to transmit but the current "
1296
"chip bus has a data width of %u bytes!\n",
1297
pl022->cur_transfer->len,
1298
pl022->cur_chip->n_bytes);
1299
dev_err(&pl022->adev->dev, "skipping this message\n");
1302
pl022->tx = (void *)transfer->tx_buf;
1303
pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1304
pl022->rx = (void *)transfer->rx_buf;
1305
pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1307
pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1308
pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1313
* pump_transfers - Tasklet function which schedules next transfer
1314
* when running in interrupt or DMA transfer mode.
1315
* @data: SSP driver private data structure
1318
static void pump_transfers(unsigned long data)
1320
struct pl022 *pl022 = (struct pl022 *) data;
1321
struct spi_message *message = NULL;
1322
struct spi_transfer *transfer = NULL;
1323
struct spi_transfer *previous = NULL;
1325
/* Get current state information */
1326
message = pl022->cur_msg;
1327
transfer = pl022->cur_transfer;
1329
/* Handle for abort */
1330
if (message->state == STATE_ERROR) {
1331
message->status = -EIO;
1336
/* Handle end of message */
1337
if (message->state == STATE_DONE) {
1338
message->status = 0;
1343
/* Delay if requested at end of transfer before CS change */
1344
if (message->state == STATE_RUNNING) {
1345
previous = list_entry(transfer->transfer_list.prev,
1346
struct spi_transfer,
1348
if (previous->delay_usecs)
1350
* FIXME: This runs in interrupt context.
1351
* Is this really smart?
1353
udelay(previous->delay_usecs);
1355
/* Drop chip select only if cs_change is requested */
1356
if (previous->cs_change)
1357
pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1360
message->state = STATE_RUNNING;
1363
if (set_up_next_transfer(pl022, transfer)) {
1364
message->state = STATE_ERROR;
1365
message->status = -EIO;
1369
/* Flush the FIFOs and let's go! */
1372
if (pl022->cur_chip->enable_dma) {
1373
if (configure_dma(pl022)) {
1374
dev_dbg(&pl022->adev->dev,
1375
"configuration of DMA failed, fall back to interrupt mode\n");
1376
goto err_config_dma;
1382
writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1385
static void do_interrupt_dma_transfer(struct pl022 *pl022)
1387
u32 irqflags = ENABLE_ALL_INTERRUPTS;
1389
/* Enable target chip */
1390
pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1391
if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1393
pl022->cur_msg->state = STATE_ERROR;
1394
pl022->cur_msg->status = -EIO;
1398
/* If we're using DMA, set up DMA here */
1399
if (pl022->cur_chip->enable_dma) {
1400
/* Configure DMA transfer */
1401
if (configure_dma(pl022)) {
1402
dev_dbg(&pl022->adev->dev,
1403
"configuration of DMA failed, fall back to interrupt mode\n");
1404
goto err_config_dma;
1406
/* Disable interrupts in DMA mode, IRQ from DMA controller */
1407
irqflags = DISABLE_ALL_INTERRUPTS;
1410
/* Enable SSP, turn on interrupts */
1411
writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1412
SSP_CR1(pl022->virtbase));
1413
writew(irqflags, SSP_IMSC(pl022->virtbase));
1416
static void do_polling_transfer(struct pl022 *pl022)
1418
struct spi_message *message = NULL;
1419
struct spi_transfer *transfer = NULL;
1420
struct spi_transfer *previous = NULL;
1421
struct chip_data *chip;
1422
unsigned long time, timeout;
1424
chip = pl022->cur_chip;
1425
message = pl022->cur_msg;
1427
while (message->state != STATE_DONE) {
1428
/* Handle for abort */
1429
if (message->state == STATE_ERROR)
1431
transfer = pl022->cur_transfer;
1433
/* Delay if requested at end of transfer */
1434
if (message->state == STATE_RUNNING) {
1436
list_entry(transfer->transfer_list.prev,
1437
struct spi_transfer, transfer_list);
1438
if (previous->delay_usecs)
1439
udelay(previous->delay_usecs);
1440
if (previous->cs_change)
1441
pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1444
message->state = STATE_RUNNING;
1445
pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1448
/* Configuration Changing Per Transfer */
1449
if (set_up_next_transfer(pl022, transfer)) {
1451
message->state = STATE_ERROR;
1454
/* Flush FIFOs and enable SSP */
1456
writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1457
SSP_CR1(pl022->virtbase));
1459
dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1461
timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1462
while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1465
if (time_after(time, timeout)) {
1466
dev_warn(&pl022->adev->dev,
1467
"%s: timeout!\n", __func__);
1468
message->state = STATE_ERROR;
1474
/* Update total byte transferred */
1475
message->actual_length += pl022->cur_transfer->len;
1476
if (pl022->cur_transfer->cs_change)
1477
pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1478
/* Move to next transfer */
1479
message->state = next_transfer(pl022);
1482
/* Handle end of message */
1483
if (message->state == STATE_DONE)
1484
message->status = 0;
1486
message->status = -EIO;
1493
* pump_messages - Workqueue function which processes spi message queue
1494
* @data: pointer to private data of SSP driver
1496
* This function checks if there is any spi message in the queue that
1497
* needs processing and delegate control to appropriate function
1498
* do_polling_transfer()/do_interrupt_dma_transfer()
1499
* based on the kind of the transfer
1502
static void pump_messages(struct work_struct *work)
1504
struct pl022 *pl022 =
1505
container_of(work, struct pl022, pump_messages);
1506
unsigned long flags;
1508
/* Lock queue and check for queue work */
1509
spin_lock_irqsave(&pl022->queue_lock, flags);
1510
if (list_empty(&pl022->queue) || !pl022->running) {
1511
pl022->busy = false;
1512
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1515
/* Make sure we are not already running a message */
1516
if (pl022->cur_msg) {
1517
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1520
/* Extract head of queue */
1522
list_entry(pl022->queue.next, struct spi_message, queue);
1524
list_del_init(&pl022->cur_msg->queue);
1526
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1528
/* Initial message state */
1529
pl022->cur_msg->state = STATE_START;
1530
pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1531
struct spi_transfer, transfer_list);
1533
/* Setup the SPI using the per chip configuration */
1534
pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1536
* We enable the core voltage and clocks here, then the clocks
1537
* and core will be disabled when giveback() is called in each method
1538
* (poll/interrupt/DMA)
1540
pm_runtime_get_sync(&pl022->adev->dev);
1541
restore_state(pl022);
1544
if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1545
do_polling_transfer(pl022);
1547
do_interrupt_dma_transfer(pl022);
1550
static int __init init_queue(struct pl022 *pl022)
1552
INIT_LIST_HEAD(&pl022->queue);
1553
spin_lock_init(&pl022->queue_lock);
1555
pl022->running = false;
1556
pl022->busy = false;
1558
tasklet_init(&pl022->pump_transfers, pump_transfers,
1559
(unsigned long)pl022);
1561
INIT_WORK(&pl022->pump_messages, pump_messages);
1562
pl022->workqueue = create_singlethread_workqueue(
1563
dev_name(pl022->master->dev.parent));
1564
if (pl022->workqueue == NULL)
1570
static int start_queue(struct pl022 *pl022)
1572
unsigned long flags;
1574
spin_lock_irqsave(&pl022->queue_lock, flags);
1576
if (pl022->running || pl022->busy) {
1577
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1581
pl022->running = true;
1582
pl022->cur_msg = NULL;
1583
pl022->cur_transfer = NULL;
1584
pl022->cur_chip = NULL;
1585
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1587
queue_work(pl022->workqueue, &pl022->pump_messages);
1592
static int stop_queue(struct pl022 *pl022)
1594
unsigned long flags;
1595
unsigned limit = 500;
1598
spin_lock_irqsave(&pl022->queue_lock, flags);
1600
/* This is a bit lame, but is optimized for the common execution path.
1601
* A wait_queue on the pl022->busy could be used, but then the common
1602
* execution path (pump_messages) would be required to call wake_up or
1603
* friends on every SPI message. Do this instead */
1604
while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) {
1605
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1607
spin_lock_irqsave(&pl022->queue_lock, flags);
1610
if (!list_empty(&pl022->queue) || pl022->busy)
1613
pl022->running = false;
1615
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1620
static int destroy_queue(struct pl022 *pl022)
1624
status = stop_queue(pl022);
1625
/* we are unloading the module or failing to load (only two calls
1626
* to this routine), and neither call can handle a return value.
1627
* However, destroy_workqueue calls flush_workqueue, and that will
1628
* block until all work is done. If the reason that stop_queue
1629
* timed out is that the work will never finish, then it does no
1630
* good to call destroy_workqueue, so return anyway. */
1634
destroy_workqueue(pl022->workqueue);
1639
static int verify_controller_parameters(struct pl022 *pl022,
1640
struct pl022_config_chip const *chip_info)
1642
if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1643
|| (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1644
dev_err(&pl022->adev->dev,
1645
"interface is configured incorrectly\n");
1648
if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1649
(!pl022->vendor->unidir)) {
1650
dev_err(&pl022->adev->dev,
1651
"unidirectional mode not supported in this "
1652
"hardware version\n");
1655
if ((chip_info->hierarchy != SSP_MASTER)
1656
&& (chip_info->hierarchy != SSP_SLAVE)) {
1657
dev_err(&pl022->adev->dev,
1658
"hierarchy is configured incorrectly\n");
1661
if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1662
&& (chip_info->com_mode != DMA_TRANSFER)
1663
&& (chip_info->com_mode != POLLING_TRANSFER)) {
1664
dev_err(&pl022->adev->dev,
1665
"Communication mode is configured incorrectly\n");
1668
switch (chip_info->rx_lev_trig) {
1669
case SSP_RX_1_OR_MORE_ELEM:
1670
case SSP_RX_4_OR_MORE_ELEM:
1671
case SSP_RX_8_OR_MORE_ELEM:
1672
/* These are always OK, all variants can handle this */
1674
case SSP_RX_16_OR_MORE_ELEM:
1675
if (pl022->vendor->fifodepth < 16) {
1676
dev_err(&pl022->adev->dev,
1677
"RX FIFO Trigger Level is configured incorrectly\n");
1681
case SSP_RX_32_OR_MORE_ELEM:
1682
if (pl022->vendor->fifodepth < 32) {
1683
dev_err(&pl022->adev->dev,
1684
"RX FIFO Trigger Level is configured incorrectly\n");
1689
dev_err(&pl022->adev->dev,
1690
"RX FIFO Trigger Level is configured incorrectly\n");
1694
switch (chip_info->tx_lev_trig) {
1695
case SSP_TX_1_OR_MORE_EMPTY_LOC:
1696
case SSP_TX_4_OR_MORE_EMPTY_LOC:
1697
case SSP_TX_8_OR_MORE_EMPTY_LOC:
1698
/* These are always OK, all variants can handle this */
1700
case SSP_TX_16_OR_MORE_EMPTY_LOC:
1701
if (pl022->vendor->fifodepth < 16) {
1702
dev_err(&pl022->adev->dev,
1703
"TX FIFO Trigger Level is configured incorrectly\n");
1707
case SSP_TX_32_OR_MORE_EMPTY_LOC:
1708
if (pl022->vendor->fifodepth < 32) {
1709
dev_err(&pl022->adev->dev,
1710
"TX FIFO Trigger Level is configured incorrectly\n");
1715
dev_err(&pl022->adev->dev,
1716
"TX FIFO Trigger Level is configured incorrectly\n");
1720
if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1721
if ((chip_info->ctrl_len < SSP_BITS_4)
1722
|| (chip_info->ctrl_len > SSP_BITS_32)) {
1723
dev_err(&pl022->adev->dev,
1724
"CTRL LEN is configured incorrectly\n");
1727
if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1728
&& (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1729
dev_err(&pl022->adev->dev,
1730
"Wait State is configured incorrectly\n");
1733
/* Half duplex is only available in the ST Micro version */
1734
if (pl022->vendor->extended_cr) {
1735
if ((chip_info->duplex !=
1736
SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1737
&& (chip_info->duplex !=
1738
SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1739
dev_err(&pl022->adev->dev,
1740
"Microwire duplex mode is configured incorrectly\n");
1744
if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1745
dev_err(&pl022->adev->dev,
1746
"Microwire half duplex mode requested,"
1747
" but this is only available in the"
1748
" ST version of PL022\n");
1756
* pl022_transfer - transfer function registered to SPI master framework
1757
* @spi: spi device which is requesting transfer
1758
* @msg: spi message which is to handled is queued to driver queue
1760
* This function is registered to the SPI framework for this SPI master
1761
* controller. It will queue the spi_message in the queue of driver if
1762
* the queue is not stopped and return.
1764
static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1766
struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1767
unsigned long flags;
1769
spin_lock_irqsave(&pl022->queue_lock, flags);
1771
if (!pl022->running) {
1772
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1775
msg->actual_length = 0;
1776
msg->status = -EINPROGRESS;
1777
msg->state = STATE_START;
1779
list_add_tail(&msg->queue, &pl022->queue);
1780
if (pl022->running && !pl022->busy)
1781
queue_work(pl022->workqueue, &pl022->pump_messages);
1783
spin_unlock_irqrestore(&pl022->queue_lock, flags);
1787
static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1789
return rate / (cpsdvsr * (1 + scr));
1792
static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1793
ssp_clock_params * clk_freq)
1795
/* Lets calculate the frequency parameters */
1796
u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1797
u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1798
best_scr = 0, tmp, found = 0;
1800
rate = clk_get_rate(pl022->clk);
1801
/* cpsdvscr = 2 & scr 0 */
1802
max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1803
/* cpsdvsr = 254 & scr = 255 */
1804
min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1806
if (!((freq <= max_tclk) && (freq >= min_tclk))) {
1807
dev_err(&pl022->adev->dev,
1808
"controller data is incorrect: out of range frequency");
1813
* best_freq will give closest possible available rate (<= requested
1814
* freq) for all values of scr & cpsdvsr.
1816
while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1817
while (scr <= SCR_MAX) {
1818
tmp = spi_rate(rate, cpsdvsr, scr);
1823
* If found exact value, update and break.
1824
* If found more closer value, update and continue.
1826
else if ((tmp == freq) || (tmp > best_freq)) {
1828
best_cpsdvsr = cpsdvsr;
1840
clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1841
clk_freq->scr = (u8) (best_scr & 0xFF);
1842
dev_dbg(&pl022->adev->dev,
1843
"SSP Target Frequency is: %u, Effective Frequency is %u\n",
1845
dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1846
clk_freq->cpsdvsr, clk_freq->scr);
1852
* A piece of default chip info unless the platform
1855
static const struct pl022_config_chip pl022_default_chip_info = {
1856
.com_mode = POLLING_TRANSFER,
1857
.iface = SSP_INTERFACE_MOTOROLA_SPI,
1858
.hierarchy = SSP_SLAVE,
1859
.slave_tx_disable = DO_NOT_DRIVE_TX,
1860
.rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1861
.tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1862
.ctrl_len = SSP_BITS_8,
1863
.wait_state = SSP_MWIRE_WAIT_ZERO,
1864
.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1865
.cs_control = null_cs_control,
1869
* pl022_setup - setup function registered to SPI master framework
1870
* @spi: spi device which is requesting setup
1872
* This function is registered to the SPI framework for this SPI master
1873
* controller. If it is the first time when setup is called by this device,
1874
* this function will initialize the runtime state for this chip and save
1875
* the same in the device structure. Else it will update the runtime info
1876
* with the updated chip info. Nothing is really being written to the
1877
* controller hardware here, that is not done until the actual transfer
1880
static int pl022_setup(struct spi_device *spi)
1882
struct pl022_config_chip const *chip_info;
1883
struct chip_data *chip;
1884
struct ssp_clock_params clk_freq = {0, };
1886
struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1887
unsigned int bits = spi->bits_per_word;
1890
if (!spi->max_speed_hz)
1893
/* Get controller_state if one is supplied */
1894
chip = spi_get_ctldata(spi);
1897
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1900
"cannot allocate controller state\n");
1904
"allocated memory for controller's runtime state\n");
1907
/* Get controller data if one is supplied */
1908
chip_info = spi->controller_data;
1910
if (chip_info == NULL) {
1911
chip_info = &pl022_default_chip_info;
1912
/* spi_board_info.controller_data not is supplied */
1914
"using default controller_data settings\n");
1917
"using user supplied controller_data settings\n");
1920
* We can override with custom divisors, else we use the board
1923
if ((0 == chip_info->clk_freq.cpsdvsr)
1924
&& (0 == chip_info->clk_freq.scr)) {
1925
status = calculate_effective_freq(pl022,
1929
goto err_config_params;
1931
memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1932
if ((clk_freq.cpsdvsr % 2) != 0)
1934
clk_freq.cpsdvsr - 1;
1936
if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1937
|| (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1940
"cpsdvsr is configured incorrectly\n");
1941
goto err_config_params;
1944
status = verify_controller_parameters(pl022, chip_info);
1946
dev_err(&spi->dev, "controller data is incorrect");
1947
goto err_config_params;
1950
pl022->rx_lev_trig = chip_info->rx_lev_trig;
1951
pl022->tx_lev_trig = chip_info->tx_lev_trig;
1953
/* Now set controller state based on controller data */
1954
chip->xfer_type = chip_info->com_mode;
1955
if (!chip_info->cs_control) {
1956
chip->cs_control = null_cs_control;
1958
"chip select function is NULL for this chip\n");
1960
chip->cs_control = chip_info->cs_control;
1963
/* PL022 doesn't support less than 4-bits */
1965
goto err_config_params;
1966
} else if (bits <= 8) {
1967
dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1969
chip->read = READING_U8;
1970
chip->write = WRITING_U8;
1971
} else if (bits <= 16) {
1972
dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1974
chip->read = READING_U16;
1975
chip->write = WRITING_U16;
1977
if (pl022->vendor->max_bpw >= 32) {
1978
dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1980
chip->read = READING_U32;
1981
chip->write = WRITING_U32;
1984
"illegal data size for this controller!\n");
1986
"a standard pl022 can only handle "
1987
"1 <= n <= 16 bit words\n");
1989
goto err_config_params;
1993
/* Now Initialize all register settings required for this chip */
1998
if ((chip_info->com_mode == DMA_TRANSFER)
1999
&& ((pl022->master_info)->enable_dma)) {
2000
chip->enable_dma = true;
2001
dev_dbg(&spi->dev, "DMA mode set in controller state\n");
2002
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2003
SSP_DMACR_MASK_RXDMAE, 0);
2004
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2005
SSP_DMACR_MASK_TXDMAE, 1);
2007
chip->enable_dma = false;
2008
dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
2009
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2010
SSP_DMACR_MASK_RXDMAE, 0);
2011
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2012
SSP_DMACR_MASK_TXDMAE, 1);
2015
chip->cpsr = clk_freq.cpsdvsr;
2017
/* Special setup for the ST micro extended control registers */
2018
if (pl022->vendor->extended_cr) {
2021
if (pl022->vendor->pl023) {
2022
/* These bits are only in the PL023 */
2023
SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
2024
SSP_CR1_MASK_FBCLKDEL_ST, 13);
2026
/* These bits are in the PL022 but not PL023 */
2027
SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
2028
SSP_CR0_MASK_HALFDUP_ST, 5);
2029
SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
2030
SSP_CR0_MASK_CSS_ST, 16);
2031
SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2032
SSP_CR0_MASK_FRF_ST, 21);
2033
SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2034
SSP_CR1_MASK_MWAIT_ST, 6);
2036
SSP_WRITE_BITS(chip->cr0, bits - 1,
2037
SSP_CR0_MASK_DSS_ST, 0);
2039
if (spi->mode & SPI_LSB_FIRST) {
2046
SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2047
SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2048
SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2049
SSP_CR1_MASK_RXIFLSEL_ST, 7);
2050
SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2051
SSP_CR1_MASK_TXIFLSEL_ST, 10);
2053
SSP_WRITE_BITS(chip->cr0, bits - 1,
2054
SSP_CR0_MASK_DSS, 0);
2055
SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2056
SSP_CR0_MASK_FRF, 4);
2059
/* Stuff that is common for all versions */
2060
if (spi->mode & SPI_CPOL)
2061
tmp = SSP_CLK_POL_IDLE_HIGH;
2063
tmp = SSP_CLK_POL_IDLE_LOW;
2064
SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2066
if (spi->mode & SPI_CPHA)
2067
tmp = SSP_CLK_SECOND_EDGE;
2069
tmp = SSP_CLK_FIRST_EDGE;
2070
SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2072
SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2073
/* Loopback is available on all versions except PL023 */
2074
if (pl022->vendor->loopback) {
2075
if (spi->mode & SPI_LOOP)
2076
tmp = LOOPBACK_ENABLED;
2078
tmp = LOOPBACK_DISABLED;
2079
SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2081
SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2082
SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2083
SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2086
/* Save controller_state */
2087
spi_set_ctldata(spi, chip);
2090
spi_set_ctldata(spi, NULL);
2096
* pl022_cleanup - cleanup function registered to SPI master framework
2097
* @spi: spi device which is requesting cleanup
2099
* This function is registered to the SPI framework for this SPI master
2100
* controller. It will free the runtime state of chip.
2102
static void pl022_cleanup(struct spi_device *spi)
2104
struct chip_data *chip = spi_get_ctldata(spi);
2106
spi_set_ctldata(spi, NULL);
2110
static int __devinit
2111
pl022_probe(struct amba_device *adev, const struct amba_id *id)
2113
struct device *dev = &adev->dev;
2114
struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2115
struct spi_master *master;
2116
struct pl022 *pl022 = NULL; /*Data for this driver */
2119
dev_info(&adev->dev,
2120
"ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2121
if (platform_info == NULL) {
2122
dev_err(&adev->dev, "probe - no platform data supplied\n");
2127
/* Allocate master with space for data */
2128
master = spi_alloc_master(dev, sizeof(struct pl022));
2129
if (master == NULL) {
2130
dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2135
pl022 = spi_master_get_devdata(master);
2136
pl022->master = master;
2137
pl022->master_info = platform_info;
2139
pl022->vendor = id->data;
2142
* Bus Number Which has been Assigned to this SSP controller
2145
master->bus_num = platform_info->bus_id;
2146
master->num_chipselect = platform_info->num_chipselect;
2147
master->cleanup = pl022_cleanup;
2148
master->setup = pl022_setup;
2149
master->transfer = pl022_transfer;
2152
* Supports mode 0-3, loopback, and active low CS. Transfers are
2153
* always MS bit first on the original pl022.
2155
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2156
if (pl022->vendor->extended_cr)
2157
master->mode_bits |= SPI_LSB_FIRST;
2159
dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2161
status = amba_request_regions(adev, NULL);
2163
goto err_no_ioregion;
2165
pl022->phybase = adev->res.start;
2166
pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2167
if (pl022->virtbase == NULL) {
2169
goto err_no_ioremap;
2171
printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2172
adev->res.start, pl022->virtbase);
2174
pl022->clk = clk_get(&adev->dev, NULL);
2175
if (IS_ERR(pl022->clk)) {
2176
status = PTR_ERR(pl022->clk);
2177
dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2181
status = clk_prepare(pl022->clk);
2183
dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2187
status = clk_enable(pl022->clk);
2189
dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2194
writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2195
SSP_CR1(pl022->virtbase));
2196
load_ssp_default_config(pl022);
2198
status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2201
dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2205
/* Get DMA channels */
2206
if (platform_info->enable_dma) {
2207
status = pl022_dma_probe(pl022);
2209
platform_info->enable_dma = 0;
2212
/* Initialize and start queue */
2213
status = init_queue(pl022);
2215
dev_err(&adev->dev, "probe - problem initializing queue\n");
2216
goto err_init_queue;
2218
status = start_queue(pl022);
2220
dev_err(&adev->dev, "probe - problem starting queue\n");
2221
goto err_start_queue;
2223
/* Register with the SPI framework */
2224
amba_set_drvdata(adev, pl022);
2225
status = spi_register_master(master);
2228
"probe - problem registering spi master\n");
2229
goto err_spi_register;
2231
dev_dbg(dev, "probe succeeded\n");
2233
/* let runtime pm put suspend */
2234
pm_runtime_put(dev);
2240
destroy_queue(pl022);
2241
if (platform_info->enable_dma)
2242
pl022_dma_remove(pl022);
2244
free_irq(adev->irq[0], pl022);
2246
clk_disable(pl022->clk);
2248
clk_unprepare(pl022->clk);
2250
clk_put(pl022->clk);
2252
iounmap(pl022->virtbase);
2254
amba_release_regions(adev);
2256
spi_master_put(master);
2262
static int __devexit
2263
pl022_remove(struct amba_device *adev)
2265
struct pl022 *pl022 = amba_get_drvdata(adev);
2271
* undo pm_runtime_put() in probe. I assume that we're not
2272
* accessing the primecell here.
2274
pm_runtime_get_noresume(&adev->dev);
2276
/* Remove the queue */
2277
if (destroy_queue(pl022) != 0)
2278
dev_err(&adev->dev, "queue remove failed\n");
2279
load_ssp_default_config(pl022);
2280
if (pl022->master_info->enable_dma)
2281
pl022_dma_remove(pl022);
2283
free_irq(adev->irq[0], pl022);
2284
clk_disable(pl022->clk);
2285
clk_unprepare(pl022->clk);
2286
clk_put(pl022->clk);
2287
iounmap(pl022->virtbase);
2288
amba_release_regions(adev);
2289
tasklet_disable(&pl022->pump_transfers);
2290
spi_unregister_master(pl022->master);
2291
spi_master_put(pl022->master);
2292
amba_set_drvdata(adev, NULL);
2296
#ifdef CONFIG_SUSPEND
2297
static int pl022_suspend(struct device *dev)
2299
struct pl022 *pl022 = dev_get_drvdata(dev);
2302
status = stop_queue(pl022);
2304
dev_warn(dev, "suspend cannot stop queue\n");
2308
amba_vcore_enable(pl022->adev);
2309
amba_pclk_enable(pl022->adev);
2310
load_ssp_default_config(pl022);
2311
amba_pclk_disable(pl022->adev);
2312
amba_vcore_disable(pl022->adev);
2313
dev_dbg(dev, "suspended\n");
2317
static int pl022_resume(struct device *dev)
2319
struct pl022 *pl022 = dev_get_drvdata(dev);
2322
/* Start the queue running */
2323
status = start_queue(pl022);
2325
dev_err(dev, "problem starting queue (%d)\n", status);
2327
dev_dbg(dev, "resumed\n");
2331
#endif /* CONFIG_PM */
2333
#ifdef CONFIG_PM_RUNTIME
2334
static int pl022_runtime_suspend(struct device *dev)
2336
struct pl022 *pl022 = dev_get_drvdata(dev);
2338
clk_disable(pl022->clk);
2339
amba_vcore_disable(pl022->adev);
2344
static int pl022_runtime_resume(struct device *dev)
2346
struct pl022 *pl022 = dev_get_drvdata(dev);
2348
amba_vcore_enable(pl022->adev);
2349
clk_enable(pl022->clk);
2355
static const struct dev_pm_ops pl022_dev_pm_ops = {
2356
SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2357
SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2360
static struct vendor_data vendor_arm = {
2364
.extended_cr = false,
2369
static struct vendor_data vendor_st = {
2373
.extended_cr = true,
2378
static struct vendor_data vendor_st_pl023 = {
2382
.extended_cr = true,
2387
static struct vendor_data vendor_db5500_pl023 = {
2391
.extended_cr = true,
2396
static struct amba_id pl022_ids[] = {
2399
* ARM PL022 variant, this has a 16bit wide
2400
* and 8 locations deep TX/RX FIFO
2404
.data = &vendor_arm,
2408
* ST Micro derivative, this has 32bit wide
2409
* and 32 locations deep TX/RX FIFO
2417
* ST-Ericsson derivative "PL023" (this is not
2418
* an official ARM number), this is a PL022 SSP block
2419
* stripped to SPI mode only, it has 32bit wide
2420
* and 32 locations deep TX/RX FIFO but no extended
2425
.data = &vendor_st_pl023,
2430
.data = &vendor_db5500_pl023,
2435
static struct amba_driver pl022_driver = {
2437
.name = "ssp-pl022",
2438
.pm = &pl022_dev_pm_ops,
2440
.id_table = pl022_ids,
2441
.probe = pl022_probe,
2442
.remove = __devexit_p(pl022_remove),
2445
static int __init pl022_init(void)
2447
return amba_driver_register(&pl022_driver);
2449
subsys_initcall(pl022_init);
2451
static void __exit pl022_exit(void)
2453
amba_driver_unregister(&pl022_driver);
2455
module_exit(pl022_exit);
2457
MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2458
MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2459
MODULE_LICENSE("GPL");