2
* core.c - DesignWare USB3 DRD Controller Core file
4
* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6
* Authors: Felipe Balbi <balbi@ti.com>,
7
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9
* Redistribution and use in source and binary forms, with or without
10
* modification, are permitted provided that the following conditions
12
* 1. Redistributions of source code must retain the above copyright
13
* notice, this list of conditions, and the following disclaimer,
14
* without modification.
15
* 2. Redistributions in binary form must reproduce the above copyright
16
* notice, this list of conditions and the following disclaimer in the
17
* documentation and/or other materials provided with the distribution.
18
* 3. The names of the above-listed copyright holders may not be used
19
* to endorse or promote products derived from this software without
20
* specific prior written permission.
22
* ALTERNATIVELY, this software may be distributed under the terms of the
23
* GNU General Public License ("GPL") version 2, as published by the Free
24
* Software Foundation.
26
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
#include <linux/module.h>
40
#include <linux/kernel.h>
41
#include <linux/slab.h>
42
#include <linux/spinlock.h>
43
#include <linux/platform_device.h>
44
#include <linux/pm_runtime.h>
45
#include <linux/interrupt.h>
46
#include <linux/ioport.h>
48
#include <linux/list.h>
49
#include <linux/delay.h>
50
#include <linux/dma-mapping.h>
52
#include <linux/usb/ch9.h>
53
#include <linux/usb/gadget.h>
54
#include <linux/module.h>
63
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
64
* @dwc: pointer to our context structure
66
static void dwc3_core_soft_reset(struct dwc3 *dwc)
70
/* Before Resetting PHY, put Core in Reset */
71
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
72
reg |= DWC3_GCTL_CORESOFTRESET;
73
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
75
/* Assert USB3 PHY reset */
76
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
77
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
78
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
80
/* Assert USB2 PHY reset */
81
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
82
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
83
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
87
/* Clear USB3 PHY reset */
88
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
89
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
90
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
92
/* Clear USB2 PHY reset */
93
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
94
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
95
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
97
/* After PHYs are stable we can take Core out of reset state */
98
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
99
reg &= ~DWC3_GCTL_CORESOFTRESET;
100
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
104
* dwc3_free_one_event_buffer - Frees one event buffer
105
* @dwc: Pointer to our controller context structure
106
* @evt: Pointer to event buffer to be freed
108
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
109
struct dwc3_event_buffer *evt)
111
dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
116
* dwc3_alloc_one_event_buffer - Allocated one event buffer structure
117
* @dwc: Pointer to our controller context structure
118
* @length: size of the event buffer
120
* Returns a pointer to the allocated event buffer structure on succes
121
* otherwise ERR_PTR(errno).
123
static struct dwc3_event_buffer *__devinit
124
dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
126
struct dwc3_event_buffer *evt;
128
evt = kzalloc(sizeof(*evt), GFP_KERNEL);
130
return ERR_PTR(-ENOMEM);
133
evt->length = length;
134
evt->buf = dma_alloc_coherent(dwc->dev, length,
135
&evt->dma, GFP_KERNEL);
138
return ERR_PTR(-ENOMEM);
145
* dwc3_free_event_buffers - frees all allocated event buffers
146
* @dwc: Pointer to our controller context structure
148
static void dwc3_free_event_buffers(struct dwc3 *dwc)
150
struct dwc3_event_buffer *evt;
153
for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
154
evt = dwc->ev_buffs[i];
156
dwc3_free_one_event_buffer(dwc, evt);
157
dwc->ev_buffs[i] = NULL;
163
* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
164
* @dwc: Pointer to out controller context structure
165
* @num: number of event buffers to allocate
166
* @length: size of event buffer
168
* Returns 0 on success otherwise negative errno. In error the case, dwc
169
* may contain some buffers allocated but not all which were requested.
171
static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num,
176
for (i = 0; i < num; i++) {
177
struct dwc3_event_buffer *evt;
179
evt = dwc3_alloc_one_event_buffer(dwc, length);
181
dev_err(dwc->dev, "can't allocate event buffer\n");
184
dwc->ev_buffs[i] = evt;
191
* dwc3_event_buffers_setup - setup our allocated event buffers
192
* @dwc: Pointer to out controller context structure
194
* Returns 0 on success otherwise negative errno.
196
static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
198
struct dwc3_event_buffer *evt;
201
for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
202
evt = dwc->ev_buffs[n];
203
dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
204
evt->buf, (unsigned long long) evt->dma,
207
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
208
lower_32_bits(evt->dma));
209
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
210
upper_32_bits(evt->dma));
211
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
212
evt->length & 0xffff);
213
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
219
static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
221
struct dwc3_event_buffer *evt;
224
for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
225
evt = dwc->ev_buffs[n];
226
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
227
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
228
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
229
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
233
static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
235
struct dwc3_hwparams *parms = &dwc->hwparams;
237
parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
238
parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
239
parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
240
parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
241
parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
242
parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
243
parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
244
parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
245
parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
249
* dwc3_core_init - Low-level initialization of DWC3 Core
250
* @dwc: Pointer to our controller context structure
252
* Returns 0 on success otherwise negative errno.
254
static int __devinit dwc3_core_init(struct dwc3 *dwc)
256
unsigned long timeout;
260
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
261
/* This should read as U3 followed by revision number */
262
if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
263
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
269
dwc3_core_soft_reset(dwc);
271
/* issue device SoftReset too */
272
timeout = jiffies + msecs_to_jiffies(500);
273
dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
275
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
276
if (!(reg & DWC3_DCTL_CSFTRST))
279
if (time_after(jiffies, timeout)) {
280
dev_err(dwc->dev, "Reset Timed Out\n");
288
ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,
289
DWC3_EVENT_BUFFERS_SIZE);
291
dev_err(dwc->dev, "failed to allocate event buffers\n");
296
ret = dwc3_event_buffers_setup(dwc);
298
dev_err(dwc->dev, "failed to setup event buffers\n");
302
dwc3_cache_hwparams(dwc);
307
dwc3_free_event_buffers(dwc);
313
static void dwc3_core_exit(struct dwc3 *dwc)
315
dwc3_event_buffers_cleanup(dwc);
316
dwc3_free_event_buffers(dwc);
319
#define DWC3_ALIGN_MASK (16 - 1)
321
static int __devinit dwc3_probe(struct platform_device *pdev)
323
const struct platform_device_id *id = platform_get_device_id(pdev);
324
struct resource *res;
327
unsigned int features = id->driver_data;
332
mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
334
dev_err(&pdev->dev, "not enough memory\n");
337
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
340
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342
dev_err(&pdev->dev, "missing resource\n");
346
res = request_mem_region(res->start, resource_size(res),
347
dev_name(&pdev->dev));
349
dev_err(&pdev->dev, "can't request mem region\n");
353
regs = ioremap(res->start, resource_size(res));
355
dev_err(&pdev->dev, "ioremap failed\n");
359
irq = platform_get_irq(pdev, 0);
361
dev_err(&pdev->dev, "missing IRQ\n");
365
spin_lock_init(&dwc->lock);
366
platform_set_drvdata(pdev, dwc);
369
dwc->regs_size = resource_size(res);
370
dwc->dev = &pdev->dev;
373
pm_runtime_enable(&pdev->dev);
374
pm_runtime_get_sync(&pdev->dev);
375
pm_runtime_forbid(&pdev->dev);
377
ret = dwc3_core_init(dwc);
379
dev_err(&pdev->dev, "failed to initialize core\n");
383
if (features & DWC3_HAS_PERIPHERAL) {
384
ret = dwc3_gadget_init(dwc);
386
dev_err(&pdev->dev, "failed to initialized gadget\n");
391
ret = dwc3_debugfs_init(dwc);
393
dev_err(&pdev->dev, "failed to initialize debugfs\n");
397
pm_runtime_allow(&pdev->dev);
402
if (features & DWC3_HAS_PERIPHERAL)
403
dwc3_gadget_exit(dwc);
412
release_mem_region(res->start, resource_size(res));
421
static int __devexit dwc3_remove(struct platform_device *pdev)
423
const struct platform_device_id *id = platform_get_device_id(pdev);
424
struct dwc3 *dwc = platform_get_drvdata(pdev);
425
struct resource *res;
426
unsigned int features = id->driver_data;
428
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430
pm_runtime_put(&pdev->dev);
431
pm_runtime_disable(&pdev->dev);
433
dwc3_debugfs_exit(dwc);
435
if (features & DWC3_HAS_PERIPHERAL)
436
dwc3_gadget_exit(dwc);
439
release_mem_region(res->start, resource_size(res));
446
static const struct platform_device_id dwc3_id_table[] __devinitconst = {
449
.driver_data = (DWC3_HAS_PERIPHERAL
455
.driver_data = DWC3_HAS_PERIPHERAL,
457
{ }, /* Terminating Entry */
459
MODULE_DEVICE_TABLE(platform, dwc3_id_table);
461
static struct platform_driver dwc3_driver = {
463
.remove = __devexit_p(dwc3_remove),
467
.id_table = dwc3_id_table,
470
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
471
MODULE_LICENSE("Dual BSD/GPL");
472
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
474
static int __devinit dwc3_init(void)
476
return platform_driver_register(&dwc3_driver);
478
module_init(dwc3_init);
480
static void __exit dwc3_exit(void)
482
platform_driver_unregister(&dwc3_driver);
484
module_exit(dwc3_exit);