2
* Libata based driver for Apple "macio" family of PATA controllers
4
* Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
5
* <benh@kernel.crashing.org>
7
* Some bits and pieces from drivers/ide/ppc/pmac.c
14
#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
17
#include <linux/blkdev.h>
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#include <linux/ata.h>
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#include <linux/libata.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <linux/scatterlist.h>
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#include <linux/gfp.h>
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#include <scsi/scsi.h>
27
#include <scsi/scsi_host.h>
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#include <scsi/scsi_device.h>
30
#include <asm/macio.h>
32
#include <asm/dbdma.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#include <asm/mediabay.h>
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#define dev_dbgdma(dev, format, arg...) \
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dev_printk(KERN_DEBUG , dev , format , ## arg)
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#define dev_dbgdma(dev, format, arg...) \
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({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
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#define DRV_NAME "pata_macio"
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#define DRV_VERSION "0.9"
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/* Models of macio ATA controller */
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controller_ohare, /* OHare based */
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controller_heathrow, /* Heathrow/Paddington */
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controller_kl_ata3, /* KeyLargo ATA-3 */
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controller_kl_ata4, /* KeyLargo ATA-4 */
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controller_un_ata6, /* UniNorth2 ATA-6 */
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controller_k2_ata6, /* K2 ATA-6 */
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controller_sh_ata6, /* Shasta ATA-6 */
60
static const char* macio_ata_names[] = {
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"OHare ATA", /* OHare based */
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"Heathrow ATA", /* Heathrow/Paddington */
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"KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
64
"KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
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"UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
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"K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
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"Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
71
* Extra registers, both 32-bit little-endian
73
#define IDE_TIMING_CONFIG 0x200
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#define IDE_INTERRUPT 0x300
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/* Kauai (U2) ATA has different register setup */
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#define IDE_KAUAI_PIO_CONFIG 0x200
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#define IDE_KAUAI_ULTRA_CONFIG 0x210
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#define IDE_KAUAI_POLL_CONFIG 0x220
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* Timing configuration register definitions
85
/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
86
#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
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#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
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#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
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#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
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/* 133Mhz cell, found in shasta.
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* See comments about 100 Mhz Uninorth 2...
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* Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
94
* weird and I don't now why .. at this stage
96
#define TR_133_PIOREG_PIO_MASK 0xff000fff
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#define TR_133_PIOREG_MDMA_MASK 0x00fff800
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#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
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#define TR_133_UDMAREG_UDMA_EN 0x00000001
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/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
102
* (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
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* controlled like gem or fw. It appears to be an evolution of keylargo
104
* ATA4 with a timing register extended to 2x32bits registers (one
105
* for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
106
* It has it's own local feature control register as well.
108
* After scratching my mind over the timing values, at least for PIO
109
* and MDMA, I think I've figured the format of the timing register,
110
* though I use pre-calculated tables for UDMA as usual...
112
#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
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#define TR_100_PIO_ADDRSETUP_SHIFT 24
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#define TR_100_MDMA_MASK 0x00fff000
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#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
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#define TR_100_MDMA_RECOVERY_SHIFT 18
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#define TR_100_MDMA_ACCESS_MASK 0x0003f000
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#define TR_100_MDMA_ACCESS_SHIFT 12
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#define TR_100_PIO_MASK 0xff000fff
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#define TR_100_PIO_RECOVERY_MASK 0x00000fc0
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#define TR_100_PIO_RECOVERY_SHIFT 6
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#define TR_100_PIO_ACCESS_MASK 0x0000003f
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#define TR_100_PIO_ACCESS_SHIFT 0
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#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
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#define TR_100_UDMAREG_UDMA_EN 0x00000001
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/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
130
* 40 connector cable and to 4 on 80 connector one.
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* Clock unit is 15ns (66Mhz)
133
* 3 Values can be programmed:
134
* - Write data setup, which appears to match the cycle time. They
135
* also call it DIOW setup.
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* - Ready to pause time (from spec)
137
* - Address setup. That one is weird. I don't see where exactly
138
* it fits in UDMA cycles, I got it's name from an obscure piece
139
* of commented out code in Darwin. They leave it to 0, we do as
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* well, despite a comment that would lead to think it has a
142
* Apple also add 60ns to the write data setup (or cycle time ?) on
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#define TR_66_UDMA_MASK 0xfff00000
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#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
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#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
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#define TR_66_PIO_ADDRSETUP_SHIFT 29
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#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
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#define TR_66_UDMA_RDY2PAUS_SHIFT 25
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#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
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#define TR_66_UDMA_WRDATASETUP_SHIFT 21
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#define TR_66_MDMA_MASK 0x000ffc00
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#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
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#define TR_66_MDMA_RECOVERY_SHIFT 15
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#define TR_66_MDMA_ACCESS_MASK 0x00007c00
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#define TR_66_MDMA_ACCESS_SHIFT 10
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#define TR_66_PIO_MASK 0xe00003ff
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#define TR_66_PIO_RECOVERY_MASK 0x000003e0
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#define TR_66_PIO_RECOVERY_SHIFT 5
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#define TR_66_PIO_ACCESS_MASK 0x0000001f
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#define TR_66_PIO_ACCESS_SHIFT 0
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/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
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* Can do pio & mdma modes, clock unit is 30ns (33Mhz)
167
* The access time and recovery time can be programmed. Some older
168
* Darwin code base limit OHare to 150ns cycle time. I decided to do
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* the same here fore safety against broken old hardware ;)
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* The HalfTick bit, when set, adds half a clock (15ns) to the access
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* time and removes one from recovery. It's not supported on KeyLargo
172
* implementation afaik. The E bit appears to be set for PIO mode 0 and
173
* is used to reach long timings used in this mode.
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#define TR_33_MDMA_MASK 0x003ff800
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#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
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#define TR_33_MDMA_RECOVERY_SHIFT 16
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#define TR_33_MDMA_ACCESS_MASK 0x0000f800
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#define TR_33_MDMA_ACCESS_SHIFT 11
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#define TR_33_MDMA_HALFTICK 0x00200000
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#define TR_33_PIO_MASK 0x000007ff
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#define TR_33_PIO_E 0x00000400
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#define TR_33_PIO_RECOVERY_MASK 0x000003e0
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#define TR_33_PIO_RECOVERY_SHIFT 5
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#define TR_33_PIO_ACCESS_MASK 0x0000001f
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#define TR_33_PIO_ACCESS_SHIFT 0
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* Interrupt register definitions. Only present on newer cells
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* (Keylargo and later afaik) so we don't use it.
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#define IDE_INTR_DMA 0x80000000
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#define IDE_INTR_DEVICE 0x40000000
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* FCR Register on Kauai. Not sure what bit 0x4 is ...
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#define KAUAI_FCR_UATA_MAGIC 0x00000004
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#define KAUAI_FCR_UATA_RESET_N 0x00000002
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#define KAUAI_FCR_UATA_ENABLE 0x00000001
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/* Allow up to 256 DBDMA commands per xfer */
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#define MAX_DCMDS 256
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/* Don't let a DMA segment go all the way to 64K */
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#define MAX_DBDMA_SEG 0xff00
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* Wait 1s for disk to answer on IDE bus after a hard reset
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* of the device (via GPIO/FCR).
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* Some devices seem to "pollute" the bus even after dropping
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* the BSY bit (typically some combo drives slave on the UDMA
216
* bus) after a hard reset. Since we hard reset all drives on
217
* KeyLargo ATA66, we have to keep that delay around. I may end
218
* up not hard resetting anymore on these and keep the delay only
219
* for older interfaces instead (we have to reset when coming
220
* from MacOS...) --BenH.
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#define IDE_WAKEUP_DELAY_MS 1000
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struct pata_macio_timing;
226
struct pata_macio_priv {
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struct device_node *node;
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struct macio_dev *mdev;
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struct pci_dev *pdev;
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void __iomem *tfregs;
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void __iomem *kauai_fcr;
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struct dbdma_cmd * dma_table_cpu;
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dma_addr_t dma_table_dma;
240
struct ata_host *host;
241
const struct pata_macio_timing *timings;
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/* Previous variants of this driver used to calculate timings
245
* for various variants of the chip and use tables for others.
247
* Not only was this confusing, but in addition, it isn't clear
248
* whether our calculation code was correct. It didn't entirely
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* match the darwin code and whatever documentation I could find
252
* I decided to entirely rely on a table instead for this version
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* of the driver. Also, because I don't really care about derated
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* modes and really old HW other than making it work, I'm not going
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* to calculate / snoop timing values for something else than the
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struct pata_macio_timing {
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u32 reg1; /* Bits to set in first timing reg */
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u32 reg2; /* Bits to set in second timing reg */
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static const struct pata_macio_timing pata_macio_ohare_timings[] = {
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{ XFER_PIO_0, 0x00000526, 0, },
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{ XFER_PIO_1, 0x00000085, 0, },
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{ XFER_PIO_2, 0x00000025, 0, },
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{ XFER_PIO_3, 0x00000025, 0, },
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{ XFER_PIO_4, 0x00000025, 0, },
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{ XFER_MW_DMA_0, 0x00074000, 0, },
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{ XFER_MW_DMA_1, 0x00221000, 0, },
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{ XFER_MW_DMA_2, 0x00211000, 0, },
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static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
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{ XFER_PIO_0, 0x00000526, 0, },
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{ XFER_PIO_1, 0x00000085, 0, },
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{ XFER_PIO_2, 0x00000025, 0, },
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{ XFER_PIO_3, 0x00000025, 0, },
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{ XFER_PIO_4, 0x00000025, 0, },
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{ XFER_MW_DMA_0, 0x00074000, 0, },
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{ XFER_MW_DMA_1, 0x00221000, 0, },
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{ XFER_MW_DMA_2, 0x00211000, 0, },
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static const struct pata_macio_timing pata_macio_kl33_timings[] = {
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{ XFER_PIO_0, 0x00000526, 0, },
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{ XFER_PIO_1, 0x00000085, 0, },
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{ XFER_PIO_2, 0x00000025, 0, },
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{ XFER_PIO_3, 0x00000025, 0, },
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{ XFER_PIO_4, 0x00000025, 0, },
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{ XFER_MW_DMA_0, 0x00084000, 0, },
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{ XFER_MW_DMA_1, 0x00021800, 0, },
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{ XFER_MW_DMA_2, 0x00011800, 0, },
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static const struct pata_macio_timing pata_macio_kl66_timings[] = {
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{ XFER_PIO_0, 0x0000038c, 0, },
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{ XFER_PIO_1, 0x0000020a, 0, },
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{ XFER_PIO_2, 0x00000127, 0, },
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{ XFER_PIO_3, 0x000000c6, 0, },
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{ XFER_PIO_4, 0x00000065, 0, },
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{ XFER_MW_DMA_0, 0x00084000, 0, },
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{ XFER_MW_DMA_1, 0x00029800, 0, },
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{ XFER_MW_DMA_2, 0x00019400, 0, },
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{ XFER_UDMA_0, 0x19100000, 0, },
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{ XFER_UDMA_1, 0x14d00000, 0, },
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{ XFER_UDMA_2, 0x10900000, 0, },
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{ XFER_UDMA_3, 0x0c700000, 0, },
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{ XFER_UDMA_4, 0x0c500000, 0, },
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static const struct pata_macio_timing pata_macio_kauai_timings[] = {
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{ XFER_PIO_0, 0x08000a92, 0, },
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{ XFER_PIO_1, 0x0800060f, 0, },
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{ XFER_PIO_2, 0x0800038b, 0, },
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{ XFER_PIO_3, 0x05000249, 0, },
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{ XFER_PIO_4, 0x04000148, 0, },
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{ XFER_MW_DMA_0, 0x00618000, 0, },
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{ XFER_MW_DMA_1, 0x00209000, 0, },
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{ XFER_MW_DMA_2, 0x00148000, 0, },
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{ XFER_UDMA_0, 0, 0x000070c1, },
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{ XFER_UDMA_1, 0, 0x00005d81, },
328
{ XFER_UDMA_2, 0, 0x00004a61, },
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{ XFER_UDMA_3, 0, 0x00003a51, },
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{ XFER_UDMA_4, 0, 0x00002a31, },
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{ XFER_UDMA_5, 0, 0x00002921, },
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static const struct pata_macio_timing pata_macio_shasta_timings[] = {
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{ XFER_PIO_0, 0x0a000c97, 0, },
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{ XFER_PIO_1, 0x07000712, 0, },
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{ XFER_PIO_2, 0x040003cd, 0, },
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{ XFER_PIO_3, 0x0500028b, 0, },
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{ XFER_PIO_4, 0x0400010a, 0, },
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{ XFER_MW_DMA_0, 0x00820800, 0, },
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{ XFER_MW_DMA_1, 0x0028b000, 0, },
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{ XFER_MW_DMA_2, 0x001ca000, 0, },
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{ XFER_UDMA_0, 0, 0x00035901, },
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{ XFER_UDMA_1, 0, 0x000348b1, },
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{ XFER_UDMA_2, 0, 0x00033881, },
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{ XFER_UDMA_3, 0, 0x00033861, },
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{ XFER_UDMA_4, 0, 0x00033841, },
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{ XFER_UDMA_5, 0, 0x00033031, },
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{ XFER_UDMA_6, 0, 0x00033021, },
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static const struct pata_macio_timing *pata_macio_find_timing(
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struct pata_macio_priv *priv,
360
for (i = 0; priv->timings[i].mode > 0; i++) {
361
if (priv->timings[i].mode == mode)
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return &priv->timings[i];
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static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
370
struct pata_macio_priv *priv = ap->private_data;
371
void __iomem *rbase = ap->ioaddr.cmd_addr;
373
if (priv->kind == controller_sh_ata6 ||
374
priv->kind == controller_un_ata6 ||
375
priv->kind == controller_k2_ata6) {
376
writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
377
writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
379
writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
382
static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
384
ata_sff_dev_select(ap, device);
387
pata_macio_apply_timings(ap, device);
390
static void pata_macio_set_timings(struct ata_port *ap,
391
struct ata_device *adev)
393
struct pata_macio_priv *priv = ap->private_data;
394
const struct pata_macio_timing *t;
396
dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
399
ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
401
ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
403
/* First clear timings */
404
priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
406
/* Now get the PIO timings */
407
t = pata_macio_find_timing(priv, adev->pio_mode);
409
dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
411
t = pata_macio_find_timing(priv, XFER_PIO_0);
415
/* PIO timings only ever use the first treg */
416
priv->treg[adev->devno][0] |= t->reg1;
418
/* Now get DMA timings */
419
t = pata_macio_find_timing(priv, adev->dma_mode);
420
if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
421
dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
422
t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
426
/* DMA timings can use both tregs */
427
priv->treg[adev->devno][0] |= t->reg1;
428
priv->treg[adev->devno][1] |= t->reg2;
430
dev_dbg(priv->dev, " -> %08x %08x\n",
431
priv->treg[adev->devno][0],
432
priv->treg[adev->devno][1]);
434
/* Apply to hardware */
435
pata_macio_apply_timings(ap, adev->devno);
439
* Blast some well known "safe" values to the timing registers at init or
440
* wakeup from sleep time, before we do real calculation
442
static void pata_macio_default_timings(struct pata_macio_priv *priv)
444
unsigned int value, value2 = 0;
447
case controller_sh_ata6:
451
case controller_un_ata6:
452
case controller_k2_ata6:
456
case controller_kl_ata4:
459
case controller_kl_ata3:
462
case controller_heathrow:
463
case controller_ohare:
468
priv->treg[0][0] = priv->treg[1][0] = value;
469
priv->treg[0][1] = priv->treg[1][1] = value2;
472
static int pata_macio_cable_detect(struct ata_port *ap)
474
struct pata_macio_priv *priv = ap->private_data;
476
/* Get cable type from device-tree */
477
if (priv->kind == controller_kl_ata4 ||
478
priv->kind == controller_un_ata6 ||
479
priv->kind == controller_k2_ata6 ||
480
priv->kind == controller_sh_ata6) {
481
const char* cable = of_get_property(priv->node, "cable-type",
483
struct device_node *root = of_find_node_by_path("/");
484
const char *model = of_get_property(root, "model", NULL);
486
if (cable && !strncmp(cable, "80-", 3)) {
487
/* Some drives fail to detect 80c cable in PowerBook
488
* These machine use proprietary short IDE cable
491
if (!strncmp(model, "PowerBook", 9))
492
return ATA_CBL_PATA40_SHORT;
494
return ATA_CBL_PATA80;
498
/* G5's seem to have incorrect cable type in device-tree.
499
* Let's assume they always have a 80 conductor cable, this seem to
500
* be always the case unless the user mucked around
502
if (of_device_is_compatible(priv->node, "K2-UATA") ||
503
of_device_is_compatible(priv->node, "shasta-ata"))
504
return ATA_CBL_PATA80;
506
/* Anything else is 40 connectors */
507
return ATA_CBL_PATA40;
510
static void pata_macio_qc_prep(struct ata_queued_cmd *qc)
512
unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
513
struct ata_port *ap = qc->ap;
514
struct pata_macio_priv *priv = ap->private_data;
515
struct scatterlist *sg;
516
struct dbdma_cmd *table;
519
dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
520
__func__, qc, qc->flags, write, qc->dev->devno);
522
if (!(qc->flags & ATA_QCFLAG_DMAMAP))
525
table = (struct dbdma_cmd *) priv->dma_table_cpu;
528
for_each_sg(qc->sg, sg, qc->n_elem, si) {
529
u32 addr, sg_len, len;
531
/* determine if physical DMA addr spans 64K boundary.
532
* Note h/w doesn't support 64-bit, so we unconditionally
533
* truncate dma_addr_t to u32.
535
addr = (u32) sg_dma_address(sg);
536
sg_len = sg_dma_len(sg);
539
/* table overflow should never happen */
540
BUG_ON (pi++ >= MAX_DCMDS);
542
len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
543
st_le16(&table->command, write ? OUTPUT_MORE: INPUT_MORE);
544
st_le16(&table->req_count, len);
545
st_le32(&table->phy_addr, addr);
547
table->xfer_status = 0;
548
table->res_count = 0;
555
/* Should never happen according to Tejun */
558
/* Convert the last command to an input/output */
560
st_le16(&table->command, write ? OUTPUT_LAST: INPUT_LAST);
563
/* Add the stop command to the end of the list */
564
memset(table, 0, sizeof(struct dbdma_cmd));
565
st_le16(&table->command, DBDMA_STOP);
567
dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
571
static void pata_macio_freeze(struct ata_port *ap)
573
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
576
unsigned int timeout = 1000000;
578
/* Make sure DMA controller is stopped */
579
writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
580
while (--timeout && (readl(&dma_regs->status) & RUN))
588
static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
590
struct ata_port *ap = qc->ap;
591
struct pata_macio_priv *priv = ap->private_data;
592
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
593
int dev = qc->dev->devno;
595
dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
597
/* Make sure DMA commands updates are visible */
598
writel(priv->dma_table_dma, &dma_regs->cmdptr);
600
/* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
603
if (priv->kind == controller_kl_ata4 &&
604
(priv->treg[dev][0] & TR_66_UDMA_EN)) {
605
void __iomem *rbase = ap->ioaddr.cmd_addr;
606
u32 reg = priv->treg[dev][0];
608
if (!(qc->tf.flags & ATA_TFLAG_WRITE))
610
writel(reg, rbase + IDE_TIMING_CONFIG);
613
/* issue r/w command */
614
ap->ops->sff_exec_command(ap, &qc->tf);
617
static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
619
struct ata_port *ap = qc->ap;
620
struct pata_macio_priv *priv = ap->private_data;
621
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
623
dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
625
writel((RUN << 16) | RUN, &dma_regs->control);
626
/* Make sure it gets to the controller right now */
627
(void)readl(&dma_regs->control);
630
static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
632
struct ata_port *ap = qc->ap;
633
struct pata_macio_priv *priv = ap->private_data;
634
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
635
unsigned int timeout = 1000000;
637
dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
639
/* Stop the DMA engine and wait for it to full halt */
640
writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
641
while (--timeout && (readl(&dma_regs->status) & RUN))
645
static u8 pata_macio_bmdma_status(struct ata_port *ap)
647
struct pata_macio_priv *priv = ap->private_data;
648
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
649
u32 dstat, rstat = ATA_DMA_INTR;
650
unsigned long timeout = 0;
652
dstat = readl(&dma_regs->status);
654
dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
656
/* We have two things to deal with here:
658
* - The dbdma won't stop if the command was started
659
* but completed with an error without transferring all
660
* datas. This happens when bad blocks are met during
661
* a multi-block transfer.
663
* - The dbdma fifo hasn't yet finished flushing to
664
* to system memory when the disk interrupt occurs.
668
/* First check for errors */
669
if ((dstat & (RUN|DEAD)) != RUN)
670
rstat |= ATA_DMA_ERR;
672
/* If ACTIVE is cleared, the STOP command has been hit and
673
* the transfer is complete. If not, we have to flush the
676
if ((dstat & ACTIVE) == 0)
679
dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
681
/* If dbdma didn't execute the STOP command yet, the
682
* active bit is still set. We consider that we aren't
683
* sharing interrupts (which is hopefully the case with
684
* those controllers) and so we just try to flush the
685
* channel for pending data in the fifo
688
writel((FLUSH << 16) | FLUSH, &dma_regs->control);
691
dstat = readl(&dma_regs->status);
692
if ((dstat & FLUSH) == 0)
694
if (++timeout > 1000) {
695
dev_warn(priv->dev, "timeout flushing DMA\n");
696
rstat |= ATA_DMA_ERR;
703
/* port_start is when we allocate the DMA command list */
704
static int pata_macio_port_start(struct ata_port *ap)
706
struct pata_macio_priv *priv = ap->private_data;
708
if (ap->ioaddr.bmdma_addr == NULL)
711
/* Allocate space for the DBDMA commands.
713
* The +2 is +1 for the stop command and +1 to allow for
714
* aligning the start address to a multiple of 16 bytes.
716
priv->dma_table_cpu =
717
dmam_alloc_coherent(priv->dev,
718
(MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
719
&priv->dma_table_dma, GFP_KERNEL);
720
if (priv->dma_table_cpu == NULL) {
721
dev_err(priv->dev, "Unable to allocate DMA command list\n");
722
ap->ioaddr.bmdma_addr = NULL;
729
static void pata_macio_irq_clear(struct ata_port *ap)
731
struct pata_macio_priv *priv = ap->private_data;
733
/* Nothing to do here */
735
dev_dbgdma(priv->dev, "%s\n", __func__);
738
static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
740
dev_dbg(priv->dev, "Enabling & resetting... \n");
745
if (priv->kind == controller_ohare && !resume) {
746
/* The code below is having trouble on some ohare machines
747
* (timing related ?). Until I can put my hand on one of these
748
* units, I keep the old way
750
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
754
/* Reset and enable controller */
755
rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
756
priv->node, priv->aapl_bus_id, 1);
757
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
758
priv->node, priv->aapl_bus_id, 1);
760
/* Only bother waiting if there's a reset control */
762
ppc_md.feature_call(PMAC_FTR_IDE_RESET,
763
priv->node, priv->aapl_bus_id, 0);
764
msleep(IDE_WAKEUP_DELAY_MS);
768
/* If resuming a PCI device, restore the config space here */
769
if (priv->pdev && resume) {
772
pci_restore_state(priv->pdev);
773
rc = pcim_enable_device(priv->pdev);
775
dev_err(&priv->pdev->dev,
776
"Failed to enable device after resume (%d)\n",
779
pci_set_master(priv->pdev);
782
/* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
783
* seem necessary and speeds up the boot process
786
writel(KAUAI_FCR_UATA_MAGIC |
787
KAUAI_FCR_UATA_RESET_N |
788
KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
791
/* Hook the standard slave config to fixup some HW related alignment
794
static int pata_macio_slave_config(struct scsi_device *sdev)
796
struct ata_port *ap = ata_shost_to_port(sdev->host);
797
struct pata_macio_priv *priv = ap->private_data;
798
struct ata_device *dev;
802
/* First call original */
803
rc = ata_scsi_slave_config(sdev);
807
/* This is lifted from sata_nv */
808
dev = &ap->link.device[sdev->id];
810
/* OHare has issues with non cache aligned DMA on some chipsets */
811
if (priv->kind == controller_ohare) {
812
blk_queue_update_dma_alignment(sdev->request_queue, 31);
813
blk_queue_update_dma_pad(sdev->request_queue, 31);
815
/* Tell the world about it */
816
ata_dev_info(dev, "OHare alignment limits applied\n");
820
/* We only have issues with ATAPI */
821
if (dev->class != ATA_DEV_ATAPI)
824
/* Shasta and K2 seem to have "issues" with reads ... */
825
if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
826
/* Allright these are bad, apply restrictions */
827
blk_queue_update_dma_alignment(sdev->request_queue, 15);
828
blk_queue_update_dma_pad(sdev->request_queue, 15);
830
/* We enable MWI and hack cache line size directly here, this
831
* is specific to this chipset and not normal values, we happen
832
* to somewhat know what we are doing here (which is basically
833
* to do the same Apple does and pray they did not get it wrong :-)
836
pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
837
pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
838
pci_write_config_word(priv->pdev, PCI_COMMAND,
839
cmd | PCI_COMMAND_INVALIDATE);
841
/* Tell the world about it */
842
ata_dev_info(dev, "K2/Shasta alignment limits applied\n");
850
static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
854
/* First, core libata suspend to do most of the work */
855
rc = ata_host_suspend(priv->host, mesg);
859
/* Restore to default timings */
860
pata_macio_default_timings(priv);
862
/* Mask interrupt. Not strictly necessary but old driver did
863
* it and I'd rather not change that here */
864
disable_irq(priv->irq);
866
/* The media bay will handle itself just fine */
870
/* Kauai has bus control FCRs directly here */
871
if (priv->kauai_fcr) {
872
u32 fcr = readl(priv->kauai_fcr);
873
fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
874
writel(fcr, priv->kauai_fcr);
877
/* For PCI, save state and disable DMA. No need to call
878
* pci_set_power_state(), the HW doesn't do D states that
879
* way, the platform code will take care of suspending the
883
pci_save_state(priv->pdev);
884
pci_disable_device(priv->pdev);
887
/* Disable the bus on older machines and the cell on kauai */
888
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
889
priv->aapl_bus_id, 0);
894
static int pata_macio_do_resume(struct pata_macio_priv *priv)
896
/* Reset and re-enable the HW */
897
pata_macio_reset_hw(priv, 1);
899
/* Sanitize drive timings */
900
pata_macio_apply_timings(priv->host->ports[0], 0);
902
/* We want our IRQ back ! */
903
enable_irq(priv->irq);
905
/* Let the libata core take it from there */
906
ata_host_resume(priv->host);
911
#endif /* CONFIG_PM */
913
static struct scsi_host_template pata_macio_sht = {
914
ATA_BASE_SHT(DRV_NAME),
915
.sg_tablesize = MAX_DCMDS,
916
/* We may not need that strict one */
917
.dma_boundary = ATA_DMA_BOUNDARY,
918
.slave_configure = pata_macio_slave_config,
921
static struct ata_port_operations pata_macio_ops = {
922
.inherits = &ata_bmdma_port_ops,
924
.freeze = pata_macio_freeze,
925
.set_piomode = pata_macio_set_timings,
926
.set_dmamode = pata_macio_set_timings,
927
.cable_detect = pata_macio_cable_detect,
928
.sff_dev_select = pata_macio_dev_select,
929
.qc_prep = pata_macio_qc_prep,
930
.bmdma_setup = pata_macio_bmdma_setup,
931
.bmdma_start = pata_macio_bmdma_start,
932
.bmdma_stop = pata_macio_bmdma_stop,
933
.bmdma_status = pata_macio_bmdma_status,
934
.port_start = pata_macio_port_start,
935
.sff_irq_clear = pata_macio_irq_clear,
938
static void __devinit pata_macio_invariants(struct pata_macio_priv *priv)
942
/* Identify the type of controller */
943
if (of_device_is_compatible(priv->node, "shasta-ata")) {
944
priv->kind = controller_sh_ata6;
945
priv->timings = pata_macio_shasta_timings;
946
} else if (of_device_is_compatible(priv->node, "kauai-ata")) {
947
priv->kind = controller_un_ata6;
948
priv->timings = pata_macio_kauai_timings;
949
} else if (of_device_is_compatible(priv->node, "K2-UATA")) {
950
priv->kind = controller_k2_ata6;
951
priv->timings = pata_macio_kauai_timings;
952
} else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
953
if (strcmp(priv->node->name, "ata-4") == 0) {
954
priv->kind = controller_kl_ata4;
955
priv->timings = pata_macio_kl66_timings;
957
priv->kind = controller_kl_ata3;
958
priv->timings = pata_macio_kl33_timings;
960
} else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
961
priv->kind = controller_heathrow;
962
priv->timings = pata_macio_heathrow_timings;
964
priv->kind = controller_ohare;
965
priv->timings = pata_macio_ohare_timings;
968
/* XXX FIXME --- setup priv->mediabay here */
970
/* Get Apple bus ID (for clock and ASIC control) */
971
bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
972
priv->aapl_bus_id = bidp ? *bidp : 0;
974
/* Fixup missing Apple bus ID in case of media-bay */
975
if (priv->mediabay && bidp == 0)
976
priv->aapl_bus_id = 1;
979
static void __devinit pata_macio_setup_ios(struct ata_ioports *ioaddr,
983
/* cmd_addr is the base of regs for that port */
984
ioaddr->cmd_addr = base;
986
/* taskfile registers */
987
ioaddr->data_addr = base + (ATA_REG_DATA << 4);
988
ioaddr->error_addr = base + (ATA_REG_ERR << 4);
989
ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
990
ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
991
ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
992
ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
993
ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
994
ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
995
ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
996
ioaddr->command_addr = base + (ATA_REG_CMD << 4);
997
ioaddr->altstatus_addr = base + 0x160;
998
ioaddr->ctl_addr = base + 0x160;
999
ioaddr->bmdma_addr = dma;
1002
static void __devinit pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
1003
struct ata_port_info *pinfo)
1007
pinfo->pio_mask = 0;
1008
pinfo->mwdma_mask = 0;
1009
pinfo->udma_mask = 0;
1011
while (priv->timings[i].mode > 0) {
1012
unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
1013
switch(priv->timings[i].mode & 0xf0) {
1014
case 0x00: /* PIO */
1015
pinfo->pio_mask |= (mask >> 8);
1017
case 0x20: /* MWDMA */
1018
pinfo->mwdma_mask |= mask;
1020
case 0x40: /* UDMA */
1021
pinfo->udma_mask |= mask;
1026
dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
1027
pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
1030
static int __devinit pata_macio_common_init(struct pata_macio_priv *priv,
1031
resource_size_t tfregs,
1032
resource_size_t dmaregs,
1033
resource_size_t fcregs,
1036
struct ata_port_info pinfo;
1037
const struct ata_port_info *ppi[] = { &pinfo, NULL };
1038
void __iomem *dma_regs = NULL;
1040
/* Fill up privates with various invariants collected from the
1043
pata_macio_invariants(priv);
1045
/* Make sure we have sane initial timings in the cache */
1046
pata_macio_default_timings(priv);
1048
/* Not sure what the real max is but we know it's less than 64K, let's
1051
dma_set_max_seg_size(priv->dev, MAX_DBDMA_SEG);
1053
/* Allocate libata host for 1 port */
1054
memset(&pinfo, 0, sizeof(struct ata_port_info));
1055
pmac_macio_calc_timing_masks(priv, &pinfo);
1056
pinfo.flags = ATA_FLAG_SLAVE_POSS;
1057
pinfo.port_ops = &pata_macio_ops;
1058
pinfo.private_data = priv;
1060
priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
1061
if (priv->host == NULL) {
1062
dev_err(priv->dev, "Failed to allocate ATA port structure\n");
1066
/* Setup the private data in host too */
1067
priv->host->private_data = priv;
1069
/* Map base registers */
1070
priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
1071
if (priv->tfregs == NULL) {
1072
dev_err(priv->dev, "Failed to map ATA ports\n");
1075
priv->host->iomap = &priv->tfregs;
1079
dma_regs = devm_ioremap(priv->dev, dmaregs,
1080
sizeof(struct dbdma_regs));
1081
if (dma_regs == NULL)
1082
dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
1085
/* If chip has local feature control, map those regs too */
1087
priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
1088
if (priv->kauai_fcr == NULL) {
1089
dev_err(priv->dev, "Failed to map ATA FCR register\n");
1094
/* Setup port data structure */
1095
pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
1096
priv->tfregs, dma_regs);
1097
priv->host->ports[0]->private_data = priv;
1099
/* hard-reset the controller */
1100
pata_macio_reset_hw(priv, 0);
1101
pata_macio_apply_timings(priv->host->ports[0], 0);
1103
/* Enable bus master if necessary */
1104
if (priv->pdev && dma_regs)
1105
pci_set_master(priv->pdev);
1107
dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
1108
macio_ata_names[priv->kind], priv->aapl_bus_id);
1112
return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,
1116
static int __devinit pata_macio_attach(struct macio_dev *mdev,
1117
const struct of_device_id *match)
1119
struct pata_macio_priv *priv;
1120
resource_size_t tfregs, dmaregs = 0;
1124
/* Check for broken device-trees */
1125
if (macio_resource_count(mdev) == 0) {
1126
dev_err(&mdev->ofdev.dev,
1127
"No addresses for controller\n");
1131
/* Enable managed resources */
1132
macio_enable_devres(mdev);
1134
/* Allocate and init private data structure */
1135
priv = devm_kzalloc(&mdev->ofdev.dev,
1136
sizeof(struct pata_macio_priv), GFP_KERNEL);
1138
dev_err(&mdev->ofdev.dev,
1139
"Failed to allocate private memory\n");
1142
priv->node = of_node_get(mdev->ofdev.dev.of_node);
1144
priv->dev = &mdev->ofdev.dev;
1146
/* Request memory resource for taskfile registers */
1147
if (macio_request_resource(mdev, 0, "pata-macio")) {
1148
dev_err(&mdev->ofdev.dev,
1149
"Cannot obtain taskfile resource\n");
1152
tfregs = macio_resource_start(mdev, 0);
1154
/* Request resources for DMA registers if any */
1155
if (macio_resource_count(mdev) >= 2) {
1156
if (macio_request_resource(mdev, 1, "pata-macio-dma"))
1157
dev_err(&mdev->ofdev.dev,
1158
"Cannot obtain DMA resource\n");
1160
dmaregs = macio_resource_start(mdev, 1);
1164
* Fixup missing IRQ for some old implementations with broken
1167
* This is a bit bogus, it should be fixed in the device-tree itself,
1168
* via the existing macio fixups, based on the type of interrupt
1169
* controller in the machine. However, I have no test HW for this case,
1170
* and this trick works well enough on those old machines...
1172
if (macio_irq_count(mdev) == 0) {
1173
dev_warn(&mdev->ofdev.dev,
1174
"No interrupts for controller, using 13\n");
1175
irq = irq_create_mapping(NULL, 13);
1177
irq = macio_irq(mdev, 0);
1179
/* Prevvent media bay callbacks until fully registered */
1180
lock_media_bay(priv->mdev->media_bay);
1182
/* Get register addresses and call common initialization */
1183
rc = pata_macio_common_init(priv,
1184
tfregs, /* Taskfile regs */
1185
dmaregs, /* DBDMA regs */
1186
0, /* Feature control */
1188
unlock_media_bay(priv->mdev->media_bay);
1193
static int __devexit pata_macio_detach(struct macio_dev *mdev)
1195
struct ata_host *host = macio_get_drvdata(mdev);
1196
struct pata_macio_priv *priv = host->private_data;
1198
lock_media_bay(priv->mdev->media_bay);
1200
/* Make sure the mediabay callback doesn't try to access
1203
priv->host->private_data = NULL;
1205
ata_host_detach(host);
1207
unlock_media_bay(priv->mdev->media_bay);
1214
static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1216
struct ata_host *host = macio_get_drvdata(mdev);
1218
return pata_macio_do_suspend(host->private_data, mesg);
1221
static int pata_macio_resume(struct macio_dev *mdev)
1223
struct ata_host *host = macio_get_drvdata(mdev);
1225
return pata_macio_do_resume(host->private_data);
1228
#endif /* CONFIG_PM */
1230
#ifdef CONFIG_PMAC_MEDIABAY
1231
static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
1233
struct ata_host *host = macio_get_drvdata(mdev);
1234
struct ata_port *ap;
1235
struct ata_eh_info *ehi;
1236
struct ata_device *dev;
1237
unsigned long flags;
1239
if (!host || !host->private_data)
1241
ap = host->ports[0];
1242
spin_lock_irqsave(ap->lock, flags);
1243
ehi = &ap->link.eh_info;
1244
if (mb_state == MB_CD) {
1245
ata_ehi_push_desc(ehi, "mediabay plug");
1246
ata_ehi_hotplugged(ehi);
1247
ata_port_freeze(ap);
1249
ata_ehi_push_desc(ehi, "mediabay unplug");
1250
ata_for_each_dev(dev, &ap->link, ALL)
1251
dev->flags |= ATA_DFLAG_DETACH;
1254
spin_unlock_irqrestore(ap->lock, flags);
1257
#endif /* CONFIG_PMAC_MEDIABAY */
1260
static int __devinit pata_macio_pci_attach(struct pci_dev *pdev,
1261
const struct pci_device_id *id)
1263
struct pata_macio_priv *priv;
1264
struct device_node *np;
1265
resource_size_t rbase;
1267
/* We cannot use a MacIO controller without its OF device node */
1268
np = pci_device_to_OF_node(pdev);
1271
"Cannot find OF device node for controller\n");
1275
/* Check that it can be enabled */
1276
if (pcim_enable_device(pdev)) {
1278
"Cannot enable controller PCI device\n");
1282
/* Allocate and init private data structure */
1283
priv = devm_kzalloc(&pdev->dev,
1284
sizeof(struct pata_macio_priv), GFP_KERNEL);
1287
"Failed to allocate private memory\n");
1290
priv->node = of_node_get(np);
1292
priv->dev = &pdev->dev;
1294
/* Get MMIO regions */
1295
if (pci_request_regions(pdev, "pata-macio")) {
1297
"Cannot obtain PCI resources\n");
1301
/* Get register addresses and call common initialization */
1302
rbase = pci_resource_start(pdev, 0);
1303
if (pata_macio_common_init(priv,
1304
rbase + 0x2000, /* Taskfile regs */
1305
rbase + 0x1000, /* DBDMA regs */
1306
rbase, /* Feature control */
1313
static void __devexit pata_macio_pci_detach(struct pci_dev *pdev)
1315
struct ata_host *host = dev_get_drvdata(&pdev->dev);
1317
ata_host_detach(host);
1322
static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1324
struct ata_host *host = dev_get_drvdata(&pdev->dev);
1326
return pata_macio_do_suspend(host->private_data, mesg);
1329
static int pata_macio_pci_resume(struct pci_dev *pdev)
1331
struct ata_host *host = dev_get_drvdata(&pdev->dev);
1333
return pata_macio_do_resume(host->private_data);
1336
#endif /* CONFIG_PM */
1338
static struct of_device_id pata_macio_match[] =
1355
static struct macio_driver pata_macio_driver =
1358
.name = "pata-macio",
1359
.owner = THIS_MODULE,
1360
.of_match_table = pata_macio_match,
1362
.probe = pata_macio_attach,
1363
.remove = pata_macio_detach,
1365
.suspend = pata_macio_suspend,
1366
.resume = pata_macio_resume,
1368
#ifdef CONFIG_PMAC_MEDIABAY
1369
.mediabay_event = pata_macio_mb_event,
1373
static const struct pci_device_id pata_macio_pci_match[] = {
1374
{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1375
{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1376
{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1377
{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1378
{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1382
static struct pci_driver pata_macio_pci_driver = {
1383
.name = "pata-pci-macio",
1384
.id_table = pata_macio_pci_match,
1385
.probe = pata_macio_pci_attach,
1386
.remove = pata_macio_pci_detach,
1388
.suspend = pata_macio_pci_suspend,
1389
.resume = pata_macio_pci_resume,
1392
.owner = THIS_MODULE,
1395
MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
1398
static int __init pata_macio_init(void)
1402
if (!machine_is(powermac))
1405
rc = pci_register_driver(&pata_macio_pci_driver);
1408
rc = macio_register_driver(&pata_macio_driver);
1410
pci_unregister_driver(&pata_macio_pci_driver);
1416
static void __exit pata_macio_exit(void)
1418
macio_unregister_driver(&pata_macio_driver);
1419
pci_unregister_driver(&pata_macio_pci_driver);
1422
module_init(pata_macio_init);
1423
module_exit(pata_macio_exit);
1425
MODULE_AUTHOR("Benjamin Herrenschmidt");
1426
MODULE_DESCRIPTION("Apple MacIO PATA driver");
1427
MODULE_LICENSE("GPL");
1428
MODULE_VERSION(DRV_VERSION);