2
* mrst/pmu.c - driver for MRST Power Management Unit
4
* Copyright (c) 2011, Intel Corporation.
6
* This program is free software; you can redistribute it and/or modify it
7
* under the terms and conditions of the GNU General Public License,
8
* version 2, as published by the Free Software Foundation.
10
* This program is distributed in the hope it will be useful, but WITHOUT
11
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15
* You should have received a copy of the GNU General Public License along with
16
* this program; if not, write to the Free Software Foundation, Inc.,
17
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20
#include <linux/cpuidle.h>
21
#include <linux/debugfs.h>
22
#include <linux/delay.h>
23
#include <linux/interrupt.h>
24
#include <linux/module.h>
25
#include <linux/pci.h>
26
#include <linux/seq_file.h>
27
#include <linux/sfi.h>
28
#include <asm/intel_scu_ipc.h>
31
#define IPCMSG_FW_REVISION 0xF4
34
u16 pci_dev_num; /* DEBUG only */
37
unsigned int pci_state_counts[PCI_D3cold + 1]; /* DEBUG only */
41
* comlete list of MRST PCI devices
43
static struct mrst_device mrst_devs[] = {
44
/* 0 */ { 0x0800, LSS_SPI0 }, /* Moorestown SPI Ctrl 0 */
45
/* 1 */ { 0x0801, LSS_SPI1 }, /* Moorestown SPI Ctrl 1 */
46
/* 2 */ { 0x0802, LSS_I2C0 }, /* Moorestown I2C 0 */
47
/* 3 */ { 0x0803, LSS_I2C1 }, /* Moorestown I2C 1 */
48
/* 4 */ { 0x0804, LSS_I2C2 }, /* Moorestown I2C 2 */
49
/* 5 */ { 0x0805, LSS_KBD }, /* Moorestown Keyboard Ctrl */
50
/* 6 */ { 0x0806, LSS_USB_HC }, /* Moorestown USB Ctrl */
51
/* 7 */ { 0x0807, LSS_SD_HC0 }, /* Moorestown SD Host Ctrl 0 */
52
/* 8 */ { 0x0808, LSS_SD_HC1 }, /* Moorestown SD Host Ctrl 1 */
53
/* 9 */ { 0x0809, LSS_NAND }, /* Moorestown NAND Ctrl */
54
/* 10 */ { 0x080a, LSS_AUDIO }, /* Moorestown Audio Ctrl */
55
/* 11 */ { 0x080b, LSS_IMAGING }, /* Moorestown ISP */
56
/* 12 */ { 0x080c, LSS_SECURITY }, /* Moorestown Security Controller */
57
/* 13 */ { 0x080d, LSS_DISPLAY }, /* Moorestown External Displays */
58
/* 14 */ { 0x080e, 0 }, /* Moorestown SCU IPC */
59
/* 15 */ { 0x080f, LSS_GPIO }, /* Moorestown GPIO Controller */
60
/* 16 */ { 0x0810, 0 }, /* Moorestown Power Management Unit */
61
/* 17 */ { 0x0811, LSS_USB_OTG }, /* Moorestown OTG Ctrl */
62
/* 18 */ { 0x0812, LSS_SPI2 }, /* Moorestown SPI Ctrl 2 */
63
/* 19 */ { 0x0813, 0 }, /* Moorestown SC DMA */
64
/* 20 */ { 0x0814, LSS_AUDIO_LPE }, /* Moorestown LPE DMA */
65
/* 21 */ { 0x0815, LSS_AUDIO_SSP }, /* Moorestown SSP0 */
67
/* 22 */ { 0x084F, LSS_SD_HC2 }, /* Moorestown SD Host Ctrl 2 */
69
/* 23 */ { 0x4102, 0 }, /* Lincroft */
70
/* 24 */ { 0x4110, 0 }, /* Lincroft */
73
/* n.b. We ignore PCI-id 0x815 in LSS9 b/c Linux has no driver for it */
74
static u16 mrst_lss9_pci_ids[] = {0x080a, 0x0814, 0};
75
static u16 mrst_lss10_pci_ids[] = {0x0800, 0x0801, 0x0802, 0x0803,
76
0x0804, 0x0805, 0x080f, 0};
78
/* handle concurrent SMP invokations of pmu_pci_set_power_state() */
79
static spinlock_t mrst_pmu_power_state_lock;
81
static unsigned int wake_counters[MRST_NUM_LSS]; /* DEBUG only */
82
static unsigned int pmu_irq_stats[INT_INVALID + 1]; /* DEBUG only */
84
static int graphics_is_off;
85
static int lss_s0i3_enabled;
86
static bool mrst_pmu_s0i3_enable;
89
static u32 pmu_wait_ready_calls;
90
static u32 pmu_wait_ready_udelays;
91
static u32 pmu_wait_ready_udelays_max;
92
static u32 pmu_wait_done_calls;
93
static u32 pmu_wait_done_udelays;
94
static u32 pmu_wait_done_udelays_max;
95
static u32 pmu_set_power_state_entry;
96
static u32 pmu_set_power_state_send_cmd;
98
static struct mrst_device *pci_id_2_mrst_dev(u16 pci_dev_num)
102
if ((pci_dev_num >= 0x0800) && (pci_dev_num <= 0x815))
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index = pci_dev_num - 0x800;
104
else if (pci_dev_num == 0x084F)
106
else if (pci_dev_num == 0x4102)
108
else if (pci_dev_num == 0x4110)
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if (pci_dev_num != mrst_devs[index].pci_dev_num) {
112
WARN_ONCE(1, FW_BUG "Unknown PCI device 0x%04X\n", pci_dev_num);
116
return &mrst_devs[index];
120
* mrst_pmu_validate_cstates
121
* @dev: cpuidle_device
123
* Certain states are not appropriate for governor to pick in some cases.
124
* This function will be called as cpuidle_device's prepare callback and
125
* thus tells governor to ignore such states when selecting the next state
129
#define IDLE_STATE4_IS_C6 4
130
#define IDLE_STATE5_IS_S0I3 5
132
int mrst_pmu_invalid_cstates(void)
134
int cpu = smp_processor_id();
137
* Demote to C4 if the PMU is busy.
138
* Since LSS changes leave the busy bit clear...
139
* busy means either the PMU is waiting for an ACK-C6 that
140
* isn't coming due to an MWAIT that returned immediately;
141
* or we returned from S0i3 successfully, and the PMU
142
* is not done sending us interrupts.
144
if (pmu_read_busy_status())
145
return 1 << IDLE_STATE4_IS_C6 | 1 << IDLE_STATE5_IS_S0I3;
148
* Disallow S0i3 if: PMU is not initialized, or CPU1 is active,
149
* or if device LSS is insufficient, or the GPU is active,
150
* or if it has been explicitly disabled.
152
if (!pmu_reg || !cpumask_equal(cpu_online_mask, cpumask_of(cpu)) ||
153
!lss_s0i3_enabled || !graphics_is_off || !mrst_pmu_s0i3_enable)
154
return 1 << IDLE_STATE5_IS_S0I3;
160
* pmu_update_wake_counters(): read PM_WKS, update wake_counters[]
163
static void pmu_update_wake_counters(void)
168
wake_status = pmu_read_wks();
170
for (lss = 0; lss < MRST_NUM_LSS; ++lss) {
171
if (wake_status & (1 << lss))
172
wake_counters[lss]++;
176
int mrst_pmu_s0i3_entry(void)
180
/* Clear any possible error conditions */
181
pmu_write_ics(0x300);
183
/* set wake control to current D-states */
184
pmu_write_wssc(S0I3_SSS_TARGET);
186
status = mrst_s0i3_entry(PM_S0I3_COMMAND, &pmu_reg->pm_cmd);
187
pmu_update_wake_counters();
191
/* poll for maximum of 5ms for busy bit to clear */
192
static int pmu_wait_ready(void)
196
pmu_wait_ready_calls++;
198
for (udelays = 0; udelays < 500; ++udelays) {
199
if (udelays > pmu_wait_ready_udelays_max)
200
pmu_wait_ready_udelays_max = udelays;
202
if (pmu_read_busy_status() == 0)
206
pmu_wait_ready_udelays++;
210
* if this fires, observe
211
* /sys/kernel/debug/mrst_pmu_wait_ready_calls
212
* /sys/kernel/debug/mrst_pmu_wait_ready_udelays
214
WARN_ONCE(1, "SCU not ready for 5ms");
217
/* poll for maximum of 50ms us for busy bit to clear */
218
static int pmu_wait_done(void)
222
pmu_wait_done_calls++;
224
for (udelays = 0; udelays < 500; ++udelays) {
225
if (udelays > pmu_wait_done_udelays_max)
226
pmu_wait_done_udelays_max = udelays;
228
if (pmu_read_busy_status() == 0)
232
pmu_wait_done_udelays++;
236
* if this fires, observe
237
* /sys/kernel/debug/mrst_pmu_wait_done_calls
238
* /sys/kernel/debug/mrst_pmu_wait_done_udelays
240
WARN_ONCE(1, "SCU not done for 50ms");
244
u32 mrst_pmu_msi_is_disabled(void)
246
return pmu_msi_is_disabled();
249
void mrst_pmu_enable_msi(void)
255
* pmu_irq - pmu driver interrupt handler
256
* Context: interrupt context
258
static irqreturn_t pmu_irq(int irq, void *dummy)
260
union pmu_pm_ics pmu_ics;
262
pmu_ics.value = pmu_read_ics();
264
if (!pmu_ics.bits.pending)
267
switch (pmu_ics.bits.cause) {
275
pmu_irq_stats[pmu_ics.bits.cause]++;
278
pmu_irq_stats[INT_INVALID]++;
281
pmu_write_ics(pmu_ics.value); /* Clear pending interrupt */
287
* Translate PCI power management to MRST LSS D-states
289
static int pci_2_mrst_state(int lss, pci_power_t pci_state)
293
if (SSMSK(D0i1, lss) & D0I1_ACG_SSS_TARGET)
305
WARN(1, "pci_state %d\n", pci_state);
310
static int pmu_issue_command(u32 pm_ssc)
312
union pmu_pm_set_cfg_cmd_t command;
314
if (pmu_read_busy_status()) {
315
pr_debug("pmu is busy, Operation not permitted\n");
320
* enable interrupts in PMU so that interrupts are
321
* propagated when ioc bit for a particular set
327
/* Configure the sub systems for pmu2 */
329
pmu_write_ssc(pm_ssc);
332
* Send the set config command for pmu its configured
333
* for mode CM_IMMEDIATE & hence with No Trigger
336
command.pmu2_params.d_param.cfg_mode = CM_IMMEDIATE;
337
command.pmu2_params.d_param.cfg_delay = 0;
338
command.pmu2_params.d_param.rsvd = 0;
340
/* construct the command to send SET_CFG to particular PMU */
341
command.pmu2_params.d_param.cmd = SET_CFG_CMD;
342
command.pmu2_params.d_param.ioc = 0;
343
command.pmu2_params.d_param.mode_id = 0;
344
command.pmu2_params.d_param.sys_state = SYS_STATE_S0I0;
346
/* write the value of PM_CMD into particular PMU */
347
pr_debug("pmu command being written %x\n",
348
command.pmu_pm_set_cfg_cmd_value);
350
pmu_write_cmd(command.pmu_pm_set_cfg_cmd_value);
355
static u16 pmu_min_lss_pci_req(u16 *ids, u16 pci_state)
357
u16 existing_request;
360
for (i = 0; ids[i]; ++i) {
361
struct mrst_device *mrst_dev;
363
mrst_dev = pci_id_2_mrst_dev(ids[i]);
364
if (unlikely(!mrst_dev))
367
existing_request = mrst_dev->latest_request;
368
if (existing_request < pci_state)
369
pci_state = existing_request;
375
* pmu_pci_set_power_state - Callback function is used by all the PCI devices
376
* for a platform specific device power on/shutdown.
379
int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t pci_state)
381
u32 old_sss, new_sss;
383
struct mrst_device *mrst_dev;
385
pmu_set_power_state_entry++;
387
BUG_ON(pdev->vendor != PCI_VENDOR_ID_INTEL);
388
BUG_ON(pci_state < PCI_D0 || pci_state > PCI_D3cold);
390
mrst_dev = pci_id_2_mrst_dev(pdev->device);
391
if (unlikely(!mrst_dev))
394
mrst_dev->pci_state_counts[pci_state]++; /* count invocations */
396
/* PMU driver calls self as part of PCI initialization, ignore */
397
if (pdev->device == PCI_DEV_ID_MRST_PMU)
400
BUG_ON(!pmu_reg); /* SW bug if called before initialized */
402
spin_lock(&mrst_pmu_power_state_lock);
404
if (pdev->d3_delay) {
405
dev_dbg(&pdev->dev, "d3_delay %d, should be 0\n",
410
* If Lincroft graphics, simply remember state
412
if ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY
413
&& !((pdev->class & PCI_SUB_CLASS_MASK) >> 8)) {
414
if (pci_state == PCI_D0)
422
goto ret; /* device with no LSS */
424
if (mrst_dev->latest_request == pci_state)
425
goto ret; /* no change */
427
mrst_dev->latest_request = pci_state; /* record latest request */
430
* LSS9 and LSS10 contain multiple PCI devices.
431
* Use the lowest numbered (highest power) state in the LSS
433
if (mrst_dev->lss == 9)
434
pci_state = pmu_min_lss_pci_req(mrst_lss9_pci_ids, pci_state);
435
else if (mrst_dev->lss == 10)
436
pci_state = pmu_min_lss_pci_req(mrst_lss10_pci_ids, pci_state);
438
status = pmu_wait_ready();
442
old_sss = pmu_read_sss();
443
new_sss = old_sss & ~SSMSK(3, mrst_dev->lss);
444
new_sss |= SSMSK(pci_2_mrst_state(mrst_dev->lss, pci_state),
447
if (new_sss == old_sss)
448
goto ret; /* nothing to do */
450
pmu_set_power_state_send_cmd++;
452
status = pmu_issue_command(new_sss);
454
if (unlikely(status != 0)) {
455
dev_err(&pdev->dev, "Failed to Issue a PM command\n");
463
((pmu_read_sss() & S0I3_SSS_TARGET) == S0I3_SSS_TARGET);
465
spin_unlock(&mrst_pmu_power_state_lock);
469
#ifdef CONFIG_DEBUG_FS
470
static char *d0ix_names[] = {"D0", "D0i1", "D0i2", "D0i3"};
472
static inline const char *d0ix_name(int state)
474
return d0ix_names[(int) state];
477
static int debug_mrst_pmu_show(struct seq_file *s, void *unused)
479
struct pci_dev *pdev = NULL;
483
seq_printf(s, "0x%08X D0I1_ACG_SSS_TARGET\n", D0I1_ACG_SSS_TARGET);
485
cur_pmsss = pmu_read_sss();
487
seq_printf(s, "0x%08X S0I3_SSS_TARGET\n", S0I3_SSS_TARGET);
489
seq_printf(s, "0x%08X Current SSS ", cur_pmsss);
490
seq_printf(s, lss_s0i3_enabled ? "\n" : "[BLOCKS s0i3]\n");
492
if (cpumask_equal(cpu_online_mask, cpumask_of(0)))
493
seq_printf(s, "cpu0 is only cpu online\n");
495
seq_printf(s, "cpu0 is NOT only cpu online [BLOCKS S0i3]\n");
497
seq_printf(s, "GFX: %s\n", graphics_is_off ? "" : "[BLOCKS s0i3]");
500
for_each_pci_dev(pdev) {
503
struct mrst_device *mrst_dev;
506
mrst_dev = pci_id_2_mrst_dev(pdev->device);
508
seq_printf(s, "%s %04x/%04X %-16.16s ",
509
dev_name(&pdev->dev),
510
pdev->vendor, pdev->device,
511
dev_driver_string(&pdev->dev));
513
if (unlikely (!mrst_dev)) {
514
seq_printf(s, " UNKNOWN\n");
519
seq_printf(s, "LSS %2d %-4s ", mrst_dev->lss,
520
d0ix_name(((cur_pmsss >>
521
(mrst_dev->lss * 2)) & 0x3)));
525
/* PCI PM config space setting */
526
pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
528
pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
529
seq_printf(s, "PCI-%-4s",
530
pci_power_name(pmcsr & PCI_PM_CTRL_STATE_MASK));
535
seq_printf(s, " %s ", pci_power_name(mrst_dev->latest_request));
536
for (i = 0; i <= PCI_D3cold; ++i)
537
seq_printf(s, "%d ", mrst_dev->pci_state_counts[i]);
540
unsigned int lssmask;
542
lssmask = SSMSK(D0i3, mrst_dev->lss);
544
if ((lssmask & S0I3_SSS_TARGET) &&
545
((lssmask & cur_pmsss) !=
546
(lssmask & S0I3_SSS_TARGET)))
547
seq_printf(s , "[BLOCKS s0i3]");
552
seq_printf(s, "Wake Counters:\n");
553
for (lss = 0; lss < MRST_NUM_LSS; ++lss)
554
seq_printf(s, "LSS%d %d\n", lss, wake_counters[lss]);
556
seq_printf(s, "Interrupt Counters:\n");
558
"INT_SPURIOUS \t%8u\n" "INT_CMD_DONE \t%8u\n"
559
"INT_CMD_ERR \t%8u\n" "INT_WAKE_RX \t%8u\n"
560
"INT_SS_ERROR \t%8u\n" "INT_S0IX_MISS\t%8u\n"
561
"INT_NO_ACKC6 \t%8u\n" "INT_INVALID \t%8u\n",
562
pmu_irq_stats[INT_SPURIOUS], pmu_irq_stats[INT_CMD_DONE],
563
pmu_irq_stats[INT_CMD_ERR], pmu_irq_stats[INT_WAKE_RX],
564
pmu_irq_stats[INT_SS_ERROR], pmu_irq_stats[INT_S0IX_MISS],
565
pmu_irq_stats[INT_NO_ACKC6], pmu_irq_stats[INT_INVALID]);
567
seq_printf(s, "mrst_pmu_wait_ready_calls %8d\n",
568
pmu_wait_ready_calls);
569
seq_printf(s, "mrst_pmu_wait_ready_udelays %8d\n",
570
pmu_wait_ready_udelays);
571
seq_printf(s, "mrst_pmu_wait_ready_udelays_max %8d\n",
572
pmu_wait_ready_udelays_max);
573
seq_printf(s, "mrst_pmu_wait_done_calls %8d\n",
574
pmu_wait_done_calls);
575
seq_printf(s, "mrst_pmu_wait_done_udelays %8d\n",
576
pmu_wait_done_udelays);
577
seq_printf(s, "mrst_pmu_wait_done_udelays_max %8d\n",
578
pmu_wait_done_udelays_max);
579
seq_printf(s, "mrst_pmu_set_power_state_entry %8d\n",
580
pmu_set_power_state_entry);
581
seq_printf(s, "mrst_pmu_set_power_state_send_cmd %8d\n",
582
pmu_set_power_state_send_cmd);
583
seq_printf(s, "SCU busy: %d\n", pmu_read_busy_status());
588
static int debug_mrst_pmu_open(struct inode *inode, struct file *file)
590
return single_open(file, debug_mrst_pmu_show, NULL);
593
static const struct file_operations devices_state_operations = {
594
.open = debug_mrst_pmu_open,
597
.release = single_release,
599
#endif /* DEBUG_FS */
602
* Validate SCU PCI shim PCI vendor capability byte
603
* against LSS hard-coded in mrst_devs[] above.
606
static void pmu_scu_firmware_debug(void)
608
struct pci_dev *pdev = NULL;
610
for_each_pci_dev(pdev) {
611
struct mrst_device *mrst_dev;
615
mrst_dev = pci_id_2_mrst_dev(pdev->device);
616
if (unlikely(!mrst_dev)) {
617
printk(KERN_ERR FW_BUG "pmu: Unknown "
618
"PCI device 0x%04X\n", pdev->device);
622
if (mrst_dev->lss == 0)
623
continue; /* no LSS in our table */
625
pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
627
printk(KERN_ERR FW_BUG "pmu: 0x%04X "
628
"missing PCI Vendor Capability\n",
632
pci_read_config_byte(pdev, pos + 4, &pci_config_lss);
633
if (!(pci_config_lss & PCI_VENDOR_CAP_LOG_SS_MASK)) {
634
printk(KERN_ERR FW_BUG "pmu: 0x%04X "
635
"invalid PCI Vendor Capability 0x%x "
636
" expected LSS 0x%X\n",
637
pdev->device, pci_config_lss, mrst_dev->lss);
640
pci_config_lss &= PCI_VENDOR_CAP_LOG_ID_MASK;
642
if (mrst_dev->lss == pci_config_lss)
645
printk(KERN_ERR FW_BUG "pmu: 0x%04X LSS = %d, expected %d\n",
646
pdev->device, pci_config_lss, mrst_dev->lss);
653
static int __devinit pmu_probe(struct pci_dev *pdev,
654
const struct pci_device_id *pci_id)
657
struct mrst_pmu_reg *pmu;
659
/* Init the device */
660
ret = pci_enable_device(pdev);
662
dev_err(&pdev->dev, "Unable to Enable PCI device\n");
666
ret = pci_request_regions(pdev, MRST_PMU_DRV_NAME);
668
dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
672
/* Map the memory of PMU reg base */
673
pmu = pci_iomap(pdev, 0, 0);
675
dev_err(&pdev->dev, "Unable to map the PMU address space\n");
680
#ifdef CONFIG_DEBUG_FS
681
/* /sys/kernel/debug/mrst_pmu */
682
(void) debugfs_create_file("mrst_pmu", S_IFREG | S_IRUGO,
683
NULL, NULL, &devices_state_operations);
685
pmu_reg = pmu; /* success */
687
if (request_irq(pdev->irq, pmu_irq, 0, MRST_PMU_DRV_NAME, NULL)) {
688
dev_err(&pdev->dev, "Registering isr has failed\n");
693
pmu_scu_firmware_debug();
695
pmu_write_wkc(S0I3_WAKE_SOURCES); /* Enable S0i3 wakeup sources */
699
pmu_write_ssc(D0I1_ACG_SSS_TARGET); /* Enable Auto-Clock_Gating */
700
pmu_write_cmd(0x201);
702
spin_lock_init(&mrst_pmu_power_state_lock);
704
/* Enable the hardware interrupt */
709
free_irq(pdev->irq, NULL);
710
pci_iounmap(pdev, pmu_reg);
713
pci_release_region(pdev, 0);
715
pci_disable_device(pdev);
719
static void __devexit pmu_remove(struct pci_dev *pdev)
721
dev_err(&pdev->dev, "Mid PM pmu_remove called\n");
723
/* Freeing up the irq */
724
free_irq(pdev->irq, NULL);
726
pci_iounmap(pdev, pmu_reg);
729
/* disable the current PCI device */
730
pci_release_region(pdev, 0);
731
pci_disable_device(pdev);
734
static DEFINE_PCI_DEVICE_TABLE(pmu_pci_ids) = {
735
{ PCI_VDEVICE(INTEL, PCI_DEV_ID_MRST_PMU), 0 },
739
MODULE_DEVICE_TABLE(pci, pmu_pci_ids);
741
static struct pci_driver driver = {
742
.name = MRST_PMU_DRV_NAME,
743
.id_table = pmu_pci_ids,
745
.remove = __devexit_p(pmu_remove),
749
* pmu_pci_register - register the PMU driver as PCI device
751
static int __init pmu_pci_register(void)
753
return pci_register_driver(&driver);
756
/* Register and probe via fs_initcall() to preceed device_initcall() */
757
fs_initcall(pmu_pci_register);
759
static void __exit mid_pci_cleanup(void)
761
pci_unregister_driver(&driver);
767
static int pmu_sfi_parse_oem(struct sfi_table_header *table)
769
struct sfi_table_simple *sb;
771
sb = (struct sfi_table_simple *)table;
772
ia_major = (sb->pentry[1] >> 0) & 0xFFFF;
773
ia_minor = (sb->pentry[1] >> 16) & 0xFFFF;
774
printk(KERN_INFO "mrst_pmu: IA FW version v%x.%x\n",
780
static int __init scu_fw_check(void)
786
return 0; /* this driver didn't probe-out */
788
sfi_table_parse("OEMB", NULL, NULL, pmu_sfi_parse_oem);
790
if (ia_major < 0x6005 || ia_minor < 0x1525) {
791
WARN(1, "mrst_pmu: IA FW version too old\n");
795
ret = intel_scu_ipc_command(IPCMSG_FW_REVISION, 0, NULL, 0,
799
WARN(1, "mrst_pmu: IPC FW version? %d\n", ret);
801
int scu_major = (fw_version >> 8) & 0xFF;
802
int scu_minor = (fw_version >> 0) & 0xFF;
804
printk(KERN_INFO "mrst_pmu: firmware v%x\n", fw_version);
806
if ((scu_major >= 0xC0) && (scu_minor >= 0x49)) {
807
printk(KERN_INFO "mrst_pmu: enabling S0i3\n");
808
mrst_pmu_s0i3_enable = true;
810
WARN(1, "mrst_pmu: S0i3 disabled, old firmware %X.%X",
811
scu_major, scu_minor);
816
late_initcall(scu_fw_check);
817
module_exit(mid_pci_cleanup);