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* Driver for Atmel AT32 and AT91 SPI Controllers
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* Copyright (C) 2006 Atmel Corporation
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <mach/board.h>
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/* SPI register offsets */
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#define SPI_RDR 0x0008
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#define SPI_TDR 0x000c
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#define SPI_IER 0x0014
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#define SPI_IDR 0x0018
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#define SPI_IMR 0x001c
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#define SPI_CSR0 0x0030
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#define SPI_CSR1 0x0034
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#define SPI_CSR2 0x0038
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#define SPI_CSR3 0x003c
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#define SPI_RPR 0x0100
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#define SPI_RCR 0x0104
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#define SPI_TPR 0x0108
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#define SPI_TCR 0x010c
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#define SPI_RNPR 0x0110
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#define SPI_RNCR 0x0114
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#define SPI_TNPR 0x0118
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#define SPI_TNCR 0x011c
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#define SPI_PTCR 0x0120
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#define SPI_PTSR 0x0124
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#define SPI_SPIEN_OFFSET 0
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#define SPI_SPIEN_SIZE 1
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#define SPI_SPIDIS_OFFSET 1
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#define SPI_SPIDIS_SIZE 1
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#define SPI_SWRST_OFFSET 7
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#define SPI_SWRST_SIZE 1
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#define SPI_LASTXFER_OFFSET 24
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#define SPI_LASTXFER_SIZE 1
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#define SPI_MSTR_OFFSET 0
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#define SPI_MSTR_SIZE 1
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#define SPI_PS_OFFSET 1
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#define SPI_PCSDEC_OFFSET 2
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#define SPI_PCSDEC_SIZE 1
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#define SPI_FDIV_OFFSET 3
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#define SPI_FDIV_SIZE 1
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#define SPI_MODFDIS_OFFSET 4
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#define SPI_MODFDIS_SIZE 1
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#define SPI_LLB_OFFSET 7
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#define SPI_LLB_SIZE 1
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#define SPI_PCS_OFFSET 16
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#define SPI_PCS_SIZE 4
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#define SPI_DLYBCS_OFFSET 24
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#define SPI_DLYBCS_SIZE 8
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/* Bitfields in RDR */
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#define SPI_RD_OFFSET 0
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#define SPI_RD_SIZE 16
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/* Bitfields in TDR */
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#define SPI_TD_OFFSET 0
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#define SPI_TD_SIZE 16
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#define SPI_RDRF_OFFSET 0
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#define SPI_RDRF_SIZE 1
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#define SPI_TDRE_OFFSET 1
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#define SPI_TDRE_SIZE 1
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#define SPI_MODF_OFFSET 2
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#define SPI_MODF_SIZE 1
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#define SPI_OVRES_OFFSET 3
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#define SPI_OVRES_SIZE 1
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#define SPI_ENDRX_OFFSET 4
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#define SPI_ENDRX_SIZE 1
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#define SPI_ENDTX_OFFSET 5
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#define SPI_ENDTX_SIZE 1
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#define SPI_RXBUFF_OFFSET 6
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#define SPI_RXBUFF_SIZE 1
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#define SPI_TXBUFE_OFFSET 7
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#define SPI_TXBUFE_SIZE 1
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#define SPI_NSSR_OFFSET 8
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#define SPI_NSSR_SIZE 1
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#define SPI_TXEMPTY_OFFSET 9
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#define SPI_TXEMPTY_SIZE 1
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#define SPI_SPIENS_OFFSET 16
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#define SPI_SPIENS_SIZE 1
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/* Bitfields in CSR0 */
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#define SPI_CPOL_OFFSET 0
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#define SPI_CPOL_SIZE 1
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#define SPI_NCPHA_OFFSET 1
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#define SPI_NCPHA_SIZE 1
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#define SPI_CSAAT_OFFSET 3
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#define SPI_CSAAT_SIZE 1
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#define SPI_BITS_OFFSET 4
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#define SPI_BITS_SIZE 4
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#define SPI_SCBR_OFFSET 8
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#define SPI_SCBR_SIZE 8
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#define SPI_DLYBS_OFFSET 16
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#define SPI_DLYBS_SIZE 8
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#define SPI_DLYBCT_OFFSET 24
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#define SPI_DLYBCT_SIZE 8
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/* Bitfields in RCR */
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#define SPI_RXCTR_OFFSET 0
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#define SPI_RXCTR_SIZE 16
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/* Bitfields in TCR */
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#define SPI_TXCTR_OFFSET 0
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#define SPI_TXCTR_SIZE 16
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/* Bitfields in RNCR */
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#define SPI_RXNCR_OFFSET 0
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#define SPI_RXNCR_SIZE 16
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/* Bitfields in TNCR */
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#define SPI_TXNCR_OFFSET 0
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#define SPI_TXNCR_SIZE 16
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/* Bitfields in PTCR */
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#define SPI_RXTEN_OFFSET 0
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#define SPI_RXTEN_SIZE 1
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#define SPI_RXTDIS_OFFSET 1
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#define SPI_RXTDIS_SIZE 1
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#define SPI_TXTEN_OFFSET 8
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#define SPI_TXTEN_SIZE 1
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#define SPI_TXTDIS_OFFSET 9
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#define SPI_TXTDIS_SIZE 1
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/* Constants for BITS */
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#define SPI_BITS_8_BPT 0
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#define SPI_BITS_9_BPT 1
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#define SPI_BITS_10_BPT 2
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#define SPI_BITS_11_BPT 3
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#define SPI_BITS_12_BPT 4
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#define SPI_BITS_13_BPT 5
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#define SPI_BITS_14_BPT 6
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#define SPI_BITS_15_BPT 7
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#define SPI_BITS_16_BPT 8
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/* Bit manipulation macros */
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#define SPI_BIT(name) \
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(1 << SPI_##name##_OFFSET)
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#define SPI_BF(name,value) \
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(((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
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#define SPI_BFEXT(name,value) \
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(((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
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#define SPI_BFINS(name,value,old) \
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( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
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| SPI_BF(name,value))
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/* Register access macros */
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#define spi_readl(port,reg) \
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__raw_readl((port)->regs + SPI_##reg)
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#define spi_writel(port,reg,value) \
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__raw_writel((value), (port)->regs + SPI_##reg)
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* The core SPI transfer engine just talks to a register bank to set up
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* DMA transfers; transfer queue progress is driven by IRQs. The clock
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* framework provides the base clock, subdivided for each spi_device.
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struct platform_device *pdev;
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struct spi_device *stay;
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struct list_head queue;
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struct spi_transfer *current_transfer;
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unsigned long current_remaining_bytes;
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struct spi_transfer *next_transfer;
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unsigned long next_remaining_bytes;
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dma_addr_t buffer_dma;
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/* Controller-specific per-slave state */
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struct atmel_spi_device {
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unsigned int npcs_pin;
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#define BUFFER_SIZE PAGE_SIZE
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#define INVALID_DMA_ADDRESS 0xffffffff
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* Version 2 of the SPI controller has
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* - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
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* - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
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* - SPI_CSRx.SBCR allows faster clocking
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* We can determine the controller version by reading the VERSION
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* register, but I haven't checked that it exists on all chips, and
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* this is cheaper anyway.
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static bool atmel_spi_is_v2(void)
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return !cpu_is_at91rm9200();
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* Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
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* they assume that spi slave device state will not change on deselect, so
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* that automagic deselection is OK. ("NPCSx rises if no data is to be
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* transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
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* controllers have CSAAT and friends.
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* Since the CSAAT functionality is a bit weird on newer controllers as
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* well, we use GPIO to control nCSx pins on all controllers, updating
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* MR.PCS to avoid confusing the controller. Using GPIOs also lets us
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* support active-high chipselects despite the controller's belief that
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* only active-low devices/systems exists.
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* However, at91rm9200 has a second erratum whereby nCS0 doesn't work
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* right when driven with GPIO. ("Mode Fault does not allow more than one
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* Master on Chip Select 0.") No workaround exists for that ... so for
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* nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
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* and (c) will trigger that first erratum in some cases.
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* TODO: Test if the atmel_spi_is_v2() branch below works on
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* AT91RM9200 if we use some other register than CSR0. However, don't
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* do this unconditionally since AP7000 has an errata where the BITS
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* field in CSR0 overrides all other CSRs.
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static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
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struct atmel_spi_device *asd = spi->controller_state;
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unsigned active = spi->mode & SPI_CS_HIGH;
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if (atmel_spi_is_v2()) {
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* Always use CSR0. This ensures that the clock
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* switches to the correct idle polarity before we
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spi_writel(as, CSR0, asd->csr);
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spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
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mr = spi_readl(as, MR);
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gpio_set_value(asd->npcs_pin, active);
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u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
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/* Make sure clock polarity is correct */
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for (i = 0; i < spi->master->num_chipselect; i++) {
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csr = spi_readl(as, CSR0 + 4 * i);
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if ((csr ^ cpol) & SPI_BIT(CPOL))
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spi_writel(as, CSR0 + 4 * i,
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csr ^ SPI_BIT(CPOL));
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mr = spi_readl(as, MR);
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mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
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if (spi->chip_select != 0)
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gpio_set_value(asd->npcs_pin, active);
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spi_writel(as, MR, mr);
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dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
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asd->npcs_pin, active ? " (high)" : "",
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static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
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struct atmel_spi_device *asd = spi->controller_state;
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unsigned active = spi->mode & SPI_CS_HIGH;
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/* only deactivate *this* device; sometimes transfers to
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* another device may be active when this routine is called.
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mr = spi_readl(as, MR);
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if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
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mr = SPI_BFINS(PCS, 0xf, mr);
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spi_writel(as, MR, mr);
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dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
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asd->npcs_pin, active ? " (low)" : "",
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if (atmel_spi_is_v2() || spi->chip_select != 0)
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gpio_set_value(asd->npcs_pin, !active);
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static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
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struct spi_transfer *xfer)
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return msg->transfers.prev == &xfer->transfer_list;
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static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
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return xfer->delay_usecs == 0 && !xfer->cs_change;
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static void atmel_spi_next_xfer_data(struct spi_master *master,
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struct spi_transfer *xfer,
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struct atmel_spi *as = spi_master_get_devdata(master);
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/* use scratch buffer only when rx or tx data is unspecified */
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*rx_dma = xfer->rx_dma + xfer->len - *plen;
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*rx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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*tx_dma = xfer->tx_dma + xfer->len - *plen;
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*tx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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memset(as->buffer, 0, len);
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dma_sync_single_for_device(&as->pdev->dev,
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as->buffer_dma, len, DMA_TO_DEVICE);
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* Submit next transfer for DMA.
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* lock is held, spi irq is blocked
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static void atmel_spi_next_xfer(struct spi_master *master,
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struct spi_message *msg)
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_transfer *xfer;
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dma_addr_t tx_dma, rx_dma;
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if (!as->current_transfer)
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xfer = list_entry(msg->transfers.next,
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struct spi_transfer, transfer_list);
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else if (!as->next_transfer)
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xfer = list_entry(as->current_transfer->transfer_list.next,
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struct spi_transfer, transfer_list);
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spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
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atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
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remaining = xfer->len - len;
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spi_writel(as, RPR, rx_dma);
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spi_writel(as, TPR, tx_dma);
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if (msg->spi->bits_per_word > 8)
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spi_writel(as, RCR, len);
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spi_writel(as, TCR, len);
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dev_dbg(&msg->spi->dev,
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" start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
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xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma);
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xfer = as->next_transfer;
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remaining = as->next_remaining_bytes;
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as->current_transfer = xfer;
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as->current_remaining_bytes = remaining;
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else if (!atmel_spi_xfer_is_last(msg, xfer)
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&& atmel_spi_xfer_can_be_chained(xfer)) {
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xfer = list_entry(xfer->transfer_list.next,
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struct spi_transfer, transfer_list);
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as->next_transfer = xfer;
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atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
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as->next_remaining_bytes = total - len;
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spi_writel(as, RNPR, rx_dma);
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spi_writel(as, TNPR, tx_dma);
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if (msg->spi->bits_per_word > 8)
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spi_writel(as, RNCR, len);
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spi_writel(as, TNCR, len);
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dev_dbg(&msg->spi->dev,
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" next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
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xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma);
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ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
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spi_writel(as, RNCR, 0);
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spi_writel(as, TNCR, 0);
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ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
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/* REVISIT: We're waiting for ENDRX before we start the next
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* transfer because we need to handle some difficult timing
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* issues otherwise. If we wait for ENDTX in one transfer and
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* then starts waiting for ENDRX in the next, it's difficult
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* to tell the difference between the ENDRX interrupt we're
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* actually waiting for and the ENDRX interrupt of the
461
* It should be doable, though. Just not now...
463
spi_writel(as, IER, ieval);
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spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
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static void atmel_spi_next_message(struct spi_master *master)
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_message *msg;
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struct spi_device *spi;
473
BUG_ON(as->current_transfer);
475
msg = list_entry(as->queue.next, struct spi_message, queue);
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dev_dbg(master->dev.parent, "start message %p for %s\n",
479
msg, dev_name(&spi->dev));
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/* select chip if it's not still active */
483
if (as->stay != spi) {
484
cs_deactivate(as, as->stay);
485
cs_activate(as, spi);
489
cs_activate(as, spi);
491
atmel_spi_next_xfer(master, msg);
495
* For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
496
* - The buffer is either valid for CPU access, else NULL
497
* - If the buffer is valid, so is its DMA address
499
* This driver manages the dma address unless message->is_dma_mapped.
502
atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
504
struct device *dev = &as->pdev->dev;
506
xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
508
/* tx_buf is a const void* where we need a void * for the dma
510
void *nonconst_tx = (void *)xfer->tx_buf;
512
xfer->tx_dma = dma_map_single(dev,
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nonconst_tx, xfer->len,
515
if (dma_mapping_error(dev, xfer->tx_dma))
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xfer->rx_dma = dma_map_single(dev,
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xfer->rx_buf, xfer->len,
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if (dma_mapping_error(dev, xfer->rx_dma)) {
524
dma_unmap_single(dev,
525
xfer->tx_dma, xfer->len,
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static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
534
struct spi_transfer *xfer)
536
if (xfer->tx_dma != INVALID_DMA_ADDRESS)
537
dma_unmap_single(master->dev.parent, xfer->tx_dma,
538
xfer->len, DMA_TO_DEVICE);
539
if (xfer->rx_dma != INVALID_DMA_ADDRESS)
540
dma_unmap_single(master->dev.parent, xfer->rx_dma,
541
xfer->len, DMA_FROM_DEVICE);
545
atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
546
struct spi_message *msg, int status, int stay)
548
if (!stay || status < 0)
549
cs_deactivate(as, msg->spi);
553
list_del(&msg->queue);
554
msg->status = status;
556
dev_dbg(master->dev.parent,
557
"xfer complete: %u bytes transferred\n",
560
spin_unlock(&as->lock);
561
msg->complete(msg->context);
562
spin_lock(&as->lock);
564
as->current_transfer = NULL;
565
as->next_transfer = NULL;
567
/* continue if needed */
568
if (list_empty(&as->queue) || as->stopping)
569
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
571
atmel_spi_next_message(master);
575
atmel_spi_interrupt(int irq, void *dev_id)
577
struct spi_master *master = dev_id;
578
struct atmel_spi *as = spi_master_get_devdata(master);
579
struct spi_message *msg;
580
struct spi_transfer *xfer;
581
u32 status, pending, imr;
584
spin_lock(&as->lock);
586
xfer = as->current_transfer;
587
msg = list_entry(as->queue.next, struct spi_message, queue);
589
imr = spi_readl(as, IMR);
590
status = spi_readl(as, SR);
591
pending = status & imr;
593
if (pending & SPI_BIT(OVRES)) {
598
spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
602
* When we get an overrun, we disregard the current
603
* transfer. Data will not be copied back from any
604
* bounce buffer and msg->actual_len will not be
605
* updated with the last xfer.
607
* We will also not process any remaning transfers in
610
* First, stop the transfer and unmap the DMA buffers.
612
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
613
if (!msg->is_dma_mapped)
614
atmel_spi_dma_unmap_xfer(master, xfer);
616
/* REVISIT: udelay in irq is unfriendly */
617
if (xfer->delay_usecs)
618
udelay(xfer->delay_usecs);
620
dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
621
spi_readl(as, TCR), spi_readl(as, RCR));
624
* Clean up DMA registers and make sure the data
625
* registers are empty.
627
spi_writel(as, RNCR, 0);
628
spi_writel(as, TNCR, 0);
629
spi_writel(as, RCR, 0);
630
spi_writel(as, TCR, 0);
631
for (timeout = 1000; timeout; timeout--)
632
if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
635
dev_warn(master->dev.parent,
636
"timeout waiting for TXEMPTY");
637
while (spi_readl(as, SR) & SPI_BIT(RDRF))
640
/* Clear any overrun happening while cleaning up */
643
atmel_spi_msg_done(master, as, msg, -EIO, 0);
644
} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
647
spi_writel(as, IDR, pending);
649
if (as->current_remaining_bytes == 0) {
650
msg->actual_length += xfer->len;
652
if (!msg->is_dma_mapped)
653
atmel_spi_dma_unmap_xfer(master, xfer);
655
/* REVISIT: udelay in irq is unfriendly */
656
if (xfer->delay_usecs)
657
udelay(xfer->delay_usecs);
659
if (atmel_spi_xfer_is_last(msg, xfer)) {
660
/* report completed message */
661
atmel_spi_msg_done(master, as, msg, 0,
664
if (xfer->cs_change) {
665
cs_deactivate(as, msg->spi);
667
cs_activate(as, msg->spi);
671
* Not done yet. Submit the next transfer.
673
* FIXME handle protocol options for xfer
675
atmel_spi_next_xfer(master, msg);
679
* Keep going, we still have data to send in
680
* the current transfer.
682
atmel_spi_next_xfer(master, msg);
686
spin_unlock(&as->lock);
691
static int atmel_spi_setup(struct spi_device *spi)
693
struct atmel_spi *as;
694
struct atmel_spi_device *asd;
696
unsigned int bits = spi->bits_per_word;
697
unsigned long bus_hz;
698
unsigned int npcs_pin;
701
as = spi_master_get_devdata(spi->master);
706
if (spi->chip_select > spi->master->num_chipselect) {
708
"setup: invalid chipselect %u (%u defined)\n",
709
spi->chip_select, spi->master->num_chipselect);
713
if (bits < 8 || bits > 16) {
715
"setup: invalid bits_per_word %u (8 to 16)\n",
720
/* see notes above re chipselect */
721
if (!atmel_spi_is_v2()
722
&& spi->chip_select == 0
723
&& (spi->mode & SPI_CS_HIGH)) {
724
dev_dbg(&spi->dev, "setup: can't be active-high\n");
728
/* v1 chips start out at half the peripheral bus speed. */
729
bus_hz = clk_get_rate(as->clk);
730
if (!atmel_spi_is_v2())
733
if (spi->max_speed_hz) {
735
* Calculate the lowest divider that satisfies the
736
* constraint, assuming div32/fdiv/mbz == 0.
738
scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
741
* If the resulting divider doesn't fit into the
742
* register bitfield, we can't satisfy the constraint.
744
if (scbr >= (1 << SPI_SCBR_SIZE)) {
746
"setup: %d Hz too slow, scbr %u; min %ld Hz\n",
747
spi->max_speed_hz, scbr, bus_hz/255);
751
/* speed zero means "as slow as possible" */
754
csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
755
if (spi->mode & SPI_CPOL)
756
csr |= SPI_BIT(CPOL);
757
if (!(spi->mode & SPI_CPHA))
758
csr |= SPI_BIT(NCPHA);
760
/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
762
* DLYBCT would add delays between words, slowing down transfers.
763
* It could potentially be useful to cope with DMA bottlenecks, but
764
* in those cases it's probably best to just use a lower bitrate.
766
csr |= SPI_BF(DLYBS, 0);
767
csr |= SPI_BF(DLYBCT, 0);
769
/* chipselect must have been muxed as GPIO (e.g. in board setup) */
770
npcs_pin = (unsigned int)spi->controller_data;
771
asd = spi->controller_state;
773
asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
777
ret = gpio_request(npcs_pin, dev_name(&spi->dev));
783
asd->npcs_pin = npcs_pin;
784
spi->controller_state = asd;
785
gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
789
spin_lock_irqsave(&as->lock, flags);
792
cs_deactivate(as, spi);
793
spin_unlock_irqrestore(&as->lock, flags);
799
"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
800
bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
802
if (!atmel_spi_is_v2())
803
spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
808
static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
810
struct atmel_spi *as;
811
struct spi_transfer *xfer;
813
struct device *controller = spi->master->dev.parent;
815
struct atmel_spi_device *asd;
817
as = spi_master_get_devdata(spi->master);
819
dev_dbg(controller, "new message %p submitted for %s\n",
820
msg, dev_name(&spi->dev));
822
if (unlikely(list_empty(&msg->transfers)))
828
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
829
if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
830
dev_dbg(&spi->dev, "missing rx or tx buf\n");
834
if (xfer->bits_per_word) {
835
asd = spi->controller_state;
836
bits = (asd->csr >> 4) & 0xf;
837
if (bits != xfer->bits_per_word - 8) {
838
dev_dbg(&spi->dev, "you can't yet change "
839
"bits_per_word in transfers\n");
844
/* FIXME implement these protocol options!! */
845
if (xfer->speed_hz) {
846
dev_dbg(&spi->dev, "no protocol options yet\n");
851
* DMA map early, for performance (empties dcache ASAP) and
852
* better fault reporting. This is a DMA-only driver.
854
* NOTE that if dma_unmap_single() ever starts to do work on
855
* platforms supported by this driver, we would need to clean
856
* up mappings for previously-mapped transfers.
858
if (!msg->is_dma_mapped) {
859
if (atmel_spi_dma_map_xfer(as, xfer) < 0)
865
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
867
" xfer %p: len %u tx %p/%08x rx %p/%08x\n",
869
xfer->tx_buf, xfer->tx_dma,
870
xfer->rx_buf, xfer->rx_dma);
874
msg->status = -EINPROGRESS;
875
msg->actual_length = 0;
877
spin_lock_irqsave(&as->lock, flags);
878
list_add_tail(&msg->queue, &as->queue);
879
if (!as->current_transfer)
880
atmel_spi_next_message(spi->master);
881
spin_unlock_irqrestore(&as->lock, flags);
886
static void atmel_spi_cleanup(struct spi_device *spi)
888
struct atmel_spi *as = spi_master_get_devdata(spi->master);
889
struct atmel_spi_device *asd = spi->controller_state;
890
unsigned gpio = (unsigned) spi->controller_data;
896
spin_lock_irqsave(&as->lock, flags);
897
if (as->stay == spi) {
899
cs_deactivate(as, spi);
901
spin_unlock_irqrestore(&as->lock, flags);
903
spi->controller_state = NULL;
908
/*-------------------------------------------------------------------------*/
910
static int __devinit atmel_spi_probe(struct platform_device *pdev)
912
struct resource *regs;
916
struct spi_master *master;
917
struct atmel_spi *as;
919
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
923
irq = platform_get_irq(pdev, 0);
927
clk = clk_get(&pdev->dev, "spi_clk");
931
/* setup spi core then atmel-specific driver state */
933
master = spi_alloc_master(&pdev->dev, sizeof *as);
937
/* the spi->mode bits understood by this driver: */
938
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
940
master->bus_num = pdev->id;
941
master->num_chipselect = 4;
942
master->setup = atmel_spi_setup;
943
master->transfer = atmel_spi_transfer;
944
master->cleanup = atmel_spi_cleanup;
945
platform_set_drvdata(pdev, master);
947
as = spi_master_get_devdata(master);
950
* Scratch buffer is used for throwaway rx and tx data.
951
* It's coherent to minimize dcache pollution.
953
as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
954
&as->buffer_dma, GFP_KERNEL);
958
spin_lock_init(&as->lock);
959
INIT_LIST_HEAD(&as->queue);
961
as->regs = ioremap(regs->start, resource_size(regs));
963
goto out_free_buffer;
967
ret = request_irq(irq, atmel_spi_interrupt, 0,
968
dev_name(&pdev->dev), master);
972
/* Initialize the hardware */
974
spi_writel(as, CR, SPI_BIT(SWRST));
975
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
976
spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
977
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
978
spi_writel(as, CR, SPI_BIT(SPIEN));
981
dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
982
(unsigned long)regs->start, irq);
984
ret = spi_register_master(master);
991
spi_writel(as, CR, SPI_BIT(SWRST));
992
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
994
free_irq(irq, master);
998
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1002
spi_master_put(master);
1006
static int __devexit atmel_spi_remove(struct platform_device *pdev)
1008
struct spi_master *master = platform_get_drvdata(pdev);
1009
struct atmel_spi *as = spi_master_get_devdata(master);
1010
struct spi_message *msg;
1012
/* reset the hardware and block queue progress */
1013
spin_lock_irq(&as->lock);
1015
spi_writel(as, CR, SPI_BIT(SWRST));
1016
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1018
spin_unlock_irq(&as->lock);
1020
/* Terminate remaining queued transfers */
1021
list_for_each_entry(msg, &as->queue, queue) {
1022
/* REVISIT unmapping the dma is a NOP on ARM and AVR32
1023
* but we shouldn't depend on that...
1025
msg->status = -ESHUTDOWN;
1026
msg->complete(msg->context);
1029
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1032
clk_disable(as->clk);
1034
free_irq(as->irq, master);
1037
spi_unregister_master(master);
1044
static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
1046
struct spi_master *master = platform_get_drvdata(pdev);
1047
struct atmel_spi *as = spi_master_get_devdata(master);
1049
clk_disable(as->clk);
1053
static int atmel_spi_resume(struct platform_device *pdev)
1055
struct spi_master *master = platform_get_drvdata(pdev);
1056
struct atmel_spi *as = spi_master_get_devdata(master);
1058
clk_enable(as->clk);
1063
#define atmel_spi_suspend NULL
1064
#define atmel_spi_resume NULL
1068
static struct platform_driver atmel_spi_driver = {
1070
.name = "atmel_spi",
1071
.owner = THIS_MODULE,
1073
.suspend = atmel_spi_suspend,
1074
.resume = atmel_spi_resume,
1075
.probe = atmel_spi_probe,
1076
.remove = __exit_p(atmel_spi_remove),
1078
module_platform_driver(atmel_spi_driver);
1080
MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1081
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1082
MODULE_LICENSE("GPL");
1083
MODULE_ALIAS("platform:atmel_spi");