2
* Copyright (C) 1999 Eddie C. Dost (ecd@atecom.com)
5
#include <linux/types.h>
6
#include <linux/sched.h>
8
#include <asm/uaccess.h>
11
#include <asm/sfp-machine.h>
12
#include <math-emu/double.h>
14
#define FLOATFUNC(x) extern int x(void *, void *, void *, void *)
68
#define OP31 0x1f /* 31 */
69
#define LFS 0x30 /* 48 */
70
#define LFSU 0x31 /* 49 */
71
#define LFD 0x32 /* 50 */
72
#define LFDU 0x33 /* 51 */
73
#define STFS 0x34 /* 52 */
74
#define STFSU 0x35 /* 53 */
75
#define STFD 0x36 /* 54 */
76
#define STFDU 0x37 /* 55 */
77
#define OP59 0x3b /* 59 */
78
#define OP63 0x3f /* 63 */
82
#define LFSX 0x217 /* 535 */
83
#define LFSUX 0x237 /* 567 */
84
#define LFDX 0x257 /* 599 */
85
#define LFDUX 0x277 /* 631 */
86
#define STFSX 0x297 /* 663 */
87
#define STFSUX 0x2b7 /* 695 */
88
#define STFDX 0x2d7 /* 727 */
89
#define STFDUX 0x2f7 /* 759 */
90
#define STFIWX 0x3d7 /* 983 */
94
#define FDIVS 0x012 /* 18 */
95
#define FSUBS 0x014 /* 20 */
96
#define FADDS 0x015 /* 21 */
97
#define FSQRTS 0x016 /* 22 */
98
#define FRES 0x018 /* 24 */
99
#define FMULS 0x019 /* 25 */
100
#define FMSUBS 0x01c /* 28 */
101
#define FMADDS 0x01d /* 29 */
102
#define FNMSUBS 0x01e /* 30 */
103
#define FNMADDS 0x01f /* 31 */
107
#define FDIV 0x012 /* 18 */
108
#define FSUB 0x014 /* 20 */
109
#define FADD 0x015 /* 21 */
110
#define FSQRT 0x016 /* 22 */
111
#define FSEL 0x017 /* 23 */
112
#define FMUL 0x019 /* 25 */
113
#define FRSQRTE 0x01a /* 26 */
114
#define FMSUB 0x01c /* 28 */
115
#define FMADD 0x01d /* 29 */
116
#define FNMSUB 0x01e /* 30 */
117
#define FNMADD 0x01f /* 31 */
120
#define FCMPU 0x000 /* 0 */
121
#define FRSP 0x00c /* 12 */
122
#define FCTIW 0x00e /* 14 */
123
#define FCTIWZ 0x00f /* 15 */
124
#define FCMPO 0x020 /* 32 */
125
#define MTFSB1 0x026 /* 38 */
126
#define FNEG 0x028 /* 40 */
127
#define MCRFS 0x040 /* 64 */
128
#define MTFSB0 0x046 /* 70 */
129
#define FMR 0x048 /* 72 */
130
#define MTFSFI 0x086 /* 134 */
131
#define FNABS 0x088 /* 136 */
132
#define FABS 0x108 /* 264 */
133
#define MFFS 0x247 /* 583 */
134
#define MTFSF 0x2c7 /* 711 */
153
#ifdef CONFIG_MATH_EMULATION
155
record_exception(struct pt_regs *regs, int eflag)
163
if (eflag & EFLAG_OVERFLOW)
165
if (eflag & EFLAG_UNDERFLOW)
167
if (eflag & EFLAG_DIVZERO)
169
if (eflag & EFLAG_INEXACT)
171
if (eflag & EFLAG_INVALID)
173
if (eflag & EFLAG_VXSNAN)
174
fpscr |= FPSCR_VXSNAN;
175
if (eflag & EFLAG_VXISI)
176
fpscr |= FPSCR_VXISI;
177
if (eflag & EFLAG_VXIDI)
178
fpscr |= FPSCR_VXIDI;
179
if (eflag & EFLAG_VXZDZ)
180
fpscr |= FPSCR_VXZDZ;
181
if (eflag & EFLAG_VXIMZ)
182
fpscr |= FPSCR_VXIMZ;
183
if (eflag & EFLAG_VXVC)
185
if (eflag & EFLAG_VXSOFT)
186
fpscr |= FPSCR_VXSOFT;
187
if (eflag & EFLAG_VXSQRT)
188
fpscr |= FPSCR_VXSQRT;
189
if (eflag & EFLAG_VXCVI)
190
fpscr |= FPSCR_VXCVI;
193
// fpscr &= ~(FPSCR_VX);
194
if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
195
FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
196
FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
199
fpscr &= ~(FPSCR_FEX);
200
if (((fpscr & FPSCR_VX) && (fpscr & FPSCR_VE)) ||
201
((fpscr & FPSCR_OX) && (fpscr & FPSCR_OE)) ||
202
((fpscr & FPSCR_UX) && (fpscr & FPSCR_UE)) ||
203
((fpscr & FPSCR_ZX) && (fpscr & FPSCR_ZE)) ||
204
((fpscr & FPSCR_XX) && (fpscr & FPSCR_XE)))
209
return (fpscr & FPSCR_FEX) ? 1 : 0;
211
#endif /* CONFIG_MATH_EMULATION */
214
do_mathemu(struct pt_regs *regs)
216
void *op0 = 0, *op1 = 0, *op2 = 0, *op3 = 0;
217
unsigned long pc = regs->nip;
221
#ifdef CONFIG_MATH_EMULATION
222
int (*func)(void *, void *, void *, void *);
227
if (get_user(insn, (u32 *)pc))
230
#ifndef CONFIG_MATH_EMULATION
231
switch (insn >> 26) {
233
idx = (insn >> 16) & 0x1f;
234
sdisp = (insn & 0xffff);
235
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
236
op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
237
lfd(op0, op1, op2, op3);
240
idx = (insn >> 16) & 0x1f;
241
sdisp = (insn & 0xffff);
242
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
243
op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
244
lfd(op0, op1, op2, op3);
245
regs->gpr[idx] = (unsigned long)op1;
248
idx = (insn >> 16) & 0x1f;
249
sdisp = (insn & 0xffff);
250
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
251
op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
252
stfd(op0, op1, op2, op3);
255
idx = (insn >> 16) & 0x1f;
256
sdisp = (insn & 0xffff);
257
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
258
op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
259
stfd(op0, op1, op2, op3);
260
regs->gpr[idx] = (unsigned long)op1;
263
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
264
op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
265
fmr(op0, op1, op2, op3);
270
#else /* CONFIG_MATH_EMULATION */
271
switch (insn >> 26) {
272
case LFS: func = lfs; type = D; break;
273
case LFSU: func = lfs; type = DU; break;
274
case LFD: func = lfd; type = D; break;
275
case LFDU: func = lfd; type = DU; break;
276
case STFS: func = stfs; type = D; break;
277
case STFSU: func = stfs; type = DU; break;
278
case STFD: func = stfd; type = D; break;
279
case STFDU: func = stfd; type = DU; break;
282
switch ((insn >> 1) & 0x3ff) {
283
case LFSX: func = lfs; type = XE; break;
284
case LFSUX: func = lfs; type = XEU; break;
285
case LFDX: func = lfd; type = XE; break;
286
case LFDUX: func = lfd; type = XEU; break;
287
case STFSX: func = stfs; type = XE; break;
288
case STFSUX: func = stfs; type = XEU; break;
289
case STFDX: func = stfd; type = XE; break;
290
case STFDUX: func = stfd; type = XEU; break;
291
case STFIWX: func = stfiwx; type = XE; break;
298
switch ((insn >> 1) & 0x1f) {
299
case FDIVS: func = fdivs; type = AB; break;
300
case FSUBS: func = fsubs; type = AB; break;
301
case FADDS: func = fadds; type = AB; break;
302
case FSQRTS: func = fsqrts; type = AB; break;
303
case FRES: func = fres; type = AB; break;
304
case FMULS: func = fmuls; type = AC; break;
305
case FMSUBS: func = fmsubs; type = ABC; break;
306
case FMADDS: func = fmadds; type = ABC; break;
307
case FNMSUBS: func = fnmsubs; type = ABC; break;
308
case FNMADDS: func = fnmadds; type = ABC; break;
316
switch ((insn >> 1) & 0x1f) {
317
case FDIV: func = fdiv; type = AB; break;
318
case FSUB: func = fsub; type = AB; break;
319
case FADD: func = fadd; type = AB; break;
320
case FSQRT: func = fsqrt; type = AB; break;
321
case FSEL: func = fsel; type = ABC; break;
322
case FMUL: func = fmul; type = AC; break;
323
case FRSQRTE: func = frsqrte; type = AB; break;
324
case FMSUB: func = fmsub; type = ABC; break;
325
case FMADD: func = fmadd; type = ABC; break;
326
case FNMSUB: func = fnmsub; type = ABC; break;
327
case FNMADD: func = fnmadd; type = ABC; break;
334
switch ((insn >> 1) & 0x3ff) {
335
case FCMPU: func = fcmpu; type = XCR; break;
336
case FRSP: func = frsp; type = XB; break;
337
case FCTIW: func = fctiw; type = XB; break;
338
case FCTIWZ: func = fctiwz; type = XB; break;
339
case FCMPO: func = fcmpo; type = XCR; break;
340
case MTFSB1: func = mtfsb1; type = XCRB; break;
341
case FNEG: func = fneg; type = XB; break;
342
case MCRFS: func = mcrfs; type = XCRL; break;
343
case MTFSB0: func = mtfsb0; type = XCRB; break;
344
case FMR: func = fmr; type = XB; break;
345
case MTFSFI: func = mtfsfi; type = XCRI; break;
346
case FNABS: func = fnabs; type = XB; break;
347
case FABS: func = fabs; type = XB; break;
348
case MFFS: func = mffs; type = X; break;
349
case MTFSF: func = mtfsf; type = XFLB; break;
361
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
362
op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
363
op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
367
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
368
op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
369
op2 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
373
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
374
op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
375
op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
376
op3 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
380
idx = (insn >> 16) & 0x1f;
381
sdisp = (insn & 0xffff);
382
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
383
op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
387
idx = (insn >> 16) & 0x1f;
391
sdisp = (insn & 0xffff);
392
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
393
op1 = (void *)(regs->gpr[idx] + sdisp);
397
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
401
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
402
op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
406
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
407
op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
411
idx = (insn >> 16) & 0x1f;
412
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
414
if (((insn >> 1) & 0x3ff) == STFIWX)
415
op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]);
419
op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]);
425
idx = (insn >> 16) & 0x1f;
426
op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
427
op1 = (void *)((idx ? regs->gpr[idx] : 0)
428
+ regs->gpr[(insn >> 11) & 0x1f]);
432
op0 = (void *)®s->ccr;
433
op1 = (void *)((insn >> 23) & 0x7);
434
op2 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
435
op3 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
439
op0 = (void *)®s->ccr;
440
op1 = (void *)((insn >> 23) & 0x7);
441
op2 = (void *)((insn >> 18) & 0x7);
445
op0 = (void *)((insn >> 21) & 0x1f);
449
op0 = (void *)((insn >> 23) & 0x7);
450
op1 = (void *)((insn >> 12) & 0xf);
454
op0 = (void *)((insn >> 17) & 0xff);
455
op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
462
eflag = func(op0, op1, op2, op3);
465
regs->ccr &= ~(0x0f000000);
466
regs->ccr |= (__FPU_FPSCR >> 4) & 0x0f000000;
469
trap = record_exception(regs, eflag);
476
regs->gpr[idx] = (unsigned long)op1;
482
#endif /* CONFIG_MATH_EMULATION */