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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* Copyright (C) 2004 Infineon IFAP DC COM CPE
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <lantiq_soc.h>
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#define PORT_LTQ_ASC 111
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#define UART_DUMMY_UER_RX 1
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#define DRVNAME "ltq_asc"
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#define LTQ_ASC_TBUF (0x0020 + 3)
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#define LTQ_ASC_RBUF (0x0024 + 3)
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#define LTQ_ASC_TBUF 0x0020
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#define LTQ_ASC_RBUF 0x0024
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#define LTQ_ASC_FSTAT 0x0048
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#define LTQ_ASC_WHBSTATE 0x0018
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#define LTQ_ASC_STATE 0x0014
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#define LTQ_ASC_IRNCR 0x00F8
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#define LTQ_ASC_CLC 0x0000
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#define LTQ_ASC_ID 0x0008
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#define LTQ_ASC_PISEL 0x0004
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#define LTQ_ASC_TXFCON 0x0044
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#define LTQ_ASC_RXFCON 0x0040
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#define LTQ_ASC_CON 0x0010
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#define LTQ_ASC_BG 0x0050
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#define LTQ_ASC_IRNREN 0x00F4
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#define ASC_IRNREN_TX 0x1
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#define ASC_IRNREN_RX 0x2
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#define ASC_IRNREN_ERR 0x4
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#define ASC_IRNREN_TX_BUF 0x8
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#define ASC_IRNCR_TIR 0x1
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#define ASC_IRNCR_RIR 0x2
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#define ASC_IRNCR_EIR 0x4
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#define ASCOPT_CSIZE 0x3
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#define ASCCLC_DISS 0x2
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#define ASCCLC_RMCMASK 0x0000FF00
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#define ASCCLC_RMCOFFSET 8
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#define ASCCON_M_8ASYNC 0x0
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#define ASCCON_M_7ASYNC 0x2
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#define ASCCON_ODD 0x00000020
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#define ASCCON_STP 0x00000080
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#define ASCCON_BRS 0x00000100
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#define ASCCON_FDE 0x00000200
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#define ASCCON_R 0x00008000
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#define ASCCON_FEN 0x00020000
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#define ASCCON_ROEN 0x00080000
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#define ASCCON_TOEN 0x00100000
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#define ASCSTATE_PE 0x00010000
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#define ASCSTATE_FE 0x00020000
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#define ASCSTATE_ROE 0x00080000
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#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
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#define ASCWHBSTATE_CLRREN 0x00000001
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#define ASCWHBSTATE_SETREN 0x00000002
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#define ASCWHBSTATE_CLRPE 0x00000004
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#define ASCWHBSTATE_CLRFE 0x00000008
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#define ASCWHBSTATE_CLRROE 0x00000020
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#define ASCTXFCON_TXFEN 0x0001
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#define ASCTXFCON_TXFFLU 0x0002
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#define ASCTXFCON_TXFITLMASK 0x3F00
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#define ASCTXFCON_TXFITLOFF 8
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#define ASCRXFCON_RXFEN 0x0001
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#define ASCRXFCON_RXFFLU 0x0002
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#define ASCRXFCON_RXFITLMASK 0x3F00
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#define ASCRXFCON_RXFITLOFF 8
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#define ASCFSTAT_RXFFLMASK 0x003F
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFREEMASK 0x3F000000
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#define ASCFSTAT_TXFREEOFF 24
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static void lqasc_tx_chars(struct uart_port *port);
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static struct ltq_uart_port *lqasc_port[MAXPORTS];
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static struct uart_driver lqasc_reg;
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static DEFINE_SPINLOCK(ltq_asc_lock);
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struct ltq_uart_port {
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struct uart_port port;
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unsigned int err_irq;
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ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
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return container_of(port, struct ltq_uart_port, port);
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lqasc_stop_tx(struct uart_port *port)
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lqasc_start_tx(struct uart_port *port)
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spin_lock_irqsave(<q_asc_lock, flags);
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lqasc_tx_chars(port);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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lqasc_stop_rx(struct uart_port *port)
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ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
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lqasc_enable_ms(struct uart_port *port)
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lqasc_rx_chars(struct uart_port *port)
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struct tty_struct *tty = tty_port_tty_get(&port->state->port);
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unsigned int ch = 0, rsr = 0, fifocnt;
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dev_dbg(port->dev, "%s:tty is busy now", __func__);
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ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
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u8 flag = TTY_NORMAL;
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ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
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rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
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& ASCSTATE_ANY) | UART_DUMMY_UER_RX;
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tty_flip_buffer_push(tty);
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* Note that the error handling code is
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* out of the main execution path
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if (rsr & ASCSTATE_ANY) {
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if (rsr & ASCSTATE_PE) {
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port->icount.parity++;
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ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
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port->membase + LTQ_ASC_WHBSTATE);
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} else if (rsr & ASCSTATE_FE) {
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port->icount.frame++;
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ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
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port->membase + LTQ_ASC_WHBSTATE);
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if (rsr & ASCSTATE_ROE) {
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port->icount.overrun++;
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ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
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port->membase + LTQ_ASC_WHBSTATE);
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rsr &= port->read_status_mask;
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if (rsr & ASCSTATE_PE)
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else if (rsr & ASCSTATE_FE)
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if ((rsr & port->ignore_status_mask) == 0)
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tty_insert_flip_char(tty, ch, flag);
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if (rsr & ASCSTATE_ROE)
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* Overrun is special, since it's reported
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* immediately, and doesn't affect the current
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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tty_flip_buffer_push(tty);
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lqasc_tx_chars(struct uart_port *port)
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_tx_stopped(port)) {
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while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
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ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
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ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
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if (uart_circ_empty(xmit))
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ltq_w8(port->state->xmit.buf[port->state->xmit.tail],
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port->membase + LTQ_ASC_TBUF);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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lqasc_tx_int(int irq, void *_port)
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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lqasc_start_tx(port);
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lqasc_err_int(int irq, void *_port)
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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/* clear any pending interrupts */
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ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
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ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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lqasc_rx_int(int irq, void *_port)
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
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lqasc_rx_chars(port);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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lqasc_tx_empty(struct uart_port *port)
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status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
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return status ? 0 : TIOCSER_TEMT;
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lqasc_get_mctrl(struct uart_port *port)
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return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
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lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
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lqasc_break_ctl(struct uart_port *port, int break_state)
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lqasc_startup(struct uart_port *port)
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struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
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port->uartclk = clk_get_rate(ltq_port->clk);
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ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
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port->membase + LTQ_ASC_CLC);
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ltq_w32(0, port->membase + LTQ_ASC_PISEL);
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((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
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ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
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port->membase + LTQ_ASC_TXFCON);
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((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
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| ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
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port->membase + LTQ_ASC_RXFCON);
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/* make sure other settings are written to hardware before
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* setting enable bits
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ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
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ASCCON_ROEN, port->membase + LTQ_ASC_CON);
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retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
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pr_err("failed to request lqasc_tx_int\n");
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retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
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pr_err("failed to request lqasc_rx_int\n");
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retval = request_irq(ltq_port->err_irq, lqasc_err_int,
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pr_err("failed to request lqasc_err_int\n");
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ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
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port->membase + LTQ_ASC_IRNREN);
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free_irq(ltq_port->rx_irq, port);
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free_irq(ltq_port->tx_irq, port);
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lqasc_shutdown(struct uart_port *port)
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struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
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free_irq(ltq_port->tx_irq, port);
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free_irq(ltq_port->rx_irq, port);
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free_irq(ltq_port->err_irq, port);
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ltq_w32(0, port->membase + LTQ_ASC_CON);
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ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
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port->membase + LTQ_ASC_RXFCON);
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ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
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port->membase + LTQ_ASC_TXFCON);
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lqasc_set_termios(struct uart_port *port,
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struct ktermios *new, struct ktermios *old)
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unsigned int divisor;
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unsigned int con = 0;
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cflag = new->c_cflag;
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iflag = new->c_iflag;
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switch (cflag & CSIZE) {
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con = ASCCON_M_7ASYNC;
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new->c_cflag &= ~ CSIZE;
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con = ASCCON_M_8ASYNC;
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cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
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if (cflag & PARENB) {
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if (!(cflag & PARODD))
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port->read_status_mask = ASCSTATE_ROE;
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port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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port->ignore_status_mask = 0;
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port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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if (iflag & IGNBRK) {
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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port->ignore_status_mask |= ASCSTATE_ROE;
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if ((cflag & CREAD) == 0)
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port->ignore_status_mask |= UART_DUMMY_UER_RX;
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/* set error signals - framing, parity and overrun, enable receiver */
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con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
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spin_lock_irqsave(<q_asc_lock, flags);
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ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
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/* Set baud rate - take a divider of 2 into account */
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baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
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divisor = uart_get_divisor(port, baud);
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divisor = divisor / 2 - 1;
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/* disable the baudrate generator */
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ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
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/* make sure the fractional divider is off */
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ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
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/* set up to use divisor of 2 */
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ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
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/* now we can write the new baudrate into the register */
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ltq_w32(divisor, port->membase + LTQ_ASC_BG);
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/* turn the baudrate generator back on */
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ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
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ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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/* Don't rewrite B0 */
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if (tty_termios_baud_rate(new))
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tty_termios_encode_baud_rate(new, baud, baud);
484
uart_update_timeout(port, cflag, baud);
488
lqasc_type(struct uart_port *port)
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if (port->type == PORT_LTQ_ASC)
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lqasc_release_port(struct uart_port *port)
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if (port->flags & UPF_IOREMAP) {
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iounmap(port->membase);
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port->membase = NULL;
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lqasc_request_port(struct uart_port *port)
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struct platform_device *pdev = to_platform_device(port->dev);
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struct resource *res;
512
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dev_err(&pdev->dev, "cannot obtain I/O memory region");
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size = resource_size(res);
519
res = devm_request_mem_region(&pdev->dev, res->start,
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size, dev_name(&pdev->dev));
522
dev_err(&pdev->dev, "cannot request I/O memory region");
526
if (port->flags & UPF_IOREMAP) {
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port->membase = devm_ioremap_nocache(&pdev->dev,
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port->mapbase, size);
529
if (port->membase == NULL)
536
lqasc_config_port(struct uart_port *port, int flags)
538
if (flags & UART_CONFIG_TYPE) {
539
port->type = PORT_LTQ_ASC;
540
lqasc_request_port(port);
545
lqasc_verify_port(struct uart_port *port,
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struct serial_struct *ser)
549
if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
551
if (ser->irq < 0 || ser->irq >= NR_IRQS)
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if (ser->baud_base < 9600)
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static struct uart_ops lqasc_pops = {
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.tx_empty = lqasc_tx_empty,
560
.set_mctrl = lqasc_set_mctrl,
561
.get_mctrl = lqasc_get_mctrl,
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.stop_tx = lqasc_stop_tx,
563
.start_tx = lqasc_start_tx,
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.stop_rx = lqasc_stop_rx,
565
.enable_ms = lqasc_enable_ms,
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.break_ctl = lqasc_break_ctl,
567
.startup = lqasc_startup,
568
.shutdown = lqasc_shutdown,
569
.set_termios = lqasc_set_termios,
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.release_port = lqasc_release_port,
572
.request_port = lqasc_request_port,
573
.config_port = lqasc_config_port,
574
.verify_port = lqasc_verify_port,
578
lqasc_console_putchar(struct uart_port *port, int ch)
586
fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT)
587
& ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
588
} while (fifofree == 0);
589
ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
594
lqasc_console_write(struct console *co, const char *s, u_int count)
596
struct ltq_uart_port *ltq_port;
597
struct uart_port *port;
600
if (co->index >= MAXPORTS)
603
ltq_port = lqasc_port[co->index];
607
port = <q_port->port;
609
spin_lock_irqsave(<q_asc_lock, flags);
610
uart_console_write(port, s, count, lqasc_console_putchar);
611
spin_unlock_irqrestore(<q_asc_lock, flags);
615
lqasc_console_setup(struct console *co, char *options)
617
struct ltq_uart_port *ltq_port;
618
struct uart_port *port;
624
if (co->index >= MAXPORTS)
627
ltq_port = lqasc_port[co->index];
631
port = <q_port->port;
633
port->uartclk = clk_get_rate(ltq_port->clk);
636
uart_parse_options(options, &baud, &parity, &bits, &flow);
637
return uart_set_options(port, co, baud, parity, bits, flow);
640
static struct console lqasc_console = {
642
.write = lqasc_console_write,
643
.device = uart_console_device,
644
.setup = lqasc_console_setup,
645
.flags = CON_PRINTBUFFER,
651
lqasc_console_init(void)
653
register_console(&lqasc_console);
656
console_initcall(lqasc_console_init);
658
static struct uart_driver lqasc_reg = {
659
.owner = THIS_MODULE,
660
.driver_name = DRVNAME,
661
.dev_name = "ttyLTQ",
665
.cons = &lqasc_console,
669
lqasc_probe(struct platform_device *pdev)
671
struct ltq_uart_port *ltq_port;
672
struct uart_port *port;
673
struct resource *mmres, *irqres;
674
int tx_irq, rx_irq, err_irq;
678
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
679
irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
680
if (!mmres || !irqres)
683
if (pdev->id >= MAXPORTS)
686
if (lqasc_port[pdev->id] != NULL)
689
clk = clk_get(&pdev->dev, "fpi");
691
pr_err("failed to get fpi clk\n");
695
tx_irq = platform_get_irq_byname(pdev, "tx");
696
rx_irq = platform_get_irq_byname(pdev, "rx");
697
err_irq = platform_get_irq_byname(pdev, "err");
698
if ((tx_irq < 0) | (rx_irq < 0) | (err_irq < 0))
701
ltq_port = kzalloc(sizeof(struct ltq_uart_port), GFP_KERNEL);
705
port = <q_port->port;
707
port->iotype = SERIAL_IO_MEM;
708
port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP;
709
port->ops = &lqasc_pops;
711
port->type = PORT_LTQ_ASC,
712
port->line = pdev->id;
713
port->dev = &pdev->dev;
715
port->irq = tx_irq; /* unused, just to be backward-compatibe */
716
port->mapbase = mmres->start;
720
ltq_port->tx_irq = tx_irq;
721
ltq_port->rx_irq = rx_irq;
722
ltq_port->err_irq = err_irq;
724
lqasc_port[pdev->id] = ltq_port;
725
platform_set_drvdata(pdev, ltq_port);
727
ret = uart_add_one_port(&lqasc_reg, port);
732
static struct platform_driver lqasc_driver = {
735
.owner = THIS_MODULE,
744
ret = uart_register_driver(&lqasc_reg);
748
ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
750
uart_unregister_driver(&lqasc_reg);
755
module_init(init_lqasc);
757
MODULE_DESCRIPTION("Lantiq serial port driver");
758
MODULE_LICENSE("GPL");