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* OMAP1 internal LCD controller
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* Copyright (C) 2004 Nokia Corporation
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* Author: Imre Deak <imre.deak@nokia.com>
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/dma-mapping.h>
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#include <linux/vmalloc.h>
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#include <linux/clk.h>
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#include <linux/gfp.h>
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#include <mach/lcdc.h>
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#include <asm/mach-types.h>
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#define MODULE_NAME "lcdc"
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#define MAX_PALETTE_SIZE PAGE_SIZE
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OMAP_LCDC_LOAD_PALETTE,
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OMAP_LCDC_LOAD_PALETTE_AND_FRAME
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static struct omap_lcd_controller {
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enum omapfb_update_mode update_mode;
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unsigned long frame_offset;
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enum omapfb_color_format color_mode;
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dma_addr_t palette_phys;
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unsigned int irq_mask;
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struct completion last_frame_complete;
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struct completion palette_load_complete;
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struct omapfb_device *fbdev;
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void (*dma_callback)(void *data);
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void *dma_callback_data;
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unsigned long vram_size;
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static void inline enable_irqs(int mask)
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lcdc.irq_mask |= mask;
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static void inline disable_irqs(int mask)
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lcdc.irq_mask &= ~mask;
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static void set_load_mode(enum lcdc_load_mode mode)
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l = omap_readl(OMAP_LCDC_CONTROL);
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case OMAP_LCDC_LOAD_PALETTE:
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case OMAP_LCDC_LOAD_FRAME:
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case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
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omap_writel(l, OMAP_LCDC_CONTROL);
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static void enable_controller(void)
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l = omap_readl(OMAP_LCDC_CONTROL);
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l |= OMAP_LCDC_CTRL_LCD_EN;
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l &= ~OMAP_LCDC_IRQ_MASK;
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l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
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omap_writel(l, OMAP_LCDC_CONTROL);
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static void disable_controller_async(void)
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l = omap_readl(OMAP_LCDC_CONTROL);
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mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
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* Preserve the DONE mask, since we still want to get the
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* final DONE irq. It will be disabled in the IRQ handler.
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mask &= ~OMAP_LCDC_IRQ_DONE;
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omap_writel(l, OMAP_LCDC_CONTROL);
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static void disable_controller(void)
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init_completion(&lcdc.last_frame_complete);
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disable_controller_async();
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if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
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msecs_to_jiffies(500)))
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dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
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static void reset_controller(u32 status)
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static unsigned long reset_count;
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static unsigned long last_jiffies;
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disable_controller_async();
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if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
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dev_err(lcdc.fbdev->dev,
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"resetting (status %#010x,reset count %lu)\n",
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status, reset_count);
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last_jiffies = jiffies;
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if (reset_count < 100) {
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dev_err(lcdc.fbdev->dev,
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"too many reset attempts, giving up.\n");
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* Configure the LCD DMA according to the current mode specified by parameters
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* in lcdc.fbdev and fbdev->var.
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static void setup_lcd_dma(void)
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static const int dma_elem_type[] = {
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OMAP_DMA_DATA_TYPE_S8,
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OMAP_DMA_DATA_TYPE_S16,
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OMAP_DMA_DATA_TYPE_S32,
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struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
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struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
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int esize, xelem, yelem;
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src = lcdc.vram_phys + lcdc.frame_offset;
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switch (var->rotate) {
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if (plane->info.mirror || (src & 3) ||
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lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
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xelem = lcdc.xres * lcdc.bpp / 8 / esize;
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if (cpu_is_omap15xx()) {
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xelem = lcdc.yres * lcdc.bpp / 16;
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dev_dbg(lcdc.fbdev->dev,
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"setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
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src, esize, xelem, yelem);
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omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
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if (!cpu_is_omap15xx()) {
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* YUV support is only for external mode when we have the
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* YUV window embedded in a 16bpp frame buffer.
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if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
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/* Set virtual xres elem size */
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omap_set_lcd_dma_b1_vxres(
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lcdc.screen_width * bpp / 8 / esize);
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/* Setup transformations */
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omap_set_lcd_dma_b1_rotation(var->rotate);
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omap_set_lcd_dma_b1_mirror(plane->info.mirror);
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omap_setup_lcd_dma();
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static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
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status = omap_readl(OMAP_LCDC_STATUS);
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if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
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reset_controller(status);
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if (status & OMAP_LCDC_STAT_DONE) {
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* Disable IRQ_DONE. The status bit will be cleared
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* only when the controller is reenabled and we don't
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* want to get more interrupts.
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l = omap_readl(OMAP_LCDC_CONTROL);
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l &= ~OMAP_LCDC_IRQ_DONE;
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omap_writel(l, OMAP_LCDC_CONTROL);
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complete(&lcdc.last_frame_complete);
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if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
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disable_controller_async();
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complete(&lcdc.palette_load_complete);
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* Clear these interrupt status bits.
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* Sync_lost, FUF bits were cleared by disabling the LCD controller
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* LOADED_PALETTE can be cleared this way only in palette only
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* load mode. In other load modes it's cleared by disabling the
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status &= ~(OMAP_LCDC_STAT_VSYNC |
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OMAP_LCDC_STAT_LOADED_PALETTE |
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OMAP_LCDC_STAT_LINE_INT);
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omap_writel(status, OMAP_LCDC_STATUS);
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* Change to a new video mode. We defer this to a later time to avoid any
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* flicker and not to mess up the current LCD DMA context. For this we disable
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* the LCD controller, which will generate a DONE irq after the last frame has
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* been transferred. Then it'll be safe to reconfigure both the LCD controller
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* as well as the LCD DMA.
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static int omap_lcdc_setup_plane(int plane, int channel_out,
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unsigned long offset, int screen_width,
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int pos_x, int pos_y, int width, int height,
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struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
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struct lcd_panel *panel = lcdc.fbdev->panel;
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if (var->rotate == 0) {
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rot_x = panel->x_res;
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rot_y = panel->y_res;
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rot_x = panel->y_res;
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rot_y = panel->x_res;
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if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
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width > rot_x || height > rot_y) {
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dev_dbg(lcdc.fbdev->dev,
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"invalid plane params plane %d pos_x %d pos_y %d "
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"w %d h %d\n", plane, pos_x, pos_y, width, height);
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lcdc.frame_offset = offset;
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lcdc.screen_width = screen_width;
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lcdc.color_mode = color_mode;
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switch (color_mode) {
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case OMAPFB_COLOR_CLUT_8BPP:
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lcdc.palette_code = 0x3000;
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lcdc.palette_size = 512;
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case OMAPFB_COLOR_RGB565:
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lcdc.palette_code = 0x4000;
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lcdc.palette_size = 32;
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case OMAPFB_COLOR_RGB444:
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lcdc.palette_code = 0x4000;
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lcdc.palette_size = 32;
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case OMAPFB_COLOR_YUV420:
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case OMAPFB_COLOR_YUV422:
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/* FIXME: other BPPs.
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* bpp1: code 0, size 256
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* bpp2: code 0x1000 size 256
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* bpp4: code 0x2000 size 256
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* bpp12: code 0x4000 size 32
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dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
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if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
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disable_controller();
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static int omap_lcdc_enable_plane(int plane, int enable)
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dev_dbg(lcdc.fbdev->dev,
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"plane %d enable %d update_mode %d ext_mode %d\n",
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plane, enable, lcdc.update_mode, lcdc.ext_mode);
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if (plane != OMAPFB_PLANE_GFX)
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* Configure the LCD DMA for a palette load operation and do the palette
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* downloading synchronously. We don't use the frame+palette load mode of
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* the controller, since the palette can always be downloaded separately.
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static void load_palette(void)
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palette = (u16 *)lcdc.palette_virt;
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*(u16 *)palette &= 0x0fff;
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*(u16 *)palette |= lcdc.palette_code;
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omap_set_lcd_dma_b1(lcdc.palette_phys,
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lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
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omap_set_lcd_dma_single_transfer(1);
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omap_setup_lcd_dma();
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init_completion(&lcdc.palette_load_complete);
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enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
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set_load_mode(OMAP_LCDC_LOAD_PALETTE);
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if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
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msecs_to_jiffies(500)))
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dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
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/* The controller gets disabled in the irq handler */
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disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
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omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
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/* Used only in internal controller mode */
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static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
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u16 transp, int update_hw_pal)
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if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
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palette = (u16 *)lcdc.palette_virt;
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palette[regno] &= ~0x0fff;
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palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
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disable_controller();
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set_load_mode(OMAP_LCDC_LOAD_FRAME);
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static void calc_ck_div(int is_tft, int pck, int *pck_div)
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lck = clk_get_rate(lcdc.lcd_ck);
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*pck_div = (lck + pck - 1) / pck;
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*pck_div = max(2, *pck_div);
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*pck_div = max(3, *pck_div);
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if (*pck_div > 255) {
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/* FIXME: try to adjust logic clock divider as well */
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dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
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static void inline setup_regs(void)
473
struct lcd_panel *panel = lcdc.fbdev->panel;
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int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
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l = omap_readl(OMAP_LCDC_CONTROL);
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l &= ~OMAP_LCDC_CTRL_LCD_TFT;
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l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
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#ifdef CONFIG_MACH_OMAP_PALMTE
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/* FIXME:if (machine_is_omap_palmte()) { */
483
/* PalmTE uses alternate TFT setting in 8BPP mode */
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l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
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omap_writel(l, OMAP_LCDC_CONTROL);
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l = omap_readl(OMAP_LCDC_TIMING2);
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l &= ~(((1 << 6) - 1) << 20);
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l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
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omap_writel(l, OMAP_LCDC_TIMING2);
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l = panel->x_res - 1;
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l |= (panel->hsw - 1) << 10;
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l |= (panel->hfp - 1) << 16;
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l |= (panel->hbp - 1) << 24;
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omap_writel(l, OMAP_LCDC_TIMING0);
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l = panel->y_res - 1;
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l |= (panel->vsw - 1) << 10;
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l |= panel->vfp << 16;
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l |= panel->vbp << 24;
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omap_writel(l, OMAP_LCDC_TIMING1);
506
l = omap_readl(OMAP_LCDC_TIMING2);
509
lck = clk_get_rate(lcdc.lcd_ck);
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calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
514
dev_warn(lcdc.fbdev->dev,
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"Pixel clock divider value is obsolete.\n"
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"Try to set pixel_clock to %lu and pcd to 0 "
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"in drivers/video/omap/lcd_%s.c and submit a patch.\n",
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lck / panel->pcd / 1000, panel->name);
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l |= panel->acb << 8;
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omap_writel(l, OMAP_LCDC_TIMING2);
526
/* update panel info with the exact clock */
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panel->pixel_clock = lck / pcd / 1000;
531
* Configure the LCD controller, download the color palette and start a looped
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* DMA transfer of the frame image data. Called only in internal
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static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
539
if (mode != lcdc.update_mode) {
541
case OMAPFB_AUTO_UPDATE:
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/* Setup and start LCD DMA */
548
set_load_mode(OMAP_LCDC_LOAD_FRAME);
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enable_irqs(OMAP_LCDC_IRQ_DONE);
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/* This will start the actual DMA transfer */
552
lcdc.update_mode = mode;
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case OMAPFB_UPDATE_DISABLED:
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disable_controller();
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lcdc.update_mode = mode;
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static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
569
return lcdc.update_mode;
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/* PM code called only in internal controller mode */
573
static void omap_lcdc_suspend(void)
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omap_lcdc_set_update_mode(OMAPFB_UPDATE_DISABLED);
578
static void omap_lcdc_resume(void)
580
omap_lcdc_set_update_mode(OMAPFB_AUTO_UPDATE);
583
static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
588
int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
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BUG_ON(callback == NULL);
592
if (lcdc.dma_callback)
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lcdc.dma_callback = callback;
596
lcdc.dma_callback_data = data;
600
EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
602
void omap_lcdc_free_dma_callback(void)
604
lcdc.dma_callback = NULL;
606
EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
608
static void lcdc_dma_handler(u16 status, void *data)
610
if (lcdc.dma_callback)
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lcdc.dma_callback(lcdc.dma_callback_data);
614
static int mmap_kern(void)
616
struct vm_struct *kvma;
617
struct vm_area_struct vma;
621
kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP);
623
dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n");
626
vma.vm_mm = &init_mm;
628
vaddr = (unsigned long)kvma->addr;
629
vma.vm_start = vaddr;
630
vma.vm_end = vaddr + lcdc.vram_size;
632
pgprot = pgprot_writecombine(pgprot_kernel);
633
if (io_remap_pfn_range(&vma, vaddr,
634
lcdc.vram_phys >> PAGE_SHIFT,
635
lcdc.vram_size, pgprot) < 0) {
636
dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n");
640
lcdc.vram_virt = (void *)vaddr;
645
static void unmap_kern(void)
647
vunmap(lcdc.vram_virt);
650
static int alloc_palette_ram(void)
652
lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
653
MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
654
if (lcdc.palette_virt == NULL) {
655
dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
658
memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
663
static void free_palette_ram(void)
665
dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
666
lcdc.palette_virt, lcdc.palette_phys);
669
static int alloc_fbmem(struct omapfb_mem_region *region)
673
struct lcd_panel *panel = lcdc.fbdev->panel;
678
frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
679
if (region->size > frame_size)
680
frame_size = region->size;
681
lcdc.vram_size = frame_size;
682
lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
683
lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
684
if (lcdc.vram_virt == NULL) {
685
dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
688
region->size = frame_size;
689
region->paddr = lcdc.vram_phys;
690
region->vaddr = lcdc.vram_virt;
693
memset(lcdc.vram_virt, 0, lcdc.vram_size);
698
static void free_fbmem(void)
700
dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
701
lcdc.vram_virt, lcdc.vram_phys);
704
static int setup_fbmem(struct omapfb_mem_desc *req_md)
708
if (!req_md->region_cnt) {
709
dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
713
if (req_md->region_cnt > 1) {
714
dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
715
req_md->region_cnt = 1;
718
if (req_md->region[0].paddr == 0) {
719
lcdc.fbmem_allocated = 1;
720
if ((r = alloc_fbmem(&req_md->region[0])) < 0)
725
lcdc.vram_phys = req_md->region[0].paddr;
726
lcdc.vram_size = req_md->region[0].size;
728
if ((r = mmap_kern()) < 0)
731
dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n",
732
lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt);
737
static void cleanup_fbmem(void)
739
if (lcdc.fbmem_allocated)
745
static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
746
struct omapfb_mem_desc *req_vram)
756
lcdc.ext_mode = ext_mode;
759
omap_writel(l, OMAP_LCDC_CONTROL);
762
* According to errata some platforms have a clock rate limitiation
764
lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
765
if (IS_ERR(lcdc.lcd_ck)) {
766
dev_err(fbdev->dev, "unable to access LCD clock\n");
767
r = PTR_ERR(lcdc.lcd_ck);
771
tc_ck = clk_get(fbdev->dev, "tc_ck");
773
dev_err(fbdev->dev, "unable to access TC clock\n");
778
rate = clk_get_rate(tc_ck);
781
if (machine_is_ams_delta())
783
if (machine_is_omap_h3())
785
r = clk_set_rate(lcdc.lcd_ck, rate);
787
dev_err(fbdev->dev, "failed to adjust LCD rate\n");
790
clk_enable(lcdc.lcd_ck);
792
r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
794
dev_err(fbdev->dev, "unable to get IRQ\n");
798
r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
800
dev_err(fbdev->dev, "unable to get LCD DMA\n");
804
omap_set_lcd_dma_single_transfer(ext_mode);
805
omap_set_lcd_dma_ext_controller(ext_mode);
808
if ((r = alloc_palette_ram()) < 0)
811
if ((r = setup_fbmem(req_vram)) < 0)
814
pr_info("omapfb: LCDC initialized\n");
823
free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
825
clk_disable(lcdc.lcd_ck);
827
clk_put(lcdc.lcd_ck);
832
static void omap_lcdc_cleanup(void)
838
free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
839
clk_disable(lcdc.lcd_ck);
840
clk_put(lcdc.lcd_ck);
843
const struct lcd_ctrl omap1_int_ctrl = {
845
.init = omap_lcdc_init,
846
.cleanup = omap_lcdc_cleanup,
847
.get_caps = omap_lcdc_get_caps,
848
.set_update_mode = omap_lcdc_set_update_mode,
849
.get_update_mode = omap_lcdc_get_update_mode,
850
.update_window = NULL,
851
.suspend = omap_lcdc_suspend,
852
.resume = omap_lcdc_resume,
853
.setup_plane = omap_lcdc_setup_plane,
854
.enable_plane = omap_lcdc_enable_plane,
855
.setcolreg = omap_lcdc_setcolreg,