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/***************************************************************************
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* Copyright (c) 2005-2009, Broadcom Corporation.
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* Name: crystalhd_hw . h
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* BCM70012 Linux driver hardware layer.
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**********************************************************************
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* This file is part of the crystalhd device driver.
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* This driver is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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* This driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this driver. If not, see <http://www.gnu.org/licenses/>.
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**********************************************************************/
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#ifndef _CRYSTALHD_HW_H_
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#define _CRYSTALHD_HW_H_
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#include "crystalhd_misc.h"
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#include "crystalhd_fw_if.h"
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#define DMA_ENGINE_CNT 2
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#define MAX_PIB_Q_DEPTH 64
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#define MIN_PIB_Q_DEPTH 2
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#define WR_POINTER_OFF 4
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#define ASPM_L1_ENABLE (BC_BIT(27))
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/*************************************************
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7412 Decoder Registers.
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**************************************************/
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#define FW_CMD_BUFF_SZ 64
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#define TS_Host2CpuSnd 0x00000100
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#define Hst2CpuMbx1 0x00100F00
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#define Cpu2HstMbx1 0x00100F04
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#define MbxStat1 0x00100F08
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#define Stream2Host_Intr_Sts 0x00100F24
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#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */
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/* TS input status register */
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#define TS_StreamAFIFOStatus 0x0010044C
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#define TS_StreamBFIFOStatus 0x0010084C
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/*UART Selection definitions*/
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#define UartSelectA 0x00100300
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#define UartSelectB 0x00100304
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#define BSVS_UART_DEC_NONE 0x00
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#define BSVS_UART_DEC_OUTER 0x01
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#define BSVS_UART_DEC_INNER 0x02
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#define BSVS_UART_STREAM 0x03
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#define REG_DecCA_RegCinCTL 0xa00
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#define REG_DecCA_RegCinBase 0xa0c
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#define REG_DecCA_RegCinEnd 0xa10
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#define REG_DecCA_RegCinWrPtr 0xa04
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#define REG_DecCA_RegCinRdPtr 0xa08
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#define REG_Dec_TsUser0Base 0x100864
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#define REG_Dec_TsUser0Rdptr 0x100868
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#define REG_Dec_TsUser0Wrptr 0x10086C
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#define REG_Dec_TsUser0End 0x100874
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#define REG_Dec_TsAudCDB2Base 0x10036c
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#define REG_Dec_TsAudCDB2Rdptr 0x100378
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#define REG_Dec_TsAudCDB2Wrptr 0x100374
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#define REG_Dec_TsAudCDB2End 0x100370
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/* DRAM bringup Registers */
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#define SDRAM_PARAM 0x00040804
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#define SDRAM_PRECHARGE 0x000408B0
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#define SDRAM_EXT_MODE 0x000408A4
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#define SDRAM_MODE 0x000408A0
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#define SDRAM_REFRESH 0x00040890
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#define SDRAM_REF_PARAM 0x00040808
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#define DecHt_PllACtl 0x34000C
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#define DecHt_PllBCtl 0x340010
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#define DecHt_PllCCtl 0x340014
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#define DecHt_PllDCtl 0x340034
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#define DecHt_PllECtl 0x340038
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#define AUD_DSP_MISC_SOFT_RESET 0x00240104
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#define AIO_MISC_PLL_RESET 0x0026000C
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#define PCIE_CLK_REQ_REG 0xDC
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#define PCI_CLK_REQ_ENABLE (BC_BIT(8))
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/*************************************************
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F/W Copy engine definitions..
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**************************************************/
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#define BC_FWIMG_ST_ADDR 0x00000000
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/* FIXME: jarod: there's a kernel function that'll do this for us... */
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#define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n)))
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#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))
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#define DecHt_HostSwReset 0x340000
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#define BC_DRAM_FW_CFG_ADDR 0x001c2000
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union intr_mask_reg {
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uint32_t mask_tx_done:1;
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uint32_t mask_tx_err:1;
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uint32_t mask_rx_done:1;
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uint32_t mask_rx_err:1;
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uint32_t mask_pcie_err:1;
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uint32_t mask_pcie_rbusmast_err:1;
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uint32_t mask_pcie_rgr_bridge:1;
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uint32_t reserved:25;
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union link_misc_perst_deco_ctrl {
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uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
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uint32_t reserved0:3; /* Reserved.No Effect*/
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uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/
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uint32_t reserved1:27; /* Reseved. No Effect*/
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union link_misc_perst_clk_ctrl {
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uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */
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uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */
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uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set
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to select an alternate clock before setting this bit.*/
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uint32_t reserved0:5; /* Reserved */
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uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */
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uint32_t pll_div:4; /* This setting controls the divider for the PLL. */
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uint32_t reserved1:12; /* Reserved */
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union link_misc_perst_decoder_ctrl {
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uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
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uint32_t res0:3; /* Reserved.No Effect*/
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uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/
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uint32_t res1:27; /* Reseved. No Effect */
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union desc_low_addr_reg {
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uint32_t list_valid:1;
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uint32_t low_addr:27;
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struct dma_descriptor { /* 8 32-bit values */
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uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */
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uint32_t res0:4; /* bits 28-31: Reserved */
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uint32_t buff_addr_low; /* 1 buffer address low */
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uint32_t buff_addr_high; /* 2 buffer address high */
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uint32_t res2:2; /* 0-1 - Reserved */
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uint32_t xfer_size:23; /* 2-24 = Xfer size in words */
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uint32_t res3:6; /* 25-30 reserved */
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uint32_t intr_enable:1; /* 31 - Interrupt After this desc */
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uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */
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uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */
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uint32_t res4:25; /* 3 - 27 Reserved bits */
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uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */
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uint32_t dma_dir:1; /* 30 bit DMA Direction */
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uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */
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uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */
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uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */
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uint32_t res8; /* Last 32bits reserved */
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* We will allocate the memory in 4K pages
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* the linked list will be a list of 32 byte descriptors.
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* The virtual address will determine what should be freed.
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struct dma_desc_mem {
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struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */
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dma_addr_t phy_addr; /* physical address of each DMA desc */
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struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */
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rx_waiting_y_intr = 0x00000001,
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rx_y_error = 0x00000004,
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/* RX-UV Bits 8:16 */
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rx_waiting_uv_intr = 0x0000100,
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rx_uv_error = 0x0000400,
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rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr),
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rx_sts_error = (rx_y_error|rx_uv_error),
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rx_y_mask = 0x000000FF,
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rx_uv_mask = 0x0000FF00,
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struct dma_desc_mem desc_mem;
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hw_comp_callback call_back;
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struct crystalhd_dio_req *dio_req;
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wait_queue_head_t *cb_event;
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struct crystalhd_rx_dma_pkt {
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struct dma_desc_mem desc_mem;
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struct crystalhd_dio_req *dio_req;
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struct BC_PIC_INFO_BLOCK pib;
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dma_addr_t uv_phy_addr;
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struct crystalhd_rx_dma_pkt *next;
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struct crystalhd_hw_stats {
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uint32_t freeq_count;
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uint32_t num_interrupts;
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uint32_t dev_interrupts;
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struct crystalhd_hw {
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struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT];
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uint32_t tx_ioq_tag_seed;
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uint32_t tx_list_post_index;
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struct crystalhd_rx_dma_pkt *rx_pkt_pool_head;
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uint32_t rx_pkt_tag_seed;
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wait_queue_head_t *pfw_cmd_event;
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uint32_t pib_del_Q_addr;
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uint32_t pib_rel_Q_addr;
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struct crystalhd_dioq *tx_freeq;
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struct crystalhd_dioq *tx_actq;
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/* Rx DMA Engine Specific Locks */
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uint32_t rx_list_post_index;
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enum list_sts rx_list_sts[DMA_ENGINE_CNT];
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struct crystalhd_dioq *rx_rdyq;
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struct crystalhd_dioq *rx_freeq;
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struct crystalhd_dioq *rx_actq;
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uint32_t stop_pending;
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struct crystalhd_hw_stats stats;
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/* Core clock in MHz */
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uint32_t core_clock_mhz;
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/* Clock defines for power control */
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#define CLOCK_PRESET 175
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/* DMA engine register BIT mask wrappers.. */
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#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK
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#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \
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INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \
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INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \
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INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \
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INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \
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INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \
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INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \
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INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK)
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#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
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MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
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MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
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MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
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#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
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MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
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MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
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MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
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#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
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MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
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MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
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MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
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#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
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MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
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MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
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MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
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/**** API Exposed to the other layers ****/
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enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp,
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void *buffer, uint32_t sz);
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enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, struct BC_FW_CMD *fw_cmd);
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bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw);
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enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *);
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enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *);
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enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *);
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enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *);
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enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq,
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hw_comp_callback call_back,
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wait_queue_head_t *cb_event,
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uint32_t *list_id, uint8_t data_flags);
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enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw);
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enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw);
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enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw);
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enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id);
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enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
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struct crystalhd_dio_req *ioreq, bool en_post);
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enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,
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struct BC_PIC_INFO_BLOCK *pib,
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struct crystalhd_dio_req **ioreq);
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enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw);
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enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw);
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void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats);
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/* API to program the core clock on the decoder */
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enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *);