1
/* $Id: isac.c,v 1.31.2.3 2004/01/13 14:31:25 keil Exp $
3
* ISAC specific routines
6
* Copyright by Karsten Keil <keil@isdn4linux.de>
8
* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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* For changes and modifications please read
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* Documentation/isdn/HiSax.cert
20
#include <linux/interrupt.h>
21
#include <linux/slab.h>
22
#include <linux/init.h>
24
#define DBUSY_TIMER_VALUE 80
27
static char *ISACVer[] __devinitdata =
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{"2086/2186 V1.1", "2085 B1", "2085 B2",
31
void __devinit ISACVersion(struct IsdnCardState *cs, char *s)
35
val = cs->readisac(cs, ISAC_RBCH);
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printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);
40
ph_command(struct IsdnCardState *cs, unsigned int command)
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if (cs->debug & L1_DEB_ISAC)
43
debugl1(cs, "ph_command %x", command);
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cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3);
49
isac_new_ph(struct IsdnCardState *cs)
51
switch (cs->dc.isac.ph_state) {
54
ph_command(cs, ISAC_CMD_DUI);
55
l1_msg(cs, HW_RESET | INDICATION, NULL);
58
l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
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l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
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l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
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l1_msg(cs, HW_RSYNC | INDICATION, NULL);
70
l1_msg(cs, HW_INFO2 | INDICATION, NULL);
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l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
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l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
84
isac_bh(struct work_struct *work)
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struct IsdnCardState *cs =
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container_of(work, struct IsdnCardState, tqueue);
90
if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
92
debugl1(cs, "D-Channel Busy cleared");
94
while (stptr != NULL) {
95
stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
99
if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
101
if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
102
DChannel_proc_rcv(cs);
103
if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
104
DChannel_proc_xmt(cs);
106
if (!test_bit(HW_ARCOFI, &cs->HW_Flags))
108
if (test_and_clear_bit(D_RX_MON1, &cs->event))
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arcofi_fsm(cs, ARCOFI_RX_END, NULL);
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if (test_and_clear_bit(D_TX_MON1, &cs->event))
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arcofi_fsm(cs, ARCOFI_TX_END, NULL);
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isac_empty_fifo(struct IsdnCardState *cs, int count)
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
121
debugl1(cs, "isac_empty_fifo");
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if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "isac_empty_fifo overrun %d",
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cs->writeisac(cs, ISAC_CMDR, 0x80);
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ptr = cs->rcvbuf + cs->rcvidx;
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cs->readisacfifo(cs, ptr, count);
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cs->writeisac(cs, ISAC_CMDR, 0x80);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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t += sprintf(t, "isac_empty_fifo cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, cs->dlog);
145
isac_fill_fifo(struct IsdnCardState *cs)
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "isac_fill_fifo");
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count = cs->tx_skb->len;
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ptr = cs->tx_skb->data;
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skb_pull(cs->tx_skb, count);
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cs->writeisacfifo(cs, ptr, count);
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cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);
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if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
171
debugl1(cs, "isac_fill_fifo dbusytimer running");
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del_timer(&cs->dbusytimer);
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init_timer(&cs->dbusytimer);
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cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
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add_timer(&cs->dbusytimer);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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t += sprintf(t, "isac_fill_fifo cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, cs->dlog);
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isac_interrupt(struct IsdnCardState *cs, u_char val)
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ISAC interrupt %x", val);
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if (val & 0x80) { /* RME */
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exval = cs->readisac(cs, ISAC_RSTA);
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if ((exval & 0x70) != 0x20) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC RDO");
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#ifdef ERROR_STATISTIC
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if (!(exval & 0x20)) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC CRC error");
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#ifdef ERROR_STATISTIC
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cs->writeisac(cs, ISAC_CMDR, 0x80);
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count = cs->readisac(cs, ISAC_RBCL) & 0x1f;
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isac_empty_fifo(cs, count);
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if ((count = cs->rcvidx) > 0) {
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if (!(skb = alloc_skb(count, GFP_ATOMIC)))
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printk(KERN_WARNING "HiSax: D receive out of memory\n");
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memcpy(skb_put(skb, count), cs->rcvbuf, count);
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skb_queue_tail(&cs->rq, skb);
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schedule_event(cs, D_RCVBUFREADY);
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if (val & 0x40) { /* RPF */
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isac_empty_fifo(cs, 32);
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if (val & 0x20) { /* RSC */
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC RSC interrupt");
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if (val & 0x10) { /* XPR */
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if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
241
del_timer(&cs->dbusytimer);
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if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
243
schedule_event(cs, D_CLEARBUSY);
245
if (cs->tx_skb->len) {
249
dev_kfree_skb_irq(cs->tx_skb);
254
if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
258
schedule_event(cs, D_XMTBUFREADY);
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if (val & 0x04) { /* CISQ */
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exval = cs->readisac(cs, ISAC_CIR0);
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ISAC CIR0 %02X", exval );
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cs->dc.isac.ph_state = (exval >> 2) & 0xf;
267
if (cs->debug & L1_DEB_ISAC)
268
debugl1(cs, "ph_state change %x", cs->dc.isac.ph_state);
269
schedule_event(cs, D_L1STATECHANGE);
272
exval = cs->readisac(cs, ISAC_CIR1);
273
if (cs->debug & L1_DEB_ISAC)
274
debugl1(cs, "ISAC CIR1 %02X", exval );
277
if (val & 0x02) { /* SIN */
279
if (cs->debug & L1_DEB_WARN)
280
debugl1(cs, "ISAC SIN interrupt");
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if (val & 0x01) { /* EXI */
283
exval = cs->readisac(cs, ISAC_EXIR);
284
if (cs->debug & L1_DEB_WARN)
285
debugl1(cs, "ISAC EXIR %02x", exval);
286
if (exval & 0x80) { /* XMR */
287
debugl1(cs, "ISAC XMR");
288
printk(KERN_WARNING "HiSax: ISAC XMR\n");
290
if (exval & 0x40) { /* XDU */
291
debugl1(cs, "ISAC XDU");
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printk(KERN_WARNING "HiSax: ISAC XDU\n");
293
#ifdef ERROR_STATISTIC
296
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
297
del_timer(&cs->dbusytimer);
298
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
299
schedule_event(cs, D_CLEARBUSY);
300
if (cs->tx_skb) { /* Restart frame */
301
skb_push(cs->tx_skb, cs->tx_cnt);
305
printk(KERN_WARNING "HiSax: ISAC XDU no skb\n");
306
debugl1(cs, "ISAC XDU no skb");
309
if (exval & 0x04) { /* MOS */
310
v1 = cs->readisac(cs, ISAC_MOSR);
311
if (cs->debug & L1_DEB_MONITOR)
312
debugl1(cs, "ISAC MOSR %02x", v1);
315
if (!cs->dc.isac.mon_rx) {
316
if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
317
if (cs->debug & L1_DEB_WARN)
318
debugl1(cs, "ISAC MON RX out of memory!");
319
cs->dc.isac.mocr &= 0xf0;
320
cs->dc.isac.mocr |= 0x0a;
321
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
324
cs->dc.isac.mon_rxp = 0;
326
if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
327
cs->dc.isac.mocr &= 0xf0;
328
cs->dc.isac.mocr |= 0x0a;
329
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
330
cs->dc.isac.mon_rxp = 0;
331
if (cs->debug & L1_DEB_WARN)
332
debugl1(cs, "ISAC MON RX overflow!");
335
cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
336
if (cs->debug & L1_DEB_MONITOR)
337
debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
338
if (cs->dc.isac.mon_rxp == 1) {
339
cs->dc.isac.mocr |= 0x04;
340
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
345
if (!cs->dc.isac.mon_rx) {
346
if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
347
if (cs->debug & L1_DEB_WARN)
348
debugl1(cs, "ISAC MON RX out of memory!");
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cs->dc.isac.mocr &= 0x0f;
350
cs->dc.isac.mocr |= 0xa0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
354
cs->dc.isac.mon_rxp = 0;
356
if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
357
cs->dc.isac.mocr &= 0x0f;
358
cs->dc.isac.mocr |= 0xa0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
360
cs->dc.isac.mon_rxp = 0;
361
if (cs->debug & L1_DEB_WARN)
362
debugl1(cs, "ISAC MON RX overflow!");
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cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
366
if (cs->debug & L1_DEB_MONITOR)
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debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
368
cs->dc.isac.mocr |= 0x40;
369
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
373
cs->dc.isac.mocr &= 0xf0;
374
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
375
cs->dc.isac.mocr |= 0x0a;
376
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
377
schedule_event(cs, D_RX_MON0);
380
cs->dc.isac.mocr &= 0x0f;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
382
cs->dc.isac.mocr |= 0xa0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
384
schedule_event(cs, D_RX_MON1);
387
if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
388
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
390
cs->dc.isac.mocr &= 0xf0;
391
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
392
cs->dc.isac.mocr |= 0x0a;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
394
if (cs->dc.isac.mon_txc &&
395
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
396
schedule_event(cs, D_TX_MON0);
399
if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
400
schedule_event(cs, D_TX_MON0);
403
cs->writeisac(cs, ISAC_MOX0,
404
cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
405
if (cs->debug & L1_DEB_MONITOR)
406
debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
410
if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
411
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
413
cs->dc.isac.mocr &= 0x0f;
414
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
415
cs->dc.isac.mocr |= 0xa0;
416
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
417
if (cs->dc.isac.mon_txc &&
418
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
419
schedule_event(cs, D_TX_MON1);
422
if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
423
schedule_event(cs, D_TX_MON1);
426
cs->writeisac(cs, ISAC_MOX1,
427
cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
428
if (cs->debug & L1_DEB_MONITOR)
429
debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
438
ISAC_l1hw(struct PStack *st, int pr, void *arg)
440
struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
441
struct sk_buff *skb = arg;
446
case (PH_DATA |REQUEST):
447
if (cs->debug & DEB_DLOG_HEX)
448
LogFrame(cs, skb->data, skb->len);
449
if (cs->debug & DEB_DLOG_VERBOSE)
450
dlogframe(cs, skb, 0);
451
spin_lock_irqsave(&cs->lock, flags);
453
skb_queue_tail(&cs->sq, skb);
454
#ifdef L2FRAME_DEBUG /* psa */
455
if (cs->debug & L1_DEB_LAPD)
456
Logl2Frame(cs, skb, "PH_DATA Queued", 0);
461
#ifdef L2FRAME_DEBUG /* psa */
462
if (cs->debug & L1_DEB_LAPD)
463
Logl2Frame(cs, skb, "PH_DATA", 0);
467
spin_unlock_irqrestore(&cs->lock, flags);
469
case (PH_PULL |INDICATION):
470
spin_lock_irqsave(&cs->lock, flags);
472
if (cs->debug & L1_DEB_WARN)
473
debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
474
skb_queue_tail(&cs->sq, skb);
476
if (cs->debug & DEB_DLOG_HEX)
477
LogFrame(cs, skb->data, skb->len);
478
if (cs->debug & DEB_DLOG_VERBOSE)
479
dlogframe(cs, skb, 0);
482
#ifdef L2FRAME_DEBUG /* psa */
483
if (cs->debug & L1_DEB_LAPD)
484
Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
488
spin_unlock_irqrestore(&cs->lock, flags);
490
case (PH_PULL | REQUEST):
491
#ifdef L2FRAME_DEBUG /* psa */
492
if (cs->debug & L1_DEB_LAPD)
493
debugl1(cs, "-> PH_REQUEST_PULL");
496
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
497
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
499
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
501
case (HW_RESET | REQUEST):
502
spin_lock_irqsave(&cs->lock, flags);
503
if ((cs->dc.isac.ph_state == ISAC_IND_EI) ||
504
(cs->dc.isac.ph_state == ISAC_IND_DR) ||
505
(cs->dc.isac.ph_state == ISAC_IND_RS))
506
ph_command(cs, ISAC_CMD_TIM);
508
ph_command(cs, ISAC_CMD_RS);
509
spin_unlock_irqrestore(&cs->lock, flags);
511
case (HW_ENABLE | REQUEST):
512
spin_lock_irqsave(&cs->lock, flags);
513
ph_command(cs, ISAC_CMD_TIM);
514
spin_unlock_irqrestore(&cs->lock, flags);
516
case (HW_INFO3 | REQUEST):
517
spin_lock_irqsave(&cs->lock, flags);
518
ph_command(cs, ISAC_CMD_AR8);
519
spin_unlock_irqrestore(&cs->lock, flags);
521
case (HW_TESTLOOP | REQUEST):
522
spin_lock_irqsave(&cs->lock, flags);
528
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
531
cs->writeisac(cs, ISAC_SPCR, 0xa);
532
cs->writeisac(cs, ISAC_ADF1, 0x2);
534
cs->writeisac(cs, ISAC_SPCR, val);
535
cs->writeisac(cs, ISAC_ADF1, 0xa);
539
cs->writeisac(cs, ISAC_SPCR, val);
541
cs->writeisac(cs, ISAC_ADF1, 0x8);
543
cs->writeisac(cs, ISAC_ADF1, 0x0);
545
spin_unlock_irqrestore(&cs->lock, flags);
547
case (HW_DEACTIVATE | RESPONSE):
548
skb_queue_purge(&cs->rq);
549
skb_queue_purge(&cs->sq);
551
dev_kfree_skb_any(cs->tx_skb);
554
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
555
del_timer(&cs->dbusytimer);
556
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
557
schedule_event(cs, D_CLEARBUSY);
560
if (cs->debug & L1_DEB_WARN)
561
debugl1(cs, "isac_l1hw unknown %04x", pr);
567
setstack_isac(struct PStack *st, struct IsdnCardState *cs)
569
st->l1.l1hw = ISAC_l1hw;
573
DC_Close_isac(struct IsdnCardState *cs)
575
kfree(cs->dc.isac.mon_rx);
576
cs->dc.isac.mon_rx = NULL;
577
kfree(cs->dc.isac.mon_tx);
578
cs->dc.isac.mon_tx = NULL;
582
dbusy_timer_handler(struct IsdnCardState *cs)
584
struct PStack *stptr;
587
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
588
rbch = cs->readisac(cs, ISAC_RBCH);
589
star = cs->readisac(cs, ISAC_STAR);
591
debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
593
if (rbch & ISAC_RBCH_XAC) { /* D-Channel Busy */
594
test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
596
while (stptr != NULL) {
597
stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
601
/* discard frame; reset transceiver */
602
test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
604
dev_kfree_skb_any(cs->tx_skb);
608
printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
609
debugl1(cs, "D-Channel Busy no skb");
611
cs->writeisac(cs, ISAC_CMDR, 0x01); /* Transmitter reset */
612
cs->irq_func(cs->irq, cs);
617
void initisac(struct IsdnCardState *cs)
619
cs->setstack_d = setstack_isac;
620
cs->DC_Close = DC_Close_isac;
621
cs->dc.isac.mon_tx = NULL;
622
cs->dc.isac.mon_rx = NULL;
623
cs->writeisac(cs, ISAC_MASK, 0xff);
624
cs->dc.isac.mocr = 0xaa;
625
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
627
cs->writeisac(cs, ISAC_ADF2, 0x0);
628
cs->writeisac(cs, ISAC_SPCR, 0xa);
629
cs->writeisac(cs, ISAC_ADF1, 0x2);
630
cs->writeisac(cs, ISAC_STCR, 0x70);
631
cs->writeisac(cs, ISAC_MODE, 0xc9);
634
if (!cs->dc.isac.adf2)
635
cs->dc.isac.adf2 = 0x80;
636
cs->writeisac(cs, ISAC_ADF2, cs->dc.isac.adf2);
637
cs->writeisac(cs, ISAC_SQXR, 0x2f);
638
cs->writeisac(cs, ISAC_SPCR, 0x00);
639
cs->writeisac(cs, ISAC_STCR, 0x70);
640
cs->writeisac(cs, ISAC_MODE, 0xc9);
641
cs->writeisac(cs, ISAC_TIMR, 0x00);
642
cs->writeisac(cs, ISAC_ADF1, 0x00);
644
ph_command(cs, ISAC_CMD_RS);
645
cs->writeisac(cs, ISAC_MASK, 0x0);
648
void clear_pending_isac_ints(struct IsdnCardState *cs)
652
val = cs->readisac(cs, ISAC_STAR);
653
debugl1(cs, "ISAC STAR %x", val);
654
val = cs->readisac(cs, ISAC_MODE);
655
debugl1(cs, "ISAC MODE %x", val);
656
val = cs->readisac(cs, ISAC_ADF2);
657
debugl1(cs, "ISAC ADF2 %x", val);
658
val = cs->readisac(cs, ISAC_ISTA);
659
debugl1(cs, "ISAC ISTA %x", val);
661
eval = cs->readisac(cs, ISAC_EXIR);
662
debugl1(cs, "ISAC EXIR %x", eval);
664
val = cs->readisac(cs, ISAC_CIR0);
665
debugl1(cs, "ISAC CIR0 %x", val);
666
cs->dc.isac.ph_state = (val >> 2) & 0xf;
667
schedule_event(cs, D_L1STATECHANGE);
668
/* Disable all IRQ */
669
cs->writeisac(cs, ISAC_MASK, 0xFF);
673
setup_isac(struct IsdnCardState *cs)
675
INIT_WORK(&cs->tqueue, isac_bh);
676
cs->dbusytimer.function = (void *) dbusy_timer_handler;
677
cs->dbusytimer.data = (long) cs;
678
init_timer(&cs->dbusytimer);