2
* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3
* Copyright (C) 2003 Red Hat
4
* Copyright (C) 2007-2008 MontaVista Software, Inc.
5
* Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
7
* May be copied or modified under the terms of the GNU General Public License
9
* Documentation for CMD680:
10
* http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12
* Documentation for SiI 3112:
13
* http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15
* Errata and other documentation only available under NDA.
19
* If you are using Marvell SATA-IDE adapters with Maxtor drives
20
* ensure the system is set up for ATA100/UDMA5, not UDMA6.
22
* If you are using WD drives with SATA bridges you must set the
23
* drive to "Single". "Master" will hang.
25
* If you have strange problems with nVidia chipset systems please
26
* see the SI support documentation and update your system BIOS
29
* The Dell DRAC4 has some interesting features including effectively hot
30
* unplugging/replugging the virtual CD interface when the DRAC is reset.
31
* This often causes drivers/ide/siimage to panic but is ok with the rather
32
* smarter code in libata.
38
#include <linux/types.h>
39
#include <linux/module.h>
40
#include <linux/pci.h>
41
#include <linux/ide.h>
42
#include <linux/init.h>
45
#define DRV_NAME "siimage"
48
* pdev_is_sata - check if device is SATA
49
* @pdev: PCI device to check
51
* Returns true if this is a SATA controller
54
static int pdev_is_sata(struct pci_dev *pdev)
56
#ifdef CONFIG_BLK_DEV_IDE_SATA
57
switch (pdev->device) {
58
case PCI_DEVICE_ID_SII_3112:
59
case PCI_DEVICE_ID_SII_1210SA:
61
case PCI_DEVICE_ID_SII_680:
70
* is_sata - check if hwif is SATA
71
* @hwif: interface to check
73
* Returns true if this is a SATA controller
76
static inline int is_sata(ide_hwif_t *hwif)
78
return pdev_is_sata(to_pci_dev(hwif->dev));
82
* siimage_selreg - return register base
86
* Turn a config register offset into the right address in either
87
* PCI space or MMIO space to access the control register in question
88
* Thankfully this is a configuration operation, so isn't performance
92
static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
94
unsigned long base = (unsigned long)hwif->hwif_data;
97
if (hwif->host_flags & IDE_HFLAG_MMIO)
98
base += hwif->channel << 6;
100
base += hwif->channel << 4;
105
* siimage_seldev - return register base
109
* Turn a config register offset into the right address in either
110
* PCI space or MMIO space to access the control register in question
111
* including accounting for the unit shift.
114
static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
116
ide_hwif_t *hwif = drive->hwif;
117
unsigned long base = (unsigned long)hwif->hwif_data;
118
u8 unit = drive->dn & 1;
121
if (hwif->host_flags & IDE_HFLAG_MMIO)
122
base += hwif->channel << 6;
124
base += hwif->channel << 4;
125
base |= unit << unit;
129
static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
131
struct ide_host *host = pci_get_drvdata(dev);
135
tmp = readb((void __iomem *)addr);
137
pci_read_config_byte(dev, addr, &tmp);
142
static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
144
struct ide_host *host = pci_get_drvdata(dev);
148
tmp = readw((void __iomem *)addr);
150
pci_read_config_word(dev, addr, &tmp);
155
static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
157
struct ide_host *host = pci_get_drvdata(dev);
160
writeb(val, (void __iomem *)addr);
162
pci_write_config_byte(dev, addr, val);
165
static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
167
struct ide_host *host = pci_get_drvdata(dev);
170
writew(val, (void __iomem *)addr);
172
pci_write_config_word(dev, addr, val);
175
static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
177
struct ide_host *host = pci_get_drvdata(dev);
180
writel(val, (void __iomem *)addr);
182
pci_write_config_dword(dev, addr, val);
186
* sil_udma_filter - compute UDMA mask
189
* Compute the available UDMA speeds for the device on the interface.
191
* For the CMD680 this depends on the clocking mode (scsc), for the
192
* SI3112 SATA controller life is a bit simpler.
195
static u8 sil_pata_udma_filter(ide_drive_t *drive)
197
ide_hwif_t *hwif = drive->hwif;
198
struct pci_dev *dev = to_pci_dev(hwif->dev);
199
unsigned long base = (unsigned long)hwif->hwif_data;
202
base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
204
scsc = sil_ioread8(dev, base);
206
switch (scsc & 0x30) {
210
case 0x20: /* 2xPCI */
216
default: /* Disabled ? */
223
static u8 sil_sata_udma_filter(ide_drive_t *drive)
225
char *m = (char *)&drive->id[ATA_ID_PROD];
227
return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
231
* sil_set_pio_mode - set host controller for PIO mode
235
* Load the timing settings for this device mode into the
239
static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
241
static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
242
static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
244
struct pci_dev *dev = to_pci_dev(hwif->dev);
245
ide_drive_t *pair = ide_get_pair_dev(drive);
248
unsigned long addr = siimage_seldev(drive, 0x04);
249
unsigned long tfaddr = siimage_selreg(hwif, 0x02);
250
unsigned long base = (unsigned long)hwif->hwif_data;
251
const u8 pio = drive->pio_mode - XFER_PIO_0;
253
u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
254
u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
255
: (mmio ? 0xB4 : 0x80);
257
u8 unit = drive->dn & 1;
259
/* trim *taskfile* PIO to the slowest of the master/slave */
261
u8 pair_pio = pair->pio_mode - XFER_PIO_0;
263
if (pair_pio < tf_pio)
267
/* cheat for now and use the docs */
268
speedp = data_speed[pio];
269
speedt = tf_speed[tf_pio];
271
sil_iowrite16(dev, speedp, addr);
272
sil_iowrite16(dev, speedt, tfaddr);
274
/* now set up IORDY */
275
speedp = sil_ioread16(dev, tfaddr - 2);
278
mode = sil_ioread8(dev, base + addr_mask);
279
mode &= ~(unit ? 0x30 : 0x03);
281
if (ide_pio_need_iordy(drive, pio)) {
283
mode |= unit ? 0x10 : 0x01;
286
sil_iowrite16(dev, speedp, tfaddr - 2);
287
sil_iowrite8(dev, mode, base + addr_mask);
291
* sil_set_dma_mode - set host controller for DMA mode
295
* Tune the SiI chipset for the desired DMA mode.
298
static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
300
static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
301
static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
302
static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
304
struct pci_dev *dev = to_pci_dev(hwif->dev);
305
unsigned long base = (unsigned long)hwif->hwif_data;
306
u16 ultra = 0, multi = 0;
307
u8 mode = 0, unit = drive->dn & 1;
308
u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
309
u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
310
: (mmio ? 0xB4 : 0x80);
311
unsigned long ma = siimage_seldev(drive, 0x08);
312
unsigned long ua = siimage_seldev(drive, 0x0C);
313
const u8 speed = drive->dma_mode;
315
scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
316
mode = sil_ioread8 (dev, base + addr_mask);
317
multi = sil_ioread16(dev, ma);
318
ultra = sil_ioread16(dev, ua);
320
mode &= ~(unit ? 0x30 : 0x03);
322
scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
324
scsc = is_sata(hwif) ? 1 : scsc;
326
if (speed >= XFER_UDMA_0) {
328
ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
329
ultra5[speed - XFER_UDMA_0];
330
mode |= unit ? 0x30 : 0x03;
332
multi = dma[speed - XFER_MW_DMA_0];
333
mode |= unit ? 0x20 : 0x02;
336
sil_iowrite8 (dev, mode, base + addr_mask);
337
sil_iowrite16(dev, multi, ma);
338
sil_iowrite16(dev, ultra, ua);
341
static int sil_test_irq(ide_hwif_t *hwif)
343
struct pci_dev *dev = to_pci_dev(hwif->dev);
344
unsigned long addr = siimage_selreg(hwif, 1);
345
u8 val = sil_ioread8(dev, addr);
347
/* Return 1 if INTRQ asserted */
348
return (val & 8) ? 1 : 0;
352
* siimage_mmio_dma_test_irq - check we caused an IRQ
353
* @drive: drive we are testing
355
* Check if we caused an IDE DMA interrupt. We may also have caused
356
* SATA status interrupts, if so we clean them up and continue.
359
static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
361
ide_hwif_t *hwif = drive->hwif;
362
void __iomem *sata_error_addr
363
= (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
365
if (sata_error_addr) {
366
unsigned long base = (unsigned long)hwif->hwif_data;
367
u32 ext_stat = readl((void __iomem *)(base + 0x10));
370
if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
371
u32 sata_error = readl(sata_error_addr);
373
writel(sata_error, sata_error_addr);
374
watchdog = (sata_error & 0x00680000) ? 1 : 0;
375
printk(KERN_WARNING "%s: sata_error = 0x%08x, "
376
"watchdog = %d, %s\n",
377
drive->name, sata_error, watchdog, __func__);
379
watchdog = (ext_stat & 0x8000) ? 1 : 0;
382
if (!(ext_stat & 0x0404) && !watchdog)
386
/* return 1 if INTR asserted */
387
if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
393
static int siimage_dma_test_irq(ide_drive_t *drive)
395
if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
396
return siimage_mmio_dma_test_irq(drive);
398
return ide_dma_test_irq(drive);
402
* sil_sata_reset_poll - wait for SATA reset
403
* @drive: drive we are resetting
405
* Poll the SATA phy and see whether it has come back from the dead
409
static int sil_sata_reset_poll(ide_drive_t *drive)
411
ide_hwif_t *hwif = drive->hwif;
412
void __iomem *sata_status_addr
413
= (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
415
if (sata_status_addr) {
416
/* SATA Status is available only when in MMIO mode */
417
u32 sata_stat = readl(sata_status_addr);
419
if ((sata_stat & 0x03) != 0x03) {
420
printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
421
hwif->name, sata_stat);
430
* sil_sata_pre_reset - reset hook
431
* @drive: IDE device being reset
433
* For the SATA devices we need to handle recalibration/geometry
437
static void sil_sata_pre_reset(ide_drive_t *drive)
439
if (drive->media == ide_disk) {
440
drive->special_flags &=
441
~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE);
446
* init_chipset_siimage - set up an SI device
449
* Perform the initial PCI set up for this device. Attempt to switch
450
* to 133 MHz clocking if the system isn't already set up to do it.
453
static int init_chipset_siimage(struct pci_dev *dev)
455
struct ide_host *host = pci_get_drvdata(dev);
456
void __iomem *ioaddr = host->host_priv;
457
unsigned long base, scsc_addr;
458
u8 rev = dev->revision, tmp;
460
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
465
base = (unsigned long)ioaddr;
467
if (ioaddr && pdev_is_sata(dev)) {
470
/* make sure IDE0/1 interrupts are not masked */
471
irq_mask = (1 << 22) | (1 << 23);
472
tmp32 = readl(ioaddr + 0x48);
473
if (tmp32 & irq_mask) {
475
writel(tmp32, ioaddr + 0x48);
476
readl(ioaddr + 0x48); /* flush */
478
writel(0, ioaddr + 0x148);
479
writel(0, ioaddr + 0x1C8);
482
sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
483
sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
485
scsc_addr = base ? (base + 0x4A) : 0x8A;
486
tmp = sil_ioread8(dev, scsc_addr);
488
switch (tmp & 0x30) {
490
/* On 100 MHz clocking, try and switch to 133 MHz */
491
sil_iowrite8(dev, tmp | 0x10, scsc_addr);
494
/* Clocking is disabled, attempt to force 133MHz clocking. */
495
sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
497
/* On 133Mhz clocking. */
500
/* On PCIx2 clocking. */
504
tmp = sil_ioread8(dev, scsc_addr);
506
sil_iowrite8 (dev, 0x72, base + 0xA1);
507
sil_iowrite16(dev, 0x328A, base + 0xA2);
508
sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
509
sil_iowrite32(dev, 0x43924392, base + 0xA8);
510
sil_iowrite32(dev, 0x40094009, base + 0xAC);
511
sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
512
sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
513
sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
514
sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
515
sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
517
if (base && pdev_is_sata(dev)) {
518
writel(0xFFFF0000, ioaddr + 0x108);
519
writel(0xFFFF0000, ioaddr + 0x188);
520
writel(0x00680000, ioaddr + 0x148);
521
writel(0x00680000, ioaddr + 0x1C8);
524
/* report the clocking mode of the controller */
525
if (!pdev_is_sata(dev)) {
526
static const char *clk_str[] =
527
{ "== 100", "== 133", "== 2X PCI", "DISABLED!" };
530
printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
531
pci_name(dev), clk_str[tmp & 3]);
538
* init_mmio_iops_siimage - set up the iops for MMIO
539
* @hwif: interface to set up
541
* The basic setup here is fairly simple, we can use standard MMIO
542
* operations. However we do have to set the taskfile register offsets
543
* by hand as there isn't a standard defined layout for them this time.
545
* The hardware supports buffered taskfiles and also some rather nice
546
* extended PRD tables. For better SI3112 support use the libata driver
549
static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
551
struct pci_dev *dev = to_pci_dev(hwif->dev);
552
struct ide_host *host = pci_get_drvdata(dev);
553
void *addr = host->host_priv;
554
u8 ch = hwif->channel;
555
struct ide_io_ports *io_ports = &hwif->io_ports;
559
* Fill in the basic hwif bits
561
hwif->host_flags |= IDE_HFLAG_MMIO;
563
hwif->hwif_data = addr;
566
* Now set up the hw. We have to do this ourselves as the
567
* MMIO layout isn't the same as the standard port based I/O.
569
memset(io_ports, 0, sizeof(*io_ports));
571
base = (unsigned long)addr;
578
* The buffered task file doesn't have status/control, so we
579
* can't currently use it sanely since we want to use LBA48 mode.
581
io_ports->data_addr = base;
582
io_ports->error_addr = base + 1;
583
io_ports->nsect_addr = base + 2;
584
io_ports->lbal_addr = base + 3;
585
io_ports->lbam_addr = base + 4;
586
io_ports->lbah_addr = base + 5;
587
io_ports->device_addr = base + 6;
588
io_ports->status_addr = base + 7;
589
io_ports->ctl_addr = base + 10;
591
if (pdev_is_sata(dev)) {
592
base = (unsigned long)addr;
595
hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
596
hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
597
hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
600
hwif->irq = dev->irq;
602
hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
605
static int is_dev_seagate_sata(ide_drive_t *drive)
607
const char *s = (const char *)&drive->id[ATA_ID_PROD];
608
unsigned len = strnlen(s, ATA_ID_PROD_LEN);
610
if ((len > 4) && (!memcmp(s, "ST", 2)))
611
if ((!memcmp(s + len - 2, "AS", 2)) ||
612
(!memcmp(s + len - 3, "ASL", 3))) {
613
printk(KERN_INFO "%s: applying pessimistic Seagate "
614
"errata fix\n", drive->name);
622
* sil_quirkproc - post probe fixups
625
* Called after drive probe we use this to decide whether the
626
* Seagate fixup must be applied. This used to be in init_iops but
627
* that can occur before we know what drives are present.
630
static void sil_quirkproc(ide_drive_t *drive)
632
ide_hwif_t *hwif = drive->hwif;
634
/* Try and rise the rqsize */
635
if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
640
* init_iops_siimage - set up iops
641
* @hwif: interface to set up
643
* Do the basic setup for the SIIMAGE hardware interface
644
* and then do the MMIO setup if we can. This is the first
645
* look in we get for setting up the hwif so that we
646
* can get the iops right before using them.
649
static void __devinit init_iops_siimage(ide_hwif_t *hwif)
651
struct pci_dev *dev = to_pci_dev(hwif->dev);
652
struct ide_host *host = pci_get_drvdata(dev);
654
hwif->hwif_data = NULL;
656
/* Pessimal until we finish probing */
660
init_mmio_iops_siimage(hwif);
664
* sil_cable_detect - cable detection
665
* @hwif: interface to check
667
* Check for the presence of an ATA66 capable cable on the interface.
670
static u8 sil_cable_detect(ide_hwif_t *hwif)
672
struct pci_dev *dev = to_pci_dev(hwif->dev);
673
unsigned long addr = siimage_selreg(hwif, 0);
674
u8 ata66 = sil_ioread8(dev, addr);
676
return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
679
static const struct ide_port_ops sil_pata_port_ops = {
680
.set_pio_mode = sil_set_pio_mode,
681
.set_dma_mode = sil_set_dma_mode,
682
.quirkproc = sil_quirkproc,
683
.test_irq = sil_test_irq,
684
.udma_filter = sil_pata_udma_filter,
685
.cable_detect = sil_cable_detect,
688
static const struct ide_port_ops sil_sata_port_ops = {
689
.set_pio_mode = sil_set_pio_mode,
690
.set_dma_mode = sil_set_dma_mode,
691
.reset_poll = sil_sata_reset_poll,
692
.pre_reset = sil_sata_pre_reset,
693
.quirkproc = sil_quirkproc,
694
.test_irq = sil_test_irq,
695
.udma_filter = sil_sata_udma_filter,
696
.cable_detect = sil_cable_detect,
699
static const struct ide_dma_ops sil_dma_ops = {
700
.dma_host_set = ide_dma_host_set,
701
.dma_setup = ide_dma_setup,
702
.dma_start = ide_dma_start,
703
.dma_end = ide_dma_end,
704
.dma_test_irq = siimage_dma_test_irq,
705
.dma_timer_expiry = ide_dma_sff_timer_expiry,
706
.dma_lost_irq = ide_dma_lost_irq,
707
.dma_sff_read_status = ide_dma_sff_read_status,
710
#define DECLARE_SII_DEV(p_ops) \
713
.init_chipset = init_chipset_siimage, \
714
.init_iops = init_iops_siimage, \
716
.dma_ops = &sil_dma_ops, \
717
.pio_mask = ATA_PIO4, \
718
.mwdma_mask = ATA_MWDMA2, \
719
.udma_mask = ATA_UDMA6, \
722
static const struct ide_port_info siimage_chipsets[] __devinitdata = {
723
/* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops),
724
/* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
728
* siimage_init_one - PCI layer discovery entry
730
* @id: ident table entry
732
* Called by the PCI code when it finds an SiI680 or SiI3112 controller.
733
* We then use the IDE PCI generic helper to do most of the work.
736
static int __devinit siimage_init_one(struct pci_dev *dev,
737
const struct pci_device_id *id)
739
void __iomem *ioaddr = NULL;
740
resource_size_t bar5 = pci_resource_start(dev, 5);
741
unsigned long barsize = pci_resource_len(dev, 5);
743
struct ide_port_info d;
744
u8 idx = id->driver_data;
747
d = siimage_chipsets[idx];
750
static int first = 1;
753
printk(KERN_INFO DRV_NAME ": For full SATA support you "
754
"should use the libata sata_sil module.\n");
758
d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
761
rc = pci_enable_device(dev);
765
pci_read_config_byte(dev, 0x8A, &BA5_EN);
766
if ((BA5_EN & 0x01) || bar5) {
768
* Drop back to PIO if we can't map the MMIO. Some systems
769
* seem to get terminally confused in the PCI spaces.
771
if (!request_mem_region(bar5, barsize, d.name)) {
772
printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
773
"available\n", pci_name(dev));
775
ioaddr = pci_ioremap_bar(dev, 5);
777
release_mem_region(bar5, barsize);
781
rc = ide_pci_init_one(dev, &d, ioaddr);
785
release_mem_region(bar5, barsize);
787
pci_disable_device(dev);
793
static void __devexit siimage_remove(struct pci_dev *dev)
795
struct ide_host *host = pci_get_drvdata(dev);
796
void __iomem *ioaddr = host->host_priv;
801
resource_size_t bar5 = pci_resource_start(dev, 5);
802
unsigned long barsize = pci_resource_len(dev, 5);
805
release_mem_region(bar5, barsize);
808
pci_disable_device(dev);
811
static const struct pci_device_id siimage_pci_tbl[] = {
812
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
813
#ifdef CONFIG_BLK_DEV_IDE_SATA
814
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
815
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
819
MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
821
static struct pci_driver siimage_pci_driver = {
823
.id_table = siimage_pci_tbl,
824
.probe = siimage_init_one,
825
.remove = __devexit_p(siimage_remove),
826
.suspend = ide_pci_suspend,
827
.resume = ide_pci_resume,
830
static int __init siimage_ide_init(void)
832
return ide_pci_register_driver(&siimage_pci_driver);
835
static void __exit siimage_ide_exit(void)
837
pci_unregister_driver(&siimage_pci_driver);
840
module_init(siimage_ide_init);
841
module_exit(siimage_ide_exit);
843
MODULE_AUTHOR("Andre Hedrick, Alan Cox");
844
MODULE_DESCRIPTION("PCI driver module for SiI IDE");
845
MODULE_LICENSE("GPL");