2
Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3
Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
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Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
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Copyright (C) 2010 Intel Corporation,
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David Woodhouse <dwmw2@infradead.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
20
along with this program; if not, write to the Free Software
21
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25
Supports the following Intel I/O Controller Hubs (ICH):
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region SMBus Block proc. block
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Chip name PCI ID size PEC buffer call read
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----------------------------------------------------------------------
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82801AA (ICH) 0x2413 16 no no no no
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82801AB (ICH0) 0x2423 16 no no no no
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82801BA (ICH2) 0x2443 16 no no no no
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82801CA (ICH3) 0x2483 32 soft no no no
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82801DB (ICH4) 0x24c3 32 hard yes no no
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82801E (ICH5) 0x24d3 32 hard yes yes yes
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6300ESB 0x25a4 32 hard yes yes yes
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82801F (ICH6) 0x266a 32 hard yes yes yes
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6310ESB/6320ESB 0x269b 32 hard yes yes yes
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82801G (ICH7) 0x27da 32 hard yes yes yes
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82801H (ICH8) 0x283e 32 hard yes yes yes
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82801I (ICH9) 0x2930 32 hard yes yes yes
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EP80579 (Tolapai) 0x5032 32 hard yes yes yes
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ICH10 0x3a30 32 hard yes yes yes
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ICH10 0x3a60 32 hard yes yes yes
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5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
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6 Series (PCH) 0x1c22 32 hard yes yes yes
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Patsburg (PCH) 0x1d22 32 hard yes yes yes
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Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
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Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
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Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
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DH89xxCC (PCH) 0x2330 32 hard yes yes yes
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Panther Point (PCH) 0x1e22 32 hard yes yes yes
55
Features supported by this driver:
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Block process call transaction no
60
I2C block read transaction yes (doesn't use the block buffer)
63
See the file Documentation/i2c/busses/i2c-i801 for details.
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/acpi.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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/* I801 SMBus address offsets */
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#define SMBHSTSTS(p) (0 + (p)->smba)
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#define SMBHSTCNT(p) (2 + (p)->smba)
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#define SMBHSTCMD(p) (3 + (p)->smba)
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#define SMBHSTADD(p) (4 + (p)->smba)
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#define SMBHSTDAT0(p) (5 + (p)->smba)
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#define SMBHSTDAT1(p) (6 + (p)->smba)
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#define SMBBLKDAT(p) (7 + (p)->smba)
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#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
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#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
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#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
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/* PCI Address Constants */
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#define SMBHSTCFG 0x040
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/* Host configuration bits for SMBHSTCFG */
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#define SMBHSTCFG_HST_EN 1
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#define SMBHSTCFG_SMB_SMI_EN 2
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#define SMBHSTCFG_I2C_EN 4
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/* Auxiliary control register bits, ICH4+ only */
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#define SMBAUXCTL_CRC 1
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#define SMBAUXCTL_E32B 2
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/* kill bit for SMBHSTCNT */
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#define SMBHSTCNT_KILL 2
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#define MAX_TIMEOUT 100
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#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
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/* I801 command constants */
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#define I801_QUICK 0x00
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#define I801_BYTE 0x04
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#define I801_BYTE_DATA 0x08
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#define I801_WORD_DATA 0x0C
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#define I801_PROC_CALL 0x10 /* unimplemented */
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#define I801_BLOCK_DATA 0x14
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#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
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#define I801_BLOCK_LAST 0x34
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#define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
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#define I801_START 0x40
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#define I801_PEC_EN 0x80 /* ICH3 and later */
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/* I801 Hosts Status register bits */
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#define SMBHSTSTS_BYTE_DONE 0x80
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#define SMBHSTSTS_INUSE_STS 0x40
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#define SMBHSTSTS_SMBALERT_STS 0x20
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#define SMBHSTSTS_FAILED 0x10
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#define SMBHSTSTS_BUS_ERR 0x08
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#define SMBHSTSTS_DEV_ERR 0x04
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#define SMBHSTSTS_INTR 0x02
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#define SMBHSTSTS_HOST_BUSY 0x01
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#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
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SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
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/* Older devices have their ID defined in <linux/pci_ids.h> */
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#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
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#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
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/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
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#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
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#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
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#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
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#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
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#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
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#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
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struct i2c_adapter adapter;
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unsigned char original_hstcfg;
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struct pci_dev *pci_dev;
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unsigned int features;
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static struct pci_driver i801_driver;
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#define FEATURE_SMBUS_PEC (1 << 0)
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#define FEATURE_BLOCK_BUFFER (1 << 1)
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#define FEATURE_BLOCK_PROC (1 << 2)
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#define FEATURE_I2C_BLOCK_READ (1 << 3)
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/* Not really a feature, but it's convenient to handle it as such */
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#define FEATURE_IDF (1 << 15)
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static const char *i801_feature_names[] = {
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"Block process call",
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static unsigned int disable_features;
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module_param(disable_features, uint, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(disable_features, "Disable selected driver features");
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/* Make sure the SMBus host is ready to start transmitting.
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Return 0 if it is, -EBUSY if it is not. */
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static int i801_check_pre(struct i801_priv *priv)
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status = inb_p(SMBHSTSTS(priv));
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if (status & SMBHSTSTS_HOST_BUSY) {
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dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
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status &= STATUS_FLAGS;
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dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
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outb_p(status, SMBHSTSTS(priv));
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status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
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dev_err(&priv->pci_dev->dev,
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"Failed clearing status flags (%02x)\n",
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/* Convert the status register to an error code, and clear it. */
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static int i801_check_post(struct i801_priv *priv, int status, int timeout)
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/* If the SMBus is still busy, we give up */
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dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
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/* try to stop the current command */
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dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
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outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
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outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
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/* Check if it worked */
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status = inb_p(SMBHSTSTS(priv));
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if ((status & SMBHSTSTS_HOST_BUSY) ||
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!(status & SMBHSTSTS_FAILED))
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dev_err(&priv->pci_dev->dev,
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"Failed terminating the transaction\n");
228
outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
232
if (status & SMBHSTSTS_FAILED) {
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dev_err(&priv->pci_dev->dev, "Transaction failed\n");
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if (status & SMBHSTSTS_DEV_ERR) {
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dev_dbg(&priv->pci_dev->dev, "No response\n");
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if (status & SMBHSTSTS_BUS_ERR) {
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dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
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/* Clear error flags */
247
outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
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status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
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dev_warn(&priv->pci_dev->dev, "Failed clearing status "
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"flags at end of transaction (%02x)\n",
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static int i801_transaction(struct i801_priv *priv, int xact)
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result = i801_check_pre(priv);
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/* the current contents of SMBHSTCNT can be overwritten, since PEC,
270
* INTREN, SMBSCMD are passed in xact */
271
outb_p(xact | I801_START, SMBHSTCNT(priv));
273
/* We will always wait for a fraction of a second! */
276
status = inb_p(SMBHSTSTS(priv));
277
} while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
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result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
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outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
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/* wait for INTR bit as advised by Intel */
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static void i801_wait_hwpec(struct i801_priv *priv)
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status = inb_p(SMBHSTSTS(priv));
296
} while ((!(status & SMBHSTSTS_INTR))
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&& (timeout++ < MAX_TIMEOUT));
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if (timeout > MAX_TIMEOUT)
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dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
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outb_p(status, SMBHSTSTS(priv));
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static int i801_block_transaction_by_block(struct i801_priv *priv,
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union i2c_smbus_data *data,
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char read_write, int hwpec)
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inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
314
/* Use 32-byte buffer to process this transaction */
315
if (read_write == I2C_SMBUS_WRITE) {
316
len = data->block[0];
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outb_p(len, SMBHSTDAT0(priv));
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for (i = 0; i < len; i++)
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outb_p(data->block[i+1], SMBBLKDAT(priv));
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status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
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I801_PEC_EN * hwpec);
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if (read_write == I2C_SMBUS_READ) {
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len = inb_p(SMBHSTDAT0(priv));
329
if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
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data->block[0] = len;
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for (i = 0; i < len; i++)
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data->block[i + 1] = inb_p(SMBBLKDAT(priv));
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static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
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union i2c_smbus_data *data,
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char read_write, int command,
350
result = i801_check_pre(priv);
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len = data->block[0];
356
if (read_write == I2C_SMBUS_WRITE) {
357
outb_p(len, SMBHSTDAT0(priv));
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outb_p(data->block[1], SMBBLKDAT(priv));
361
for (i = 1; i <= len; i++) {
362
if (i == len && read_write == I2C_SMBUS_READ) {
363
if (command == I2C_SMBUS_I2C_BLOCK_DATA)
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smbcmd = I801_I2C_BLOCK_LAST;
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smbcmd = I801_BLOCK_LAST;
368
if (command == I2C_SMBUS_I2C_BLOCK_DATA
369
&& read_write == I2C_SMBUS_READ)
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smbcmd = I801_I2C_BLOCK_DATA;
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smbcmd = I801_BLOCK_DATA;
374
outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
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outb_p(inb(SMBHSTCNT(priv)) | I801_START,
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/* We will always wait for a fraction of a second! */
384
status = inb_p(SMBHSTSTS(priv));
385
} while ((!(status & SMBHSTSTS_BYTE_DONE))
386
&& (timeout++ < MAX_TIMEOUT));
388
result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
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if (i == 1 && read_write == I2C_SMBUS_READ
393
&& command != I2C_SMBUS_I2C_BLOCK_DATA) {
394
len = inb_p(SMBHSTDAT0(priv));
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if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
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dev_err(&priv->pci_dev->dev,
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"Illegal SMBus block read size %d\n",
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while (inb_p(SMBHSTSTS(priv)) &
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outb_p(SMBHSTSTS_BYTE_DONE,
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outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
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data->block[0] = len;
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/* Retrieve/store value in SMBBLKDAT */
411
if (read_write == I2C_SMBUS_READ)
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data->block[i] = inb_p(SMBBLKDAT(priv));
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if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
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outb_p(data->block[i+1], SMBBLKDAT(priv));
416
/* signals SMBBLKDAT ready */
417
outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
423
static int i801_set_block_buffer_mode(struct i801_priv *priv)
425
outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
426
if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
431
/* Block transaction function */
432
static int i801_block_transaction(struct i801_priv *priv,
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union i2c_smbus_data *data, char read_write,
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int command, int hwpec)
439
if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
440
if (read_write == I2C_SMBUS_WRITE) {
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/* set I2C_EN bit in configuration register */
442
pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
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pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
444
hostc | SMBHSTCFG_I2C_EN);
445
} else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
446
dev_err(&priv->pci_dev->dev,
447
"I2C block read is unsupported!\n");
452
if (read_write == I2C_SMBUS_WRITE
453
|| command == I2C_SMBUS_I2C_BLOCK_DATA) {
454
if (data->block[0] < 1)
456
if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
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data->block[0] = I2C_SMBUS_BLOCK_MAX;
459
data->block[0] = 32; /* max for SMBus block reads */
462
/* Experience has shown that the block buffer can only be used for
463
SMBus (not I2C) block transactions, even though the datasheet
464
doesn't mention this limitation. */
465
if ((priv->features & FEATURE_BLOCK_BUFFER)
466
&& command != I2C_SMBUS_I2C_BLOCK_DATA
467
&& i801_set_block_buffer_mode(priv) == 0)
468
result = i801_block_transaction_by_block(priv, data,
471
result = i801_block_transaction_byte_by_byte(priv, data,
475
if (result == 0 && hwpec)
476
i801_wait_hwpec(priv);
478
if (command == I2C_SMBUS_I2C_BLOCK_DATA
479
&& read_write == I2C_SMBUS_WRITE) {
480
/* restore saved configuration register value */
481
pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
486
/* Return negative errno on error. */
487
static s32 i801_access(struct i2c_adapter *adap, u16 addr,
488
unsigned short flags, char read_write, u8 command,
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int size, union i2c_smbus_data *data)
494
struct i801_priv *priv = i2c_get_adapdata(adap);
496
hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
497
&& size != I2C_SMBUS_QUICK
498
&& size != I2C_SMBUS_I2C_BLOCK_DATA;
501
case I2C_SMBUS_QUICK:
502
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
507
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
509
if (read_write == I2C_SMBUS_WRITE)
510
outb_p(command, SMBHSTCMD(priv));
513
case I2C_SMBUS_BYTE_DATA:
514
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
516
outb_p(command, SMBHSTCMD(priv));
517
if (read_write == I2C_SMBUS_WRITE)
518
outb_p(data->byte, SMBHSTDAT0(priv));
519
xact = I801_BYTE_DATA;
521
case I2C_SMBUS_WORD_DATA:
522
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
524
outb_p(command, SMBHSTCMD(priv));
525
if (read_write == I2C_SMBUS_WRITE) {
526
outb_p(data->word & 0xff, SMBHSTDAT0(priv));
527
outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
529
xact = I801_WORD_DATA;
531
case I2C_SMBUS_BLOCK_DATA:
532
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
534
outb_p(command, SMBHSTCMD(priv));
537
case I2C_SMBUS_I2C_BLOCK_DATA:
538
/* NB: page 240 of ICH5 datasheet shows that the R/#W
539
* bit should be cleared here, even when reading */
540
outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
541
if (read_write == I2C_SMBUS_READ) {
542
/* NB: page 240 of ICH5 datasheet also shows
543
* that DATA1 is the cmd field when reading */
544
outb_p(command, SMBHSTDAT1(priv));
546
outb_p(command, SMBHSTCMD(priv));
550
dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
555
if (hwpec) /* enable/disable hardware PEC */
556
outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
558
outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
562
ret = i801_block_transaction(priv, data, read_write, size,
565
ret = i801_transaction(priv, xact | ENABLE_INT9);
567
/* Some BIOSes don't like it when PEC is enabled at reboot or resume
568
time, so we forcibly disable it after every transaction. Turn off
569
E32B for the same reason. */
571
outb_p(inb_p(SMBAUXCTL(priv)) &
572
~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
578
if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
581
switch (xact & 0x7f) {
582
case I801_BYTE: /* Result put in SMBHSTDAT0 */
584
data->byte = inb_p(SMBHSTDAT0(priv));
587
data->word = inb_p(SMBHSTDAT0(priv)) +
588
(inb_p(SMBHSTDAT1(priv)) << 8);
595
static u32 i801_func(struct i2c_adapter *adapter)
597
struct i801_priv *priv = i2c_get_adapdata(adapter);
599
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
600
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
601
I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
602
((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
603
((priv->features & FEATURE_I2C_BLOCK_READ) ?
604
I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
607
static const struct i2c_algorithm smbus_algorithm = {
608
.smbus_xfer = i801_access,
609
.functionality = i801_func,
612
static const struct pci_device_id i801_ids[] = {
613
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
614
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
615
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
616
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
617
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
618
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
619
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
620
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
621
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
622
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
623
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
624
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
625
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
626
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
627
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
628
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
629
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
630
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
631
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
632
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
633
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
634
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
635
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
639
MODULE_DEVICE_TABLE(pci, i801_ids);
641
#if defined CONFIG_X86 && defined CONFIG_DMI
642
static unsigned char apanel_addr;
644
/* Scan the system ROM for the signature "FJKEYINF" */
645
static __init const void __iomem *bios_signature(const void __iomem *bios)
648
const unsigned char signature[] = "FJKEYINF";
650
for (offset = 0; offset < 0x10000; offset += 0x10) {
651
if (check_signature(bios + offset, signature,
652
sizeof(signature)-1))
653
return bios + offset;
658
static void __init input_apanel_init(void)
661
const void __iomem *p;
663
bios = ioremap(0xF0000, 0x10000); /* Can't fail */
664
p = bios_signature(bios);
666
/* just use the first address */
667
apanel_addr = readb(p + 8 + 3) >> 1;
672
struct dmi_onboard_device_info {
675
unsigned short i2c_addr;
676
const char *i2c_type;
679
static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
680
{ "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
681
{ "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
682
{ "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
685
static void __devinit dmi_check_onboard_device(u8 type, const char *name,
686
struct i2c_adapter *adap)
689
struct i2c_board_info info;
691
for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
692
/* & ~0x80, ignore enabled/disabled bit */
693
if ((type & ~0x80) != dmi_devices[i].type)
695
if (strcasecmp(name, dmi_devices[i].name))
698
memset(&info, 0, sizeof(struct i2c_board_info));
699
info.addr = dmi_devices[i].i2c_addr;
700
strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
701
i2c_new_device(adap, &info);
706
/* We use our own function to check for onboard devices instead of
707
dmi_find_device() as some buggy BIOS's have the devices we are interested
708
in marked as disabled */
709
static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
717
count = (dm->length - sizeof(struct dmi_header)) / 2;
718
for (i = 0; i < count; i++) {
719
const u8 *d = (char *)(dm + 1) + (i * 2);
720
const char *name = ((char *) dm) + dm->length;
727
while (s > 0 && name[0]) {
728
name += strlen(name) + 1;
731
if (name[0] == 0) /* Bogus string reference */
734
dmi_check_onboard_device(type, name, adap);
738
/* Register optional slaves */
739
static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
741
/* Only register slaves on main SMBus channel */
742
if (priv->features & FEATURE_IDF)
746
struct i2c_board_info info;
748
memset(&info, 0, sizeof(struct i2c_board_info));
749
info.addr = apanel_addr;
750
strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
751
i2c_new_device(&priv->adapter, &info);
754
if (dmi_name_in_vendors("FUJITSU"))
755
dmi_walk(dmi_check_onboard_devices, &priv->adapter);
758
static void __init input_apanel_init(void) {}
759
static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
760
#endif /* CONFIG_X86 && CONFIG_DMI */
762
static int __devinit i801_probe(struct pci_dev *dev,
763
const struct pci_device_id *id)
767
struct i801_priv *priv;
769
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
773
i2c_set_adapdata(&priv->adapter, priv);
774
priv->adapter.owner = THIS_MODULE;
775
priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
776
priv->adapter.algo = &smbus_algorithm;
779
switch (dev->device) {
780
case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
781
case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
782
case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
783
priv->features |= FEATURE_IDF;
786
priv->features |= FEATURE_I2C_BLOCK_READ;
788
case PCI_DEVICE_ID_INTEL_82801DB_3:
789
priv->features |= FEATURE_SMBUS_PEC;
790
priv->features |= FEATURE_BLOCK_BUFFER;
792
case PCI_DEVICE_ID_INTEL_82801CA_3:
793
case PCI_DEVICE_ID_INTEL_82801BA_2:
794
case PCI_DEVICE_ID_INTEL_82801AB_3:
795
case PCI_DEVICE_ID_INTEL_82801AA_3:
799
/* Disable features on user request */
800
for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
801
if (priv->features & disable_features & (1 << i))
802
dev_notice(&dev->dev, "%s disabled by user\n",
803
i801_feature_names[i]);
805
priv->features &= ~disable_features;
807
err = pci_enable_device(dev);
809
dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
814
/* Determine the address of the SMBus area */
815
priv->smba = pci_resource_start(dev, SMBBAR);
817
dev_err(&dev->dev, "SMBus base address uninitialized, "
823
err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
829
err = pci_request_region(dev, SMBBAR, i801_driver.name);
831
dev_err(&dev->dev, "Failed to request SMBus region "
832
"0x%lx-0x%Lx\n", priv->smba,
833
(unsigned long long)pci_resource_end(dev, SMBBAR));
837
pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
838
priv->original_hstcfg = temp;
839
temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
840
if (!(temp & SMBHSTCFG_HST_EN)) {
841
dev_info(&dev->dev, "Enabling SMBus device\n");
842
temp |= SMBHSTCFG_HST_EN;
844
pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
846
if (temp & SMBHSTCFG_SMB_SMI_EN)
847
dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
849
dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
851
/* Clear special mode bits */
852
if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
853
outb_p(inb_p(SMBAUXCTL(priv)) &
854
~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
856
/* set up the sysfs linkage to our parent device */
857
priv->adapter.dev.parent = &dev->dev;
859
/* Retry up to 3 times on lost arbitration */
860
priv->adapter.retries = 3;
862
snprintf(priv->adapter.name, sizeof(priv->adapter.name),
863
"SMBus I801 adapter at %04lx", priv->smba);
864
err = i2c_add_adapter(&priv->adapter);
866
dev_err(&dev->dev, "Failed to add SMBus adapter\n");
870
i801_probe_optional_slaves(priv);
872
pci_set_drvdata(dev, priv);
876
pci_release_region(dev, SMBBAR);
882
static void __devexit i801_remove(struct pci_dev *dev)
884
struct i801_priv *priv = pci_get_drvdata(dev);
886
i2c_del_adapter(&priv->adapter);
887
pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
888
pci_release_region(dev, SMBBAR);
889
pci_set_drvdata(dev, NULL);
892
* do not call pci_disable_device(dev) since it can cause hard hangs on
893
* some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
898
static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
900
struct i801_priv *priv = pci_get_drvdata(dev);
903
pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
904
pci_set_power_state(dev, pci_choose_state(dev, mesg));
908
static int i801_resume(struct pci_dev *dev)
910
pci_set_power_state(dev, PCI_D0);
911
pci_restore_state(dev);
912
return pci_enable_device(dev);
915
#define i801_suspend NULL
916
#define i801_resume NULL
919
static struct pci_driver i801_driver = {
920
.name = "i801_smbus",
921
.id_table = i801_ids,
923
.remove = __devexit_p(i801_remove),
924
.suspend = i801_suspend,
925
.resume = i801_resume,
928
static int __init i2c_i801_init(void)
930
if (dmi_name_in_vendors("FUJITSU"))
932
return pci_register_driver(&i801_driver);
935
static void __exit i2c_i801_exit(void)
937
pci_unregister_driver(&i801_driver);
940
MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
941
"Jean Delvare <khali@linux-fr.org>");
942
MODULE_DESCRIPTION("I801 SMBus driver");
943
MODULE_LICENSE("GPL");
945
module_init(i2c_i801_init);
946
module_exit(i2c_i801_exit);