2
This is part of rtl8187 OpenSource driver.
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Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
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Released under the terms of GPL (General Public Licence)
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Parts of this driver are based on the GPL part of the
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official realtek driver
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Parts of this driver are based on the rtl8192 driver skeleton
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from Patric Schenke & Andres Salomon
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Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
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We want to tanks the Authors of those projects and the Ndiswrapper
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#include <linux/module.h>
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#include <linux/kernel.h>
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//#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/netdevice.h>
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//#include <linux/pci.h>
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#include <linux/usb.h>
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#include <linux/etherdevice.h>
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#include <linux/delay.h>
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#include <linux/rtnetlink.h> //for rtnl_lock()
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#include <linux/wireless.h>
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#include <linux/timer.h>
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#include <linux/proc_fs.h> // Necessary because we use the proc fs
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#include <linux/if_arp.h>
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#include <linux/random.h>
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#include "ieee80211/ieee80211.h"
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#define RTL819xU_MODULE_NAME "rtl819xU"
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//added for HW security, john.0629
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#define MAX_KEY_LEN 61
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#define KEY_BUF_SIZE 5
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#define BIT0 0x00000001
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#define BIT1 0x00000002
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#define BIT2 0x00000004
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#define BIT3 0x00000008
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#define BIT4 0x00000010
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#define Rx_Smooth_Factor 20
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#define DMESGW(x,a...)
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#define DMESGE(x,a...)
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extern u32 rt_global_debug_component;
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#define RT_TRACE(component, x, args...) \
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do { if(rt_global_debug_component & component) \
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printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
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#define COMP_TRACE BIT0 // For function call tracing.
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#define COMP_DBG BIT1 // Only for temporary debug message.
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#define COMP_INIT BIT2 // during driver initialization / halt / reset.
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#define COMP_RECV BIT3 // Reveive part data path.
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#define COMP_SEND BIT4 // Send part path.
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#define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
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#define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
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#define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
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#define COMP_SWBW BIT8 // For bandwidth switch.
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#define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
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#define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
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#define COMP_QOS BIT11 // For QoS.
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#define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
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#define COMP_RM BIT13 // For Radio Measurement.
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#define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
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#define COMP_PHY BIT15
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#define COMP_CH BIT16 //channel setting debug
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#define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
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#define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
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#define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
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#define COMP_SEC BIT20 // Event handling
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#define COMP_LED BIT21 // For LED.
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#define COMP_RF BIT22 // For RF.
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//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
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#define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
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//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
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//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
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#define COMP_FIRMWARE BIT24 //for firmware downloading
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#define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
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#define COMP_AMSDU BIT26 // For A-MSDU Debugging
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#define COMP_SCAN BIT27
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//#define COMP_RESET BIT28
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#define COMP_DOWN BIT29 //for rm driver module
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#define COMP_RESET BIT30 //for silent reset
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#define COMP_ERR BIT31 //for error out, always on
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#define RTL819x_DEBUG
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#define assert(expr) \
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printk( "Assertion failed! %s,%s,%s,line=%d\n", \
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#expr,__FILE__,__FUNCTION__,__LINE__); \
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//wb added to debug out data buf
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//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
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#define RT_DEBUG_DATA(level, data, datalen) \
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do{ if ((rt_global_debug_component & (level)) == (level)) \
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u8* pdata = (u8*) data; \
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printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
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for(i=0; i<(int)(datalen); i++) \
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printk("%2x ", pdata[i]); \
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if ((i+1)%16 == 0) printk("\n"); \
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#define assert(expr) do {} while (0)
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#define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
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#endif /* RTL8169_DEBUG */
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// Queue Select Value in TxDesc
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#define QSLT_BEACON 0x10
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#define QSLT_HIGH 0x11
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#define QSLT_MGNT 0x12
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#define QSLT_CMD 0x13
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#define DESC90_RATE1M 0x00
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#define DESC90_RATE2M 0x01
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#define DESC90_RATE5_5M 0x02
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#define DESC90_RATE11M 0x03
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#define DESC90_RATE6M 0x04
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#define DESC90_RATE9M 0x05
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#define DESC90_RATE12M 0x06
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#define DESC90_RATE18M 0x07
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#define DESC90_RATE24M 0x08
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#define DESC90_RATE36M 0x09
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#define DESC90_RATE48M 0x0a
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#define DESC90_RATE54M 0x0b
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#define DESC90_RATEMCS0 0x00
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#define DESC90_RATEMCS1 0x01
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#define DESC90_RATEMCS2 0x02
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#define DESC90_RATEMCS3 0x03
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#define DESC90_RATEMCS4 0x04
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#define DESC90_RATEMCS5 0x05
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#define DESC90_RATEMCS6 0x06
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#define DESC90_RATEMCS7 0x07
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#define DESC90_RATEMCS8 0x08
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#define DESC90_RATEMCS9 0x09
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#define DESC90_RATEMCS10 0x0a
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#define DESC90_RATEMCS11 0x0b
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#define DESC90_RATEMCS12 0x0c
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#define DESC90_RATEMCS13 0x0d
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#define DESC90_RATEMCS14 0x0e
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#define DESC90_RATEMCS15 0x0f
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#define DESC90_RATEMCS32 0x20
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#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
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#define IEEE80211_WATCH_DOG_TIME 2000
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#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
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//for txpowertracking by amy
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#define OFDM_Table_Length 19
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#define CCK_Table_length 12
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typedef struct _tx_desc_819x_usb {
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u8 ResvForPaddingLen:7;
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}tx_desc_819x_usb, *ptx_desc_819x_usb;
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#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
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typedef struct _tx_desc_819x_usb_aggr_subframe {
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}tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
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typedef struct _tx_desc_cmd_819x_usb {
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//u32 NextDescAddress;
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}tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
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typedef struct _tx_fwinfo_819x_usb {
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u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
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u8 TxBandwidth:1; // This is used for HT MCS rate only.
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u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
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u8 AllowAggregation:1;
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u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
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u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
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u8 RtsBandwidth:1; // This is used for HT MCS rate only.
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u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
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u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
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u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
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}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
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typedef struct rtl8192_rx_info {
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struct net_device *dev;
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typedef struct rx_desc_819x_usb{
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}rx_desc_819x_usb, *prx_desc_819x_usb;
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#ifdef USB_RX_AGGREGATION_SUPPORT
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typedef struct _rx_desc_819x_usb_aggr_subframe{
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//u4Byte BufferAddress;
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}rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
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typedef struct rx_drvinfo_819x_usb{
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}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
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#define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
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#define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
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#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
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#define ENCRYPTION_MAX_OVERHEAD 128
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#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
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#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
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#define MAX_FRAGMENT_COUNT 8
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#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
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#define MAX_TRANSMIT_BUFFER_SIZE 32000
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#define MAX_TRANSMIT_BUFFER_SIZE 8000
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#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
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#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
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#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
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#define scrclng 4 // octets for crc32 (FCS, ICV)
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typedef enum rf_optype
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RF_OP_By_SW_3wire = 0,
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/* 8190 Loopback Mode definition */
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typedef enum _rtl819xUsb_loopback{
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RTL819xU_NO_LOOPBACK = 0,
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RTL819xU_MAC_LOOPBACK = 1,
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RTL819xU_DMA_LOOPBACK = 2,
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RTL819xU_CCK_LOOPBACK = 3,
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}rtl819xUsb_loopback_e;
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/* due to rtl8192 firmware */
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typedef enum _desc_packet_type_e{
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DESC_PACKET_TYPE_INIT = 0,
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DESC_PACKET_TYPE_NORMAL = 1,
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typedef enum _firmware_status{
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FW_STATUS_0_INIT = 0,
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FW_STATUS_1_MOVE_BOOT_CODE = 1,
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FW_STATUS_2_MOVE_MAIN_CODE = 2,
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FW_STATUS_3_TURNON_CPU = 3,
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FW_STATUS_4_MOVE_DATA_CODE = 4,
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FW_STATUS_5_READY = 5,
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typedef struct _rt_firmare_seg_container {
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}fw_seg_container, *pfw_seg_container;
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typedef struct _rt_firmware{
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firmware_status_e firmware_status;
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u16 cmdpacket_frag_thresold;
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#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
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u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
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u16 firmware_buf_size;
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}rt_firmware, *prt_firmware;
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#define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
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typedef struct _rt_firmware_info_819xUsb{
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}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
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/* Firmware Queue Layout */
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#define NUM_OF_FIRMWARE_QUEUE 10
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#define NUM_OF_PAGES_IN_FW 0x100
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000
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#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
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#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00
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#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
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#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
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#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
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#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
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#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
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#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
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#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
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#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
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#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
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#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
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#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
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#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
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#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
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#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
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#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
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#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
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//=================================================================
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//=================================================================
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#define EPROM_93c46 0
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#define EPROM_93c56 1
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#define DEFAULT_FRAG_THRESHOLD 2342U
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#define MIN_FRAG_THRESHOLD 256U
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#define DEFAULT_BEACONINTERVAL 0x64U
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#define DEFAULT_BEACON_ESSID "Rtl819xU"
541
#define DEFAULT_SSID ""
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#define DEFAULT_RETRY_RTS 7
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#define DEFAULT_RETRY_DATA 7
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#define PRISM_HDR_SIZE 64
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#define PHY_RSSI_SLID_WIN_MAX 100
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typedef enum _WIRELESS_MODE {
550
WIRELESS_MODE_UNKNOWN = 0x00,
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WIRELESS_MODE_A = 0x01,
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WIRELESS_MODE_B = 0x02,
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WIRELESS_MODE_G = 0x04,
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WIRELESS_MODE_AUTO = 0x08,
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WIRELESS_MODE_N_24G = 0x10,
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WIRELESS_MODE_N_5G = 0x20
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#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
562
typedef struct buffer
569
typedef struct rtl_reg_debug{
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unsigned char length;
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unsigned char buf[0xff];
585
typedef struct _rt_9x_tx_rate_history {
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// HT_MCS[0][]: BW=0 SG=0
589
// HT_MCS[1][]: BW=1 SG=0
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// HT_MCS[2][]: BW=0 SG=1
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// HT_MCS[3][]: BW=1 SG=1
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}rt_tx_rahis_t, *prt_tx_rahis_t;
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typedef struct _RT_SMOOTH_DATA_4RF {
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char elements[4][100];//array to store values
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u32 index; //index to current array to store
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u32 TotalNum; //num of valid elements
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u32 TotalVal[4]; //sum of valid elements
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}RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
601
#define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
602
//stats seems messed up, clean it ASAP
606
// unsigned long rxrdu;
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//unsigned long rxnolast;
608
//unsigned long rxnodata;
609
// unsigned long rxreset;
610
// unsigned long rxnopointer;
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unsigned long rxframgment;
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unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
614
unsigned long rxurberr;
615
unsigned long rxstaterr;
616
unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
617
unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
618
unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
619
unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
620
unsigned long numpacket_matchbssid; // debug use only.
621
unsigned long numpacket_toself; // debug use only.
622
unsigned long num_process_phyinfo; // debug use only.
623
unsigned long numqry_phystatus;
624
unsigned long numqry_phystatusCCK;
625
unsigned long numqry_phystatusHT;
626
unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
627
unsigned long txnperr;
628
unsigned long txnpdrop;
629
unsigned long txresumed;
630
// unsigned long rxerr;
631
// unsigned long rxoverflow;
632
// unsigned long rxint;
633
unsigned long txnpokint;
634
// unsigned long txhpokint;
635
// unsigned long txhperr;
636
// unsigned long ints;
637
// unsigned long shints;
638
unsigned long txoverflow;
639
// unsigned long rxdmafail;
640
// unsigned long txbeacon;
641
// unsigned long txbeaconerr;
642
unsigned long txlpokint;
643
unsigned long txlpdrop;
644
unsigned long txlperr;
645
unsigned long txbeokint;
646
unsigned long txbedrop;
647
unsigned long txbeerr;
648
unsigned long txbkokint;
649
unsigned long txbkdrop;
650
unsigned long txbkerr;
651
unsigned long txviokint;
652
unsigned long txvidrop;
653
unsigned long txvierr;
654
unsigned long txvookint;
655
unsigned long txvodrop;
656
unsigned long txvoerr;
657
unsigned long txbeaconokint;
658
unsigned long txbeacondrop;
659
unsigned long txbeaconerr;
660
unsigned long txmanageokint;
661
unsigned long txmanagedrop;
662
unsigned long txmanageerr;
663
unsigned long txdatapkt;
664
unsigned long txfeedback;
665
unsigned long txfeedbackok;
667
unsigned long txoktotal;
668
unsigned long txokbytestotal;
669
unsigned long txokinperiod;
670
unsigned long txmulticast;
671
unsigned long txbytesmulticast;
672
unsigned long txbroadcast;
673
unsigned long txbytesbroadcast;
674
unsigned long txunicast;
675
unsigned long txbytesunicast;
677
unsigned long rxoktotal;
678
unsigned long rxbytesunicast;
679
unsigned long txfeedbackfail;
680
unsigned long txerrtotal;
681
unsigned long txerrbytestotal;
682
unsigned long txerrmulticast;
683
unsigned long txerrbroadcast;
684
unsigned long txerrunicast;
685
unsigned long txretrycount;
686
unsigned long txfeedbackretry;
688
unsigned long slide_signal_strength[100];
689
unsigned long slide_evm[100];
690
unsigned long slide_rssi_total; // For recording sliding window's RSSI value
691
unsigned long slide_evm_total; // For recording sliding window's EVM value
692
long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
694
long last_signal_strength_inpercent;
695
long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
696
u8 rx_rssi_percentage[4];
697
u8 rx_evm_percentage[2];
699
rt_tx_rahis_t txrate;
700
u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
701
u32 Slide_Beacon_Total; //cosa add for beacon rssi
702
RT_SMOOTH_DATA_4RF cck_adc_pwdb;
704
u32 CurrentShowTxate;
709
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
710
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
711
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
715
typedef struct ChnlAccessSetting {
722
}*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
724
typedef struct _BB_REGISTER_DEFINITION{
725
u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
726
u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
727
u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
728
u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
729
u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
730
u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
731
u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
732
u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
733
u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
734
u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
735
u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
736
u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
737
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
738
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
739
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
740
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
741
u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
742
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
744
typedef enum _RT_RF_TYPE_819xU{
750
}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
752
typedef struct _rate_adaptive
754
u8 rate_adaptive_disabled;
758
u32 high_rssi_thresh_for_ra;
759
u32 high2low_rssi_thresh_for_ra;
760
u8 low2high_rssi_thresh_for_ra40M;
761
u32 low_rssi_thresh_for_ra40M;
762
u8 low2high_rssi_thresh_for_ra20M;
763
u32 low_rssi_thresh_for_ra20M;
764
u32 upper_rssi_threshold_ratr;
765
u32 middle_rssi_threshold_ratr;
766
u32 low_rssi_threshold_ratr;
767
u32 low_rssi_threshold_ratr_40M;
768
u32 low_rssi_threshold_ratr_20M;
769
u8 ping_rssi_enable; //cosa add for test
770
u32 ping_rssi_ratr; //cosa add for test
771
u32 ping_rssi_thresh_for_ra;//cosa add for test
774
} rate_adaptive, *prate_adaptive;
776
#define TxBBGainTableLength 37
777
#define CCKTxBBGainTableLength 23
779
typedef struct _txbbgain_struct
781
long txbb_iq_amplifygain;
783
} txbbgain_struct, *ptxbbgain_struct;
785
typedef struct _ccktxbbgain_struct
787
//The Value is from a22 to a29 one Byte one time is much Safer
788
u8 ccktxbb_valuearray[8];
789
} ccktxbbgain_struct,*pccktxbbgain_struct;
792
typedef struct _init_gain
800
} init_gain, *pinit_gain;
803
typedef struct _phy_ofdm_rx_status_report_819xusb
818
}phy_sts_ofdm_819xusb_t;
820
typedef struct _phy_cck_rx_status_report_819xusb
822
/* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
823
0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
827
}phy_sts_cck_819xusb_t;
830
typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
835
}phy_ofdm_rx_status_rxsc_sgien_exintfflag;
837
typedef enum _RT_CUSTOMER_ID
840
RT_CID_8187_ALPHA0 = 1,
841
RT_CID_8187_SERCOMM_PS = 2,
842
RT_CID_8187_HW_LED = 3,
843
RT_CID_8187_NETGEAR = 4,
845
RT_CID_819x_CAMEO = 6,
846
RT_CID_819x_RUNTOP = 7,
847
RT_CID_819x_Senao = 8,
848
RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
849
RT_CID_819x_Netcore = 10,
850
RT_CID_Nettronix = 11,
853
}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
855
//================================================================================
856
// LED customization.
857
//================================================================================
859
typedef enum _LED_STRATEGY_8190{
860
SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
861
SW_LED_MODE1, // SW control for PCI Express
862
SW_LED_MODE2, // SW control for Cameo.
863
SW_LED_MODE3, // SW contorl for RunTop.
864
SW_LED_MODE4, // SW control for Netcore
865
HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
866
}LED_STRATEGY_8190, *PLED_STRATEGY_8190;
868
typedef enum _RESET_TYPE {
869
RESET_TYPE_NORESET = 0x00,
870
RESET_TYPE_NORMAL = 0x01,
871
RESET_TYPE_SILENT = 0x02
874
/* The simple tx command OP code. */
875
typedef enum _tag_TxCmd_Config_Index{
876
TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
877
TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
878
TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
879
TXCMD_SET_TX_DURATION = 0xFF900003,
880
TXCMD_SET_RX_RSSI = 0xFF900004,
881
TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
885
typedef struct r8192_priv
887
struct usb_device *udev;
888
//added for maintain info from eeprom
892
u8 eeprom_CustomerID;
893
u8 eeprom_ChannelPlan;
894
RT_CUSTOMER_ID CustomerID;
895
LED_STRATEGY_8190 LedStrategy;
896
u8 txqueue_to_outpipemap[9];
898
struct ieee80211_device *ieee80211;
900
short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
901
u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
902
// short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
904
enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
906
short plcp_preamble_mode;
909
// spinlock_t irq_th_lock;
912
//spinlock_t rf_lock; //used to lock rf write operation added by wb
915
// short irq_enabled;
916
// struct net_device *dev; //comment this out.
922
// u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
923
// u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
924
// u8 cck_txpwr_base;
925
// u8 ofdm_txpwr_base;
926
// u8 challow[15]; //channels from 1 to 14, 0 not used
928
short crcmon; //if 1 allow bad crc frame reception in monitor mode
931
// struct timer_list scan_timer;
934
// spinlock_t scan_lock;
936
//u8 active_scan_num;
937
struct semaphore wx_sem;
938
struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
946
u8 rf_type; //0 means 1T2R, 1 means 2T4R
947
RT_RF_TYPE_819xU rf_chip;
950
short (*rf_set_sens)(struct net_device *dev,short sens);
951
u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
952
void (*rf_close)(struct net_device *dev);
953
void (*rf_init)(struct net_device *dev);
958
struct iw_statistics wstats;
959
struct proc_dir_entry *dir_dev;
964
// dma_addr_t rxringdma;
966
struct urb **rx_cmd_urb;
970
#ifdef THOMAS_TASKLET
971
atomic_t irt_counter;//count for irq_rx_tasklet
973
#ifdef JACKSON_NEW_RX
974
struct sk_buff **pp_rxskb;
978
/* modified by davad for Rx process */
979
struct sk_buff_head rx_queue;
980
struct sk_buff_head skb_queue;
981
struct work_struct qos_activate;
983
atomic_t tx_pending[0x10];//UART_PRIORITY+1
986
struct tasklet_struct irq_rx_tasklet;
987
struct urb *rxurb_task;
989
//2 Tx Related variables
993
u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
995
u32 LastRxDescTSFHigh;
996
u32 LastRxDescTSFLow;
999
//2 Rx Related variables
1000
u16 EarlyRxThreshold;
1010
struct ChnlAccessSetting ChannelAccessSetting;
1011
struct work_struct reset_wq;
1013
/**********************************************************/
1019
bool bCurrentRxAggrEnable;
1020
u8 Rf_Mode; //add for Firmware RF -R/W switch
1021
prt_firmware pFirmware;
1022
rtl819xUsb_loopback_e LoopbackMode;
1023
u16 EEPROMTxPowerDiff;
1024
u8 EEPROMThermalMeter;
1026
u8 EEPROMCrystalCap;
1028
u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1029
u8 EEPROMTxPowerLevelCCK_V1[3];
1030
u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1031
u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1034
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1035
// Read/write are allow for following hardware information variables
1036
u32 MCSTxPowerLevelOriginalOffset[6];
1037
u32 CCKTxPowerLevelOriginalOffset;
1038
u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1039
u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1040
u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1043
u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1044
u8 CrystalCap; // CrystalCap.
1045
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1048
// Use to calculate PWBD.
1050
long undecorated_smoothed_pwdb;
1053
u8 SwChnlInProgress;
1056
u8 SetBWModeInProgress;
1057
HT_CHANNEL_WIDTH CurrentChannelBW;
1061
u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1062
// Joseph test for shorten RF configuration time.
1063
// We save RF reg0 in this variable to reduce RF reading.
1067
bool brfpath_rxenable[4];
1069
bool SetRFPowerStateInProgress;
1071
struct timer_list watch_dog_timer;
1073
//+by amy 080515 for dynamic mechenism
1074
//Add by amy Tx Power Control for Near/Far Range 2008/05/15
1075
bool bdynamic_txpower; //bDynamicTxPower
1076
bool bDynamicTxHighPower; // Tx high power state
1077
bool bDynamicTxLowPower; // Tx low power state
1078
bool bLastDTPFlag_High;
1079
bool bLastDTPFlag_Low;
1081
bool bstore_last_dtpflag;
1082
bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1083
//Add by amy for Rate Adaptive
1084
rate_adaptive rate_adaptive;
1085
//Add by amy for TX power tracking
1086
//2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1087
txbbgain_struct txbbgain_table[TxBBGainTableLength];
1088
u8 txpower_count;//For 6 sec do tracking again
1089
bool btxpower_trackingInit;
1092
//2007/09/10 Mars Add CCK TX Power Tracking
1093
ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1094
ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1095
u8 rfa_txpowertrackingindex;
1096
u8 rfa_txpowertrackingindex_real;
1097
u8 rfa_txpowertracking_default;
1098
u8 rfc_txpowertrackingindex;
1099
u8 rfc_txpowertrackingindex_real;
1101
s8 cck_present_attentuation;
1102
u8 cck_present_attentuation_20Mdefault;
1103
u8 cck_present_attentuation_40Mdefault;
1104
char cck_present_attentuation_difference;
1105
bool btxpower_tracking;
1107
bool btxpowerdata_readfromEEPORM;
1109
//For Backup Initial Gain
1110
init_gain initgain_backup;
1111
u8 DefaultInitialGain[4];
1112
// For EDCA Turbo mode, Added by amy 080515.
1113
bool bis_any_nonbepkts;
1114
bool bcurrent_turbo_EDCA;
1115
bool bis_cur_rdlstate;
1116
struct timer_list fsync_timer;
1117
bool bfsync_processing; // 500ms Fsync timer is active or not
1119
u32 rateCountDiffRecord;
1120
u32 ContiuneDiffCount;
1125
u8 framesyncMonitor;
1126
//Added by amy 080516 for RX related
1128
u8 nrxAMPDU_aggr_num;
1133
//by amy for reset_count
1137
u32 txpower_checkcnt;
1138
u32 txpower_tracking_callback_cnt;
1139
u8 thermal_read_val[40];
1140
u8 thermal_readback_index;
1141
u32 ccktxpower_adjustcnt_not_ch14;
1142
u32 ccktxpower_adjustcnt_ch14;
1143
u8 tx_fwinfo_force_subcarriermode;
1144
u8 tx_fwinfo_force_subcarrierval;
1145
//by amy for silent reset
1146
RESET_TYPE ResetProgress;
1147
bool bForcedSilentReset;
1148
bool bDisableNormalResetCheck;
1151
int IrpPendingCount;
1152
bool bResetInProgress;
1154
u8 InitialGainOperateType;
1158
//define work item by amy 080526
1160
struct delayed_work update_beacon_wq;
1161
struct delayed_work watch_dog_wq;
1162
struct delayed_work txpower_tracking_wq;
1163
struct delayed_work rfpath_check_wq;
1164
struct delayed_work gpio_change_rf_wq;
1165
struct delayed_work initialgain_operate_wq;
1166
struct workqueue_struct *priv_wq;
1170
// now mirging to rtl8187B
1173
LOW_PRIORITY = 0x02,
1179
BULK_PRIORITY = 0x01,
1190
BEACON_PRIORITY, //0x0A
1195
UART_PRIORITY //0x0F
1206
struct ssid_thread {
1207
struct net_device *dev;
1208
u8 name[IW_ESSID_MAX_SIZE + 1];
1212
bool init_firmware(struct net_device *dev);
1213
short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1214
short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1216
u32 read_cam(struct net_device *dev, u8 addr);
1217
void write_cam(struct net_device *dev, u8 addr, u32 data);
1219
u8 read_nic_byte(struct net_device *dev, int x);
1220
u8 read_nic_byte_E(struct net_device *dev, int x);
1221
u32 read_nic_dword(struct net_device *dev, int x);
1222
u16 read_nic_word(struct net_device *dev, int x) ;
1223
void write_nic_byte(struct net_device *dev, int x,u8 y);
1224
void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1225
void write_nic_word(struct net_device *dev, int x,u16 y);
1226
void write_nic_dword(struct net_device *dev, int x,u32 y);
1227
void force_pci_posting(struct net_device *dev);
1229
void rtl8192_rtx_disable(struct net_device *);
1230
void rtl8192_rx_enable(struct net_device *);
1231
void rtl8192_tx_enable(struct net_device *);
1233
void rtl8192_disassociate(struct net_device *dev);
1234
//void fix_rx_fifo(struct net_device *dev);
1235
void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1237
void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1238
void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1239
void rtl8192_update_msr(struct net_device *dev);
1240
int rtl8192_down(struct net_device *dev);
1241
int rtl8192_up(struct net_device *dev);
1242
void rtl8192_commit(struct net_device *dev);
1243
void rtl8192_set_chan(struct net_device *dev,short ch);
1244
void write_phy(struct net_device *dev, u8 adr, u8 data);
1245
void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1246
void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1247
void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1248
void rtl8192_set_rxconf(struct net_device *dev);
1249
//short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1250
extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate);
1252
void EnableHWSecurityConfig8192(struct net_device *dev);
1253
void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );