2
* linux/arch/alpha/kernel/core_wildfire.c
6
* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
9
#define __EXTERN_INLINE inline
11
#include <asm/core_wildfire.h>
12
#undef __EXTERN_INLINE
14
#include <linux/types.h>
15
#include <linux/pci.h>
16
#include <linux/sched.h>
17
#include <linux/init.h>
19
#include <asm/ptrace.h>
25
#define DEBUG_CONFIG 0
26
#define DEBUG_DUMP_REGS 0
27
#define DEBUG_DUMP_CONFIG 1
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# define DBG_CFG(args) printk args
32
# define DBG_CFG(args)
36
static void wildfire_dump_pci_regs(int qbbno, int hoseno);
37
static void wildfire_dump_pca_regs(int qbbno, int pcano);
38
static void wildfire_dump_qsa_regs(int qbbno);
39
static void wildfire_dump_qsd_regs(int qbbno);
40
static void wildfire_dump_iop_regs(int qbbno);
41
static void wildfire_dump_gp_regs(int qbbno);
44
static void wildfire_dump_hardware_config(void);
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unsigned char wildfire_hard_qbb_map[WILDFIRE_MAX_QBB];
48
unsigned char wildfire_soft_qbb_map[WILDFIRE_MAX_QBB];
49
#define QBB_MAP_EMPTY 0xff
51
unsigned long wildfire_hard_qbb_mask;
52
unsigned long wildfire_soft_qbb_mask;
53
unsigned long wildfire_gp_mask;
54
unsigned long wildfire_hs_mask;
55
unsigned long wildfire_iop_mask;
56
unsigned long wildfire_ior_mask;
57
unsigned long wildfire_pca_mask;
58
unsigned long wildfire_cpu_mask;
59
unsigned long wildfire_mem_mask;
62
wildfire_init_hose(int qbbno, int hoseno)
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struct pci_controller *hose;
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hose = alloc_pci_controller();
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hose->io_space = alloc_resource();
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hose->mem_space = alloc_resource();
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/* This is for userland consumption. */
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hose->sparse_mem_base = 0;
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hose->sparse_io_base = 0;
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hose->dense_mem_base = WILDFIRE_MEM(qbbno, hoseno);
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hose->dense_io_base = WILDFIRE_IO(qbbno, hoseno);
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hose->config_space_base = WILDFIRE_CONF(qbbno, hoseno);
78
hose->index = (qbbno << 3) + hoseno;
80
hose->io_space->start = WILDFIRE_IO(qbbno, hoseno) - WILDFIRE_IO_BIAS;
81
hose->io_space->end = hose->io_space->start + WILDFIRE_IO_SPACE - 1;
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hose->io_space->name = pci_io_names[hoseno];
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hose->io_space->flags = IORESOURCE_IO;
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hose->mem_space->start = WILDFIRE_MEM(qbbno, hoseno)-WILDFIRE_MEM_BIAS;
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hose->mem_space->end = hose->mem_space->start + 0xffffffff;
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hose->mem_space->name = pci_mem_names[hoseno];
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hose->mem_space->flags = IORESOURCE_MEM;
90
if (request_resource(&ioport_resource, hose->io_space) < 0)
91
printk(KERN_ERR "Failed to request IO on qbb %d hose %d\n",
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if (request_resource(&iomem_resource, hose->mem_space) < 0)
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printk(KERN_ERR "Failed to request MEM on qbb %d hose %d\n",
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wildfire_dump_pci_regs(qbbno, hoseno);
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* Set up the PCI to main memory translation windows.
104
* Note: Window 3 is scatter-gather only
106
* Window 0 is scatter-gather 8MB at 8MB (for isa)
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* Window 1 is direct access 1GB at 1GB
108
* Window 2 is direct access 1GB at 2GB
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* Window 3 is scatter-gather 128MB at 3GB
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* ??? We ought to scale window 3 memory.
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hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
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hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x08000000, 0);
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pci = WILDFIRE_pci(qbbno, hoseno);
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pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3;
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pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000;
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pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes);
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pci->pci_window[1].wbase.csr = 0x40000000 | 1;
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pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000;
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pci->pci_window[1].tbase.csr = 0;
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pci->pci_window[2].wbase.csr = 0x80000000 | 1;
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pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000;
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pci->pci_window[2].tbase.csr = 0x40000000;
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pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3;
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pci->pci_window[3].wmask.csr = (hose->sg_pci->size - 1) & 0xfff00000;
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pci->pci_window[3].tbase.csr = virt_to_phys(hose->sg_pci->ptes);
134
wildfire_pci_tbi(hose, 0, 0); /* Flush TLB at the end. */
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wildfire_init_pca(int qbbno, int pcano)
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/* Test for PCA existence first. */
142
if (!WILDFIRE_PCA_EXISTS(qbbno, pcano))
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wildfire_dump_pca_regs(qbbno, pcano);
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/* Do both hoses of the PCA. */
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wildfire_init_hose(qbbno, (pcano << 1) + 0);
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wildfire_init_hose(qbbno, (pcano << 1) + 1);
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wildfire_init_qbb(int qbbno)
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/* Test for QBB existence first. */
160
if (!WILDFIRE_QBB_EXISTS(qbbno))
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wildfire_dump_qsa_regs(qbbno);
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wildfire_dump_qsd_regs(qbbno);
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wildfire_dump_iop_regs(qbbno);
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wildfire_dump_gp_regs(qbbno);
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/* Init all PCAs here. */
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for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) {
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wildfire_init_pca(qbbno, pcano);
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wildfire_hardware_probe(void)
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unsigned int hard_qbb, soft_qbb;
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wildfire_fast_qsd *fast = WILDFIRE_fast_qsd();
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temp = fast->qsd_whami.csr;
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printk(KERN_ERR "fast QSD_WHAMI at base %p is 0x%lx\n", fast, temp);
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hard_qbb = (temp >> 8) & 7;
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soft_qbb = (temp >> 4) & 7;
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/* Init the HW configuration variables. */
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wildfire_hard_qbb_mask = (1 << hard_qbb);
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wildfire_soft_qbb_mask = (1 << soft_qbb);
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wildfire_gp_mask = 0;
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wildfire_hs_mask = 0;
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wildfire_iop_mask = 0;
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wildfire_ior_mask = 0;
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wildfire_pca_mask = 0;
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wildfire_cpu_mask = 0;
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wildfire_mem_mask = 0;
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memset(wildfire_hard_qbb_map, QBB_MAP_EMPTY, WILDFIRE_MAX_QBB);
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memset(wildfire_soft_qbb_map, QBB_MAP_EMPTY, WILDFIRE_MAX_QBB);
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/* First, determine which QBBs are present. */
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qsa = WILDFIRE_qsa(soft_qbb);
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temp = qsa->qsa_qbb_id.csr;
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printk(KERN_ERR "QSA_QBB_ID at base %p is 0x%lx\n", qsa, temp);
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if (temp & 0x40) /* Is there an HS? */
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wildfire_hs_mask = 1;
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if (temp & 0x20) { /* Is there a GP? */
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gp = WILDFIRE_gp(soft_qbb);
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for (i = 0; i < 4; i++) {
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temp |= gp->gpa_qbb_map[i].csr << (i * 8);
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printk(KERN_ERR "GPA_QBB_MAP[%d] at base %p is 0x%lx\n",
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for (hard_qbb = 0; hard_qbb < WILDFIRE_MAX_QBB; hard_qbb++) {
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if (temp & 8) { /* Is there a QBB? */
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wildfire_hard_qbb_mask |= (1 << hard_qbb);
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wildfire_soft_qbb_mask |= (1 << soft_qbb);
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wildfire_gp_mask = wildfire_soft_qbb_mask;
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/* Next determine each QBBs resources. */
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for (soft_qbb = 0; soft_qbb < WILDFIRE_MAX_QBB; soft_qbb++) {
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if (WILDFIRE_QBB_EXISTS(soft_qbb)) {
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qsd = WILDFIRE_qsd(soft_qbb);
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temp = qsd->qsd_whami.csr;
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printk(KERN_ERR "QSD_WHAMI at base %p is 0x%lx\n", qsd, temp);
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hard_qbb = (temp >> 8) & 7;
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wildfire_hard_qbb_map[hard_qbb] = soft_qbb;
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wildfire_soft_qbb_map[soft_qbb] = hard_qbb;
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qsa = WILDFIRE_qsa(soft_qbb);
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temp = qsa->qsa_qbb_pop[0].csr;
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printk(KERN_ERR "QSA_QBB_POP_0 at base %p is 0x%lx\n", qsa, temp);
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wildfire_cpu_mask |= ((temp >> 0) & 0xf) << (soft_qbb << 2);
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wildfire_mem_mask |= ((temp >> 4) & 0xf) << (soft_qbb << 2);
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temp = qsa->qsa_qbb_pop[1].csr;
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printk(KERN_ERR "QSA_QBB_POP_1 at base %p is 0x%lx\n", qsa, temp);
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wildfire_iop_mask |= (1 << soft_qbb);
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wildfire_ior_mask |= ((temp >> 4) & 0xf) << (soft_qbb << 2);
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temp = qsa->qsa_qbb_id.csr;
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printk(KERN_ERR "QSA_QBB_ID at %p is 0x%lx\n", qsa, temp);
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wildfire_gp_mask |= (1 << soft_qbb);
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/* Probe for PCA existence here. */
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for (i = 0; i < WILDFIRE_PCA_PER_QBB; i++) {
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iop = WILDFIRE_iop(soft_qbb);
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ne = WILDFIRE_ne(soft_qbb, i);
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fe = WILDFIRE_fe(soft_qbb, i);
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if ((iop->iop_hose[i].init.csr & 1) == 1 &&
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((ne->ne_what_am_i.csr & 0xf00000300UL) == 0x100000300UL) &&
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((fe->fe_what_am_i.csr & 0xf00000300UL) == 0x100000200UL))
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wildfire_pca_mask |= 1 << ((soft_qbb << 2) + i);
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#if DEBUG_DUMP_CONFIG
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wildfire_dump_hardware_config();
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wildfire_init_arch(void)
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/* With multiple PCI buses, we play with I/O as physical addrs. */
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ioport_resource.end = ~0UL;
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/* Probe the hardware for info about configuration. */
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wildfire_hardware_probe();
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/* Now init all the found QBBs. */
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for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) {
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wildfire_init_qbb(qbbno);
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/* Normal direct PCI DMA mapping. */
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__direct_map_base = 0x40000000UL;
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__direct_map_size = 0x80000000UL;
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wildfire_machine_check(unsigned long vector, unsigned long la_ptr)
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/* FIXME: clear pci errors */
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process_mcheck_info(vector, la_ptr, "WILDFIRE",
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mcheck_expected(smp_processor_id()));
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wildfire_kill_arch(int mode)
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wildfire_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
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int qbbno = hose->index >> 3;
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int hoseno = hose->index & 7;
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wildfire_pci *pci = WILDFIRE_pci(qbbno, hoseno);
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pci->pci_flush_tlb.csr; /* reading does the trick */
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr, unsigned char *type1)
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struct pci_controller *hose = pbus->sysdata;
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u8 bus = pbus->number;
362
DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
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"pci_addr=0x%p, type1=0x%p)\n",
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bus, device_fn, where, pci_addr, type1));
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if (!pbus->parent) /* No parent means peer PCI bus. */
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addr = (bus << 16) | (device_fn << 8) | where;
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addr |= hose->config_space_base;
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DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
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wildfire_read_config(struct pci_bus *bus, unsigned int devfn, int where,
380
int size, u32 *value)
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
386
return PCIBIOS_DEVICE_NOT_FOUND;
390
*value = __kernel_ldbu(*(vucp)addr);
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*value = __kernel_ldwu(*(vusp)addr);
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*value = *(vuip)addr;
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return PCIBIOS_SUCCESSFUL;
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wildfire_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
411
return PCIBIOS_DEVICE_NOT_FOUND;
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__kernel_stb(value, *(vucp)addr);
417
__kernel_ldbu(*(vucp)addr);
420
__kernel_stw(value, *(vusp)addr);
422
__kernel_ldwu(*(vusp)addr);
431
return PCIBIOS_SUCCESSFUL;
434
struct pci_ops wildfire_pci_ops =
436
.read = wildfire_read_config,
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.write = wildfire_write_config,
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int wildfire_pa_to_nid(unsigned long pa)
449
int wildfire_cpuid_to_nid(int cpuid)
451
/* assume 4 CPUs per node */
455
unsigned long wildfire_node_mem_start(int nid)
458
return (unsigned long)nid * (64UL * 1024 * 1024 * 1024);
461
unsigned long wildfire_node_mem_size(int nid)
464
return 64UL * 1024 * 1024 * 1024;
470
wildfire_dump_pci_regs(int qbbno, int hoseno)
472
wildfire_pci *pci = WILDFIRE_pci(qbbno, hoseno);
475
printk(KERN_ERR "PCI registers for QBB %d hose %d (%p)\n",
478
printk(KERN_ERR " PCI_IO_ADDR_EXT: 0x%16lx\n",
479
pci->pci_io_addr_ext.csr);
480
printk(KERN_ERR " PCI_CTRL: 0x%16lx\n", pci->pci_ctrl.csr);
481
printk(KERN_ERR " PCI_ERR_SUM: 0x%16lx\n", pci->pci_err_sum.csr);
482
printk(KERN_ERR " PCI_ERR_ADDR: 0x%16lx\n", pci->pci_err_addr.csr);
483
printk(KERN_ERR " PCI_STALL_CNT: 0x%16lx\n", pci->pci_stall_cnt.csr);
484
printk(KERN_ERR " PCI_PEND_INT: 0x%16lx\n", pci->pci_pend_int.csr);
485
printk(KERN_ERR " PCI_SENT_INT: 0x%16lx\n", pci->pci_sent_int.csr);
487
printk(KERN_ERR " DMA window registers for QBB %d hose %d (%p)\n",
489
for (i = 0; i < 4; i++) {
490
printk(KERN_ERR " window %d: 0x%16lx 0x%16lx 0x%16lx\n", i,
491
pci->pci_window[i].wbase.csr,
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pci->pci_window[i].wmask.csr,
493
pci->pci_window[i].tbase.csr);
495
printk(KERN_ERR "\n");
499
wildfire_dump_pca_regs(int qbbno, int pcano)
501
wildfire_pca *pca = WILDFIRE_pca(qbbno, pcano);
504
printk(KERN_ERR "PCA registers for QBB %d PCA %d (%p)\n",
507
printk(KERN_ERR " PCA_WHAT_AM_I: 0x%16lx\n", pca->pca_what_am_i.csr);
508
printk(KERN_ERR " PCA_ERR_SUM: 0x%16lx\n", pca->pca_err_sum.csr);
509
printk(KERN_ERR " PCA_PEND_INT: 0x%16lx\n", pca->pca_pend_int.csr);
510
printk(KERN_ERR " PCA_SENT_INT: 0x%16lx\n", pca->pca_sent_int.csr);
511
printk(KERN_ERR " PCA_STDIO_EL: 0x%16lx\n",
512
pca->pca_stdio_edge_level.csr);
514
printk(KERN_ERR " PCA target registers for QBB %d PCA %d (%p)\n",
516
for (i = 0; i < 4; i++) {
517
printk(KERN_ERR " target %d: 0x%16lx 0x%16lx\n", i,
518
pca->pca_int[i].target.csr,
519
pca->pca_int[i].enable.csr);
522
printk(KERN_ERR "\n");
526
wildfire_dump_qsa_regs(int qbbno)
528
wildfire_qsa *qsa = WILDFIRE_qsa(qbbno);
531
printk(KERN_ERR "QSA registers for QBB %d (%p)\n", qbbno, qsa);
533
printk(KERN_ERR " QSA_QBB_ID: 0x%16lx\n", qsa->qsa_qbb_id.csr);
534
printk(KERN_ERR " QSA_PORT_ENA: 0x%16lx\n", qsa->qsa_port_ena.csr);
535
printk(KERN_ERR " QSA_REF_INT: 0x%16lx\n", qsa->qsa_ref_int.csr);
537
for (i = 0; i < 5; i++)
538
printk(KERN_ERR " QSA_CONFIG_%d: 0x%16lx\n",
539
i, qsa->qsa_config[i].csr);
541
for (i = 0; i < 2; i++)
542
printk(KERN_ERR " QSA_QBB_POP_%d: 0x%16lx\n",
543
i, qsa->qsa_qbb_pop[0].csr);
545
printk(KERN_ERR "\n");
549
wildfire_dump_qsd_regs(int qbbno)
551
wildfire_qsd *qsd = WILDFIRE_qsd(qbbno);
553
printk(KERN_ERR "QSD registers for QBB %d (%p)\n", qbbno, qsd);
555
printk(KERN_ERR " QSD_WHAMI: 0x%16lx\n", qsd->qsd_whami.csr);
556
printk(KERN_ERR " QSD_REV: 0x%16lx\n", qsd->qsd_rev.csr);
557
printk(KERN_ERR " QSD_PORT_PRESENT: 0x%16lx\n",
558
qsd->qsd_port_present.csr);
559
printk(KERN_ERR " QSD_PORT_ACTUVE: 0x%16lx\n",
560
qsd->qsd_port_active.csr);
561
printk(KERN_ERR " QSD_FAULT_ENA: 0x%16lx\n",
562
qsd->qsd_fault_ena.csr);
563
printk(KERN_ERR " QSD_CPU_INT_ENA: 0x%16lx\n",
564
qsd->qsd_cpu_int_ena.csr);
565
printk(KERN_ERR " QSD_MEM_CONFIG: 0x%16lx\n",
566
qsd->qsd_mem_config.csr);
567
printk(KERN_ERR " QSD_ERR_SUM: 0x%16lx\n",
568
qsd->qsd_err_sum.csr);
570
printk(KERN_ERR "\n");
574
wildfire_dump_iop_regs(int qbbno)
576
wildfire_iop *iop = WILDFIRE_iop(qbbno);
579
printk(KERN_ERR "IOP registers for QBB %d (%p)\n", qbbno, iop);
581
printk(KERN_ERR " IOA_CONFIG: 0x%16lx\n", iop->ioa_config.csr);
582
printk(KERN_ERR " IOD_CONFIG: 0x%16lx\n", iop->iod_config.csr);
583
printk(KERN_ERR " IOP_SWITCH_CREDITS: 0x%16lx\n",
584
iop->iop_switch_credits.csr);
585
printk(KERN_ERR " IOP_HOSE_CREDITS: 0x%16lx\n",
586
iop->iop_hose_credits.csr);
588
for (i = 0; i < 4; i++)
589
printk(KERN_ERR " IOP_HOSE_%d_INIT: 0x%16lx\n",
590
i, iop->iop_hose[i].init.csr);
591
for (i = 0; i < 4; i++)
592
printk(KERN_ERR " IOP_DEV_INT_TARGET_%d: 0x%16lx\n",
593
i, iop->iop_dev_int[i].target.csr);
595
printk(KERN_ERR "\n");
599
wildfire_dump_gp_regs(int qbbno)
601
wildfire_gp *gp = WILDFIRE_gp(qbbno);
604
printk(KERN_ERR "GP registers for QBB %d (%p)\n", qbbno, gp);
605
for (i = 0; i < 4; i++)
606
printk(KERN_ERR " GPA_QBB_MAP_%d: 0x%16lx\n",
607
i, gp->gpa_qbb_map[i].csr);
609
printk(KERN_ERR " GPA_MEM_POP_MAP: 0x%16lx\n",
610
gp->gpa_mem_pop_map.csr);
611
printk(KERN_ERR " GPA_SCRATCH: 0x%16lx\n", gp->gpa_scratch.csr);
612
printk(KERN_ERR " GPA_DIAG: 0x%16lx\n", gp->gpa_diag.csr);
613
printk(KERN_ERR " GPA_CONFIG_0: 0x%16lx\n", gp->gpa_config_0.csr);
614
printk(KERN_ERR " GPA_INIT_ID: 0x%16lx\n", gp->gpa_init_id.csr);
615
printk(KERN_ERR " GPA_CONFIG_2: 0x%16lx\n", gp->gpa_config_2.csr);
617
printk(KERN_ERR "\n");
619
#endif /* DUMP_REGS */
621
#if DEBUG_DUMP_CONFIG
623
wildfire_dump_hardware_config(void)
627
printk(KERN_ERR "Probed Hardware Configuration\n");
629
printk(KERN_ERR " hard_qbb_mask: 0x%16lx\n", wildfire_hard_qbb_mask);
630
printk(KERN_ERR " soft_qbb_mask: 0x%16lx\n", wildfire_soft_qbb_mask);
632
printk(KERN_ERR " gp_mask: 0x%16lx\n", wildfire_gp_mask);
633
printk(KERN_ERR " hs_mask: 0x%16lx\n", wildfire_hs_mask);
634
printk(KERN_ERR " iop_mask: 0x%16lx\n", wildfire_iop_mask);
635
printk(KERN_ERR " ior_mask: 0x%16lx\n", wildfire_ior_mask);
636
printk(KERN_ERR " pca_mask: 0x%16lx\n", wildfire_pca_mask);
638
printk(KERN_ERR " cpu_mask: 0x%16lx\n", wildfire_cpu_mask);
639
printk(KERN_ERR " mem_mask: 0x%16lx\n", wildfire_mem_mask);
641
printk(" hard_qbb_map: ");
642
for (i = 0; i < WILDFIRE_MAX_QBB; i++)
643
if (wildfire_hard_qbb_map[i] == QBB_MAP_EMPTY)
646
printk("%3d ", wildfire_hard_qbb_map[i]);
649
printk(" soft_qbb_map: ");
650
for (i = 0; i < WILDFIRE_MAX_QBB; i++)
651
if (wildfire_soft_qbb_map[i] == QBB_MAP_EMPTY)
654
printk("%3d ", wildfire_soft_qbb_map[i]);
657
#endif /* DUMP_CONFIG */