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* include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994
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* Copyright 2009 Wolfson Microelectronics PLC.
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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#ifndef __MFD_WM8994_REGISTERS_H__
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#define __MFD_WM8994_REGISTERS_H__
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#define WM8994_SOFTWARE_RESET 0x00
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#define WM8994_POWER_MANAGEMENT_1 0x01
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#define WM8994_POWER_MANAGEMENT_2 0x02
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#define WM8994_POWER_MANAGEMENT_3 0x03
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#define WM8994_POWER_MANAGEMENT_4 0x04
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#define WM8994_POWER_MANAGEMENT_5 0x05
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#define WM8994_POWER_MANAGEMENT_6 0x06
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#define WM8994_INPUT_MIXER_1 0x15
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#define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18
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#define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19
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#define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
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#define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
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#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
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#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
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#define WM8994_LINE_OUTPUTS_VOLUME 0x1E
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#define WM8994_HPOUT2_VOLUME 0x1F
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#define WM8994_LEFT_OPGA_VOLUME 0x20
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#define WM8994_RIGHT_OPGA_VOLUME 0x21
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#define WM8994_SPKMIXL_ATTENUATION 0x22
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#define WM8994_SPKMIXR_ATTENUATION 0x23
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#define WM8994_SPKOUT_MIXERS 0x24
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#define WM8994_CLASSD 0x25
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#define WM8994_SPEAKER_VOLUME_LEFT 0x26
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#define WM8994_SPEAKER_VOLUME_RIGHT 0x27
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#define WM8994_INPUT_MIXER_2 0x28
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#define WM8994_INPUT_MIXER_3 0x29
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#define WM8994_INPUT_MIXER_4 0x2A
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#define WM8994_INPUT_MIXER_5 0x2B
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#define WM8994_INPUT_MIXER_6 0x2C
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#define WM8994_OUTPUT_MIXER_1 0x2D
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#define WM8994_OUTPUT_MIXER_2 0x2E
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#define WM8994_OUTPUT_MIXER_3 0x2F
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#define WM8994_OUTPUT_MIXER_4 0x30
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#define WM8994_OUTPUT_MIXER_5 0x31
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#define WM8994_OUTPUT_MIXER_6 0x32
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#define WM8994_HPOUT2_MIXER 0x33
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#define WM8994_LINE_MIXER_1 0x34
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#define WM8994_LINE_MIXER_2 0x35
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#define WM8994_SPEAKER_MIXER 0x36
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#define WM8994_ADDITIONAL_CONTROL 0x37
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#define WM8994_ANTIPOP_1 0x38
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#define WM8994_ANTIPOP_2 0x39
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#define WM8994_MICBIAS 0x3A
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#define WM8994_LDO_1 0x3B
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#define WM8994_LDO_2 0x3C
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#define WM8958_MICBIAS1 0x3D
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#define WM8958_MICBIAS2 0x3E
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#define WM8994_CHARGE_PUMP_1 0x4C
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#define WM8958_CHARGE_PUMP_2 0x4D
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#define WM8994_CLASS_W_1 0x51
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#define WM8994_DC_SERVO_1 0x54
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#define WM8994_DC_SERVO_2 0x55
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#define WM8994_DC_SERVO_4 0x57
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#define WM8994_DC_SERVO_READBACK 0x58
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#define WM8994_DC_SERVO_4E 0x59
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#define WM8994_ANALOGUE_HP_1 0x60
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#define WM8958_MIC_DETECT_1 0xD0
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#define WM8958_MIC_DETECT_2 0xD1
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#define WM8958_MIC_DETECT_3 0xD2
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#define WM8994_CHIP_REVISION 0x100
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#define WM8994_CONTROL_INTERFACE 0x101
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#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110
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#define WM8994_WRITE_SEQUENCER_CTRL_2 0x111
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#define WM8994_AIF1_CLOCKING_1 0x200
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#define WM8994_AIF1_CLOCKING_2 0x201
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#define WM8994_AIF2_CLOCKING_1 0x204
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#define WM8994_AIF2_CLOCKING_2 0x205
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#define WM8994_CLOCKING_1 0x208
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#define WM8994_CLOCKING_2 0x209
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#define WM8994_AIF1_RATE 0x210
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#define WM8994_AIF2_RATE 0x211
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#define WM8994_RATE_STATUS 0x212
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#define WM8994_FLL1_CONTROL_1 0x220
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#define WM8994_FLL1_CONTROL_2 0x221
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#define WM8994_FLL1_CONTROL_3 0x222
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#define WM8994_FLL1_CONTROL_4 0x223
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#define WM8994_FLL1_CONTROL_5 0x224
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#define WM8994_FLL2_CONTROL_1 0x240
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#define WM8994_FLL2_CONTROL_2 0x241
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#define WM8994_FLL2_CONTROL_3 0x242
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#define WM8994_FLL2_CONTROL_4 0x243
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#define WM8994_FLL2_CONTROL_5 0x244
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#define WM8994_AIF1_CONTROL_1 0x300
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#define WM8994_AIF1_CONTROL_2 0x301
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#define WM8994_AIF1_MASTER_SLAVE 0x302
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#define WM8994_AIF1_BCLK 0x303
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#define WM8994_AIF1ADC_LRCLK 0x304
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#define WM8994_AIF1DAC_LRCLK 0x305
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#define WM8994_AIF1DAC_DATA 0x306
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#define WM8994_AIF1ADC_DATA 0x307
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#define WM8994_AIF2_CONTROL_1 0x310
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#define WM8994_AIF2_CONTROL_2 0x311
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#define WM8994_AIF2_MASTER_SLAVE 0x312
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#define WM8994_AIF2_BCLK 0x313
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#define WM8994_AIF2ADC_LRCLK 0x314
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#define WM8994_AIF2DAC_LRCLK 0x315
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#define WM8994_AIF2DAC_DATA 0x316
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#define WM8994_AIF2ADC_DATA 0x317
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#define WM8958_AIF3_CONTROL_1 0x320
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#define WM8958_AIF3_CONTROL_2 0x321
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#define WM8958_AIF3DAC_DATA 0x322
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#define WM8958_AIF3ADC_DATA 0x323
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#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400
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#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401
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#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402
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#define WM8994_AIF1_DAC1_RIGHT_VOLUME 0x403
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#define WM8994_AIF1_ADC2_LEFT_VOLUME 0x404
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#define WM8994_AIF1_ADC2_RIGHT_VOLUME 0x405
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#define WM8994_AIF1_DAC2_LEFT_VOLUME 0x406
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#define WM8994_AIF1_DAC2_RIGHT_VOLUME 0x407
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#define WM8994_AIF1_ADC1_FILTERS 0x410
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#define WM8994_AIF1_ADC2_FILTERS 0x411
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#define WM8994_AIF1_DAC1_FILTERS_1 0x420
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#define WM8994_AIF1_DAC1_FILTERS_2 0x421
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#define WM8994_AIF1_DAC2_FILTERS_1 0x422
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#define WM8994_AIF1_DAC2_FILTERS_2 0x423
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#define WM8958_AIF1_DAC1_NOISE_GATE 0x430
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#define WM8958_AIF1_DAC2_NOISE_GATE 0x431
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#define WM8994_AIF1_DRC1_1 0x440
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#define WM8994_AIF1_DRC1_2 0x441
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#define WM8994_AIF1_DRC1_3 0x442
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#define WM8994_AIF1_DRC1_4 0x443
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#define WM8994_AIF1_DRC1_5 0x444
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#define WM8994_AIF1_DRC2_1 0x450
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#define WM8994_AIF1_DRC2_2 0x451
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#define WM8994_AIF1_DRC2_3 0x452
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#define WM8994_AIF1_DRC2_4 0x453
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#define WM8994_AIF1_DRC2_5 0x454
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#define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480
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#define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481
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#define WM8994_AIF1_DAC1_EQ_BAND_1_A 0x482
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#define WM8994_AIF1_DAC1_EQ_BAND_1_B 0x483
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#define WM8994_AIF1_DAC1_EQ_BAND_1_PG 0x484
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#define WM8994_AIF1_DAC1_EQ_BAND_2_A 0x485
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#define WM8994_AIF1_DAC1_EQ_BAND_2_B 0x486
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#define WM8994_AIF1_DAC1_EQ_BAND_2_C 0x487
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#define WM8994_AIF1_DAC1_EQ_BAND_2_PG 0x488
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#define WM8994_AIF1_DAC1_EQ_BAND_3_A 0x489
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#define WM8994_AIF1_DAC1_EQ_BAND_3_B 0x48A
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#define WM8994_AIF1_DAC1_EQ_BAND_3_C 0x48B
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#define WM8994_AIF1_DAC1_EQ_BAND_3_PG 0x48C
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#define WM8994_AIF1_DAC1_EQ_BAND_4_A 0x48D
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#define WM8994_AIF1_DAC1_EQ_BAND_4_B 0x48E
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#define WM8994_AIF1_DAC1_EQ_BAND_4_C 0x48F
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#define WM8994_AIF1_DAC1_EQ_BAND_4_PG 0x490
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#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491
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#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492
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#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493
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#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0
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#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1
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#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2
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#define WM8994_AIF1_DAC2_EQ_BAND_1_B 0x4A3
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#define WM8994_AIF1_DAC2_EQ_BAND_1_PG 0x4A4
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#define WM8994_AIF1_DAC2_EQ_BAND_2_A 0x4A5
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#define WM8994_AIF1_DAC2_EQ_BAND_2_B 0x4A6
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#define WM8994_AIF1_DAC2_EQ_BAND_2_C 0x4A7
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#define WM8994_AIF1_DAC2_EQ_BAND_2_PG 0x4A8
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#define WM8994_AIF1_DAC2_EQ_BAND_3_A 0x4A9
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#define WM8994_AIF1_DAC2_EQ_BAND_3_B 0x4AA
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#define WM8994_AIF1_DAC2_EQ_BAND_3_C 0x4AB
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#define WM8994_AIF1_DAC2_EQ_BAND_3_PG 0x4AC
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#define WM8994_AIF1_DAC2_EQ_BAND_4_A 0x4AD
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#define WM8994_AIF1_DAC2_EQ_BAND_4_B 0x4AE
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#define WM8994_AIF1_DAC2_EQ_BAND_4_C 0x4AF
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#define WM8994_AIF1_DAC2_EQ_BAND_4_PG 0x4B0
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#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1
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#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2
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#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
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#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500
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#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501
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#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
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#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
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#define WM8994_AIF2_ADC_FILTERS 0x510
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#define WM8994_AIF2_DAC_FILTERS_1 0x520
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#define WM8994_AIF2_DAC_FILTERS_2 0x521
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#define WM8958_AIF2_DAC_NOISE_GATE 0x530
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#define WM8994_AIF2_DRC_1 0x540
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#define WM8994_AIF2_DRC_2 0x541
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#define WM8994_AIF2_DRC_3 0x542
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#define WM8994_AIF2_DRC_4 0x543
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#define WM8994_AIF2_DRC_5 0x544
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#define WM8994_AIF2_EQ_GAINS_1 0x580
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#define WM8994_AIF2_EQ_GAINS_2 0x581
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#define WM8994_AIF2_EQ_BAND_1_A 0x582
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#define WM8994_AIF2_EQ_BAND_1_B 0x583
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#define WM8994_AIF2_EQ_BAND_1_PG 0x584
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#define WM8994_AIF2_EQ_BAND_2_A 0x585
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#define WM8994_AIF2_EQ_BAND_2_B 0x586
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#define WM8994_AIF2_EQ_BAND_2_C 0x587
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#define WM8994_AIF2_EQ_BAND_2_PG 0x588
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#define WM8994_AIF2_EQ_BAND_3_A 0x589
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#define WM8994_AIF2_EQ_BAND_3_B 0x58A
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#define WM8994_AIF2_EQ_BAND_3_C 0x58B
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#define WM8994_AIF2_EQ_BAND_3_PG 0x58C
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#define WM8994_AIF2_EQ_BAND_4_A 0x58D
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#define WM8994_AIF2_EQ_BAND_4_B 0x58E
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#define WM8994_AIF2_EQ_BAND_4_C 0x58F
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#define WM8994_AIF2_EQ_BAND_4_PG 0x590
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#define WM8994_AIF2_EQ_BAND_5_A 0x591
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#define WM8994_AIF2_EQ_BAND_5_B 0x592
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#define WM8994_AIF2_EQ_BAND_5_PG 0x593
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#define WM8994_DAC1_MIXER_VOLUMES 0x600
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#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
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#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
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#define WM8994_DAC2_MIXER_VOLUMES 0x603
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#define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604
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#define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605
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#define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606
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#define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607
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#define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608
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#define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609
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#define WM8994_DAC1_LEFT_VOLUME 0x610
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#define WM8994_DAC1_RIGHT_VOLUME 0x611
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#define WM8994_DAC2_LEFT_VOLUME 0x612
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#define WM8994_DAC2_RIGHT_VOLUME 0x613
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#define WM8994_DAC_SOFTMUTE 0x614
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#define WM8994_OVERSAMPLING 0x620
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#define WM8994_SIDETONE 0x621
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#define WM8994_GPIO_1 0x700
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#define WM8994_GPIO_2 0x701
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#define WM8994_GPIO_3 0x702
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#define WM8994_GPIO_4 0x703
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#define WM8994_GPIO_5 0x704
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#define WM8994_GPIO_6 0x705
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#define WM8994_GPIO_7 0x706
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#define WM8994_GPIO_8 0x707
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#define WM8994_GPIO_9 0x708
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#define WM8994_GPIO_10 0x709
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#define WM8994_GPIO_11 0x70A
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#define WM8994_PULL_CONTROL_1 0x720
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#define WM8994_PULL_CONTROL_2 0x721
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#define WM8994_INTERRUPT_STATUS_1 0x730
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#define WM8994_INTERRUPT_STATUS_2 0x731
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#define WM8994_INTERRUPT_RAW_STATUS_2 0x732
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#define WM8994_INTERRUPT_STATUS_1_MASK 0x738
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#define WM8994_INTERRUPT_STATUS_2_MASK 0x739
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#define WM8994_INTERRUPT_CONTROL 0x740
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#define WM8994_IRQ_DEBOUNCE 0x748
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#define WM8958_DSP2_PROGRAM 0x900
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#define WM8958_DSP2_CONFIG 0x901
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#define WM8958_DSP2_MAGICNUM 0xA00
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#define WM8958_DSP2_RELEASEYEAR 0xA01
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#define WM8958_DSP2_RELEASEMONTHDAY 0xA02
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#define WM8958_DSP2_RELEASETIME 0xA03
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#define WM8958_DSP2_VERMAJMIN 0xA04
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#define WM8958_DSP2_VERBUILD 0xA05
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#define WM8958_DSP2_EXECCONTROL 0xA0D
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2 0x2203
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1 0x2204
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2 0x2205
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#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1 0x2206
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#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2 0x2207
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#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1 0x2208
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#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2 0x2209
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#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1 0x220A
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#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2 0x220B
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#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1 0x220C
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#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2 0x220D
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#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1 0x220E
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#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2 0x220F
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#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1 0x2210
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#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2 0x2211
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#define WM8958_MBC_BAND_1_LOWER_CUTOFF_1 0x2212
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#define WM8958_MBC_BAND_1_LOWER_CUTOFF_2 0x2213
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#define WM8958_MBC_BAND_1_K_1 0x2400
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#define WM8958_MBC_BAND_1_K_2 0x2401
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#define WM8958_MBC_BAND_1_N1_1 0x2402
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#define WM8958_MBC_BAND_1_N1_2 0x2403
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#define WM8958_MBC_BAND_1_N2_1 0x2404
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#define WM8958_MBC_BAND_1_N2_2 0x2405
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#define WM8958_MBC_BAND_1_N3_1 0x2406
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#define WM8958_MBC_BAND_1_N3_2 0x2407
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#define WM8958_MBC_BAND_1_N4_1 0x2408
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#define WM8958_MBC_BAND_1_N4_2 0x2409
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#define WM8958_MBC_BAND_1_N5_1 0x240A
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#define WM8958_MBC_BAND_1_N5_2 0x240B
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#define WM8958_MBC_BAND_1_X1_1 0x240C
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#define WM8958_MBC_BAND_1_X1_2 0x240D
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#define WM8958_MBC_BAND_1_X2_1 0x240E
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#define WM8958_MBC_BAND_1_X2_2 0x240F
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#define WM8958_MBC_BAND_1_X3_1 0x2410
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#define WM8958_MBC_BAND_1_X3_2 0x2411
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#define WM8958_MBC_BAND_1_ATTACK_1 0x2412
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#define WM8958_MBC_BAND_1_ATTACK_2 0x2413
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#define WM8958_MBC_BAND_1_DECAY_1 0x2414
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#define WM8958_MBC_BAND_1_DECAY_2 0x2415
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#define WM8958_MBC_BAND_2_K_1 0x2416
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#define WM8958_MBC_BAND_2_K_2 0x2417
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#define WM8958_MBC_BAND_2_N1_1 0x2418
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#define WM8958_MBC_BAND_2_N1_2 0x2419
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#define WM8958_MBC_BAND_2_N2_1 0x241A
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#define WM8958_MBC_BAND_2_N2_2 0x241B
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#define WM8958_MBC_BAND_2_N3_1 0x241C
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#define WM8958_MBC_BAND_2_N3_2 0x241D
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#define WM8958_MBC_BAND_2_N4_1 0x241E
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#define WM8958_MBC_BAND_2_N4_2 0x241F
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#define WM8958_MBC_BAND_2_N5_1 0x2420
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#define WM8958_MBC_BAND_2_N5_2 0x2421
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#define WM8958_MBC_BAND_2_X1_1 0x2422
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#define WM8958_MBC_BAND_2_X1_2 0x2423
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#define WM8958_MBC_BAND_2_X2_1 0x2424
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#define WM8958_MBC_BAND_2_X2_2 0x2425
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#define WM8958_MBC_BAND_2_X3_1 0x2426
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#define WM8958_MBC_BAND_2_X3_2 0x2427
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#define WM8958_MBC_BAND_2_ATTACK_1 0x2428
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#define WM8958_MBC_BAND_2_ATTACK_2 0x2429
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#define WM8958_MBC_BAND_2_DECAY_1 0x242A
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#define WM8958_MBC_BAND_2_DECAY_2 0x242B
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#define WM8958_MBC_B2_PG2_1 0x242C
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#define WM8958_MBC_B2_PG2_2 0x242D
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#define WM8958_MBC_B1_PG2_1 0x242E
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#define WM8958_MBC_B1_PG2_2 0x242F
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#define WM8994_WRITE_SEQUENCER_0 0x3000
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#define WM8994_WRITE_SEQUENCER_1 0x3001
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#define WM8994_WRITE_SEQUENCER_2 0x3002
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#define WM8994_WRITE_SEQUENCER_3 0x3003
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#define WM8994_WRITE_SEQUENCER_4 0x3004
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#define WM8994_WRITE_SEQUENCER_5 0x3005
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#define WM8994_WRITE_SEQUENCER_6 0x3006
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#define WM8994_WRITE_SEQUENCER_7 0x3007
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#define WM8994_WRITE_SEQUENCER_8 0x3008
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#define WM8994_WRITE_SEQUENCER_9 0x3009
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#define WM8994_WRITE_SEQUENCER_10 0x300A
347
#define WM8994_WRITE_SEQUENCER_11 0x300B
348
#define WM8994_WRITE_SEQUENCER_12 0x300C
349
#define WM8994_WRITE_SEQUENCER_13 0x300D
350
#define WM8994_WRITE_SEQUENCER_14 0x300E
351
#define WM8994_WRITE_SEQUENCER_15 0x300F
352
#define WM8994_WRITE_SEQUENCER_16 0x3010
353
#define WM8994_WRITE_SEQUENCER_17 0x3011
354
#define WM8994_WRITE_SEQUENCER_18 0x3012
355
#define WM8994_WRITE_SEQUENCER_19 0x3013
356
#define WM8994_WRITE_SEQUENCER_20 0x3014
357
#define WM8994_WRITE_SEQUENCER_21 0x3015
358
#define WM8994_WRITE_SEQUENCER_22 0x3016
359
#define WM8994_WRITE_SEQUENCER_23 0x3017
360
#define WM8994_WRITE_SEQUENCER_24 0x3018
361
#define WM8994_WRITE_SEQUENCER_25 0x3019
362
#define WM8994_WRITE_SEQUENCER_26 0x301A
363
#define WM8994_WRITE_SEQUENCER_27 0x301B
364
#define WM8994_WRITE_SEQUENCER_28 0x301C
365
#define WM8994_WRITE_SEQUENCER_29 0x301D
366
#define WM8994_WRITE_SEQUENCER_30 0x301E
367
#define WM8994_WRITE_SEQUENCER_31 0x301F
368
#define WM8994_WRITE_SEQUENCER_32 0x3020
369
#define WM8994_WRITE_SEQUENCER_33 0x3021
370
#define WM8994_WRITE_SEQUENCER_34 0x3022
371
#define WM8994_WRITE_SEQUENCER_35 0x3023
372
#define WM8994_WRITE_SEQUENCER_36 0x3024
373
#define WM8994_WRITE_SEQUENCER_37 0x3025
374
#define WM8994_WRITE_SEQUENCER_38 0x3026
375
#define WM8994_WRITE_SEQUENCER_39 0x3027
376
#define WM8994_WRITE_SEQUENCER_40 0x3028
377
#define WM8994_WRITE_SEQUENCER_41 0x3029
378
#define WM8994_WRITE_SEQUENCER_42 0x302A
379
#define WM8994_WRITE_SEQUENCER_43 0x302B
380
#define WM8994_WRITE_SEQUENCER_44 0x302C
381
#define WM8994_WRITE_SEQUENCER_45 0x302D
382
#define WM8994_WRITE_SEQUENCER_46 0x302E
383
#define WM8994_WRITE_SEQUENCER_47 0x302F
384
#define WM8994_WRITE_SEQUENCER_48 0x3030
385
#define WM8994_WRITE_SEQUENCER_49 0x3031
386
#define WM8994_WRITE_SEQUENCER_50 0x3032
387
#define WM8994_WRITE_SEQUENCER_51 0x3033
388
#define WM8994_WRITE_SEQUENCER_52 0x3034
389
#define WM8994_WRITE_SEQUENCER_53 0x3035
390
#define WM8994_WRITE_SEQUENCER_54 0x3036
391
#define WM8994_WRITE_SEQUENCER_55 0x3037
392
#define WM8994_WRITE_SEQUENCER_56 0x3038
393
#define WM8994_WRITE_SEQUENCER_57 0x3039
394
#define WM8994_WRITE_SEQUENCER_58 0x303A
395
#define WM8994_WRITE_SEQUENCER_59 0x303B
396
#define WM8994_WRITE_SEQUENCER_60 0x303C
397
#define WM8994_WRITE_SEQUENCER_61 0x303D
398
#define WM8994_WRITE_SEQUENCER_62 0x303E
399
#define WM8994_WRITE_SEQUENCER_63 0x303F
400
#define WM8994_WRITE_SEQUENCER_64 0x3040
401
#define WM8994_WRITE_SEQUENCER_65 0x3041
402
#define WM8994_WRITE_SEQUENCER_66 0x3042
403
#define WM8994_WRITE_SEQUENCER_67 0x3043
404
#define WM8994_WRITE_SEQUENCER_68 0x3044
405
#define WM8994_WRITE_SEQUENCER_69 0x3045
406
#define WM8994_WRITE_SEQUENCER_70 0x3046
407
#define WM8994_WRITE_SEQUENCER_71 0x3047
408
#define WM8994_WRITE_SEQUENCER_72 0x3048
409
#define WM8994_WRITE_SEQUENCER_73 0x3049
410
#define WM8994_WRITE_SEQUENCER_74 0x304A
411
#define WM8994_WRITE_SEQUENCER_75 0x304B
412
#define WM8994_WRITE_SEQUENCER_76 0x304C
413
#define WM8994_WRITE_SEQUENCER_77 0x304D
414
#define WM8994_WRITE_SEQUENCER_78 0x304E
415
#define WM8994_WRITE_SEQUENCER_79 0x304F
416
#define WM8994_WRITE_SEQUENCER_80 0x3050
417
#define WM8994_WRITE_SEQUENCER_81 0x3051
418
#define WM8994_WRITE_SEQUENCER_82 0x3052
419
#define WM8994_WRITE_SEQUENCER_83 0x3053
420
#define WM8994_WRITE_SEQUENCER_84 0x3054
421
#define WM8994_WRITE_SEQUENCER_85 0x3055
422
#define WM8994_WRITE_SEQUENCER_86 0x3056
423
#define WM8994_WRITE_SEQUENCER_87 0x3057
424
#define WM8994_WRITE_SEQUENCER_88 0x3058
425
#define WM8994_WRITE_SEQUENCER_89 0x3059
426
#define WM8994_WRITE_SEQUENCER_90 0x305A
427
#define WM8994_WRITE_SEQUENCER_91 0x305B
428
#define WM8994_WRITE_SEQUENCER_92 0x305C
429
#define WM8994_WRITE_SEQUENCER_93 0x305D
430
#define WM8994_WRITE_SEQUENCER_94 0x305E
431
#define WM8994_WRITE_SEQUENCER_95 0x305F
432
#define WM8994_WRITE_SEQUENCER_96 0x3060
433
#define WM8994_WRITE_SEQUENCER_97 0x3061
434
#define WM8994_WRITE_SEQUENCER_98 0x3062
435
#define WM8994_WRITE_SEQUENCER_99 0x3063
436
#define WM8994_WRITE_SEQUENCER_100 0x3064
437
#define WM8994_WRITE_SEQUENCER_101 0x3065
438
#define WM8994_WRITE_SEQUENCER_102 0x3066
439
#define WM8994_WRITE_SEQUENCER_103 0x3067
440
#define WM8994_WRITE_SEQUENCER_104 0x3068
441
#define WM8994_WRITE_SEQUENCER_105 0x3069
442
#define WM8994_WRITE_SEQUENCER_106 0x306A
443
#define WM8994_WRITE_SEQUENCER_107 0x306B
444
#define WM8994_WRITE_SEQUENCER_108 0x306C
445
#define WM8994_WRITE_SEQUENCER_109 0x306D
446
#define WM8994_WRITE_SEQUENCER_110 0x306E
447
#define WM8994_WRITE_SEQUENCER_111 0x306F
448
#define WM8994_WRITE_SEQUENCER_112 0x3070
449
#define WM8994_WRITE_SEQUENCER_113 0x3071
450
#define WM8994_WRITE_SEQUENCER_114 0x3072
451
#define WM8994_WRITE_SEQUENCER_115 0x3073
452
#define WM8994_WRITE_SEQUENCER_116 0x3074
453
#define WM8994_WRITE_SEQUENCER_117 0x3075
454
#define WM8994_WRITE_SEQUENCER_118 0x3076
455
#define WM8994_WRITE_SEQUENCER_119 0x3077
456
#define WM8994_WRITE_SEQUENCER_120 0x3078
457
#define WM8994_WRITE_SEQUENCER_121 0x3079
458
#define WM8994_WRITE_SEQUENCER_122 0x307A
459
#define WM8994_WRITE_SEQUENCER_123 0x307B
460
#define WM8994_WRITE_SEQUENCER_124 0x307C
461
#define WM8994_WRITE_SEQUENCER_125 0x307D
462
#define WM8994_WRITE_SEQUENCER_126 0x307E
463
#define WM8994_WRITE_SEQUENCER_127 0x307F
464
#define WM8994_WRITE_SEQUENCER_128 0x3080
465
#define WM8994_WRITE_SEQUENCER_129 0x3081
466
#define WM8994_WRITE_SEQUENCER_130 0x3082
467
#define WM8994_WRITE_SEQUENCER_131 0x3083
468
#define WM8994_WRITE_SEQUENCER_132 0x3084
469
#define WM8994_WRITE_SEQUENCER_133 0x3085
470
#define WM8994_WRITE_SEQUENCER_134 0x3086
471
#define WM8994_WRITE_SEQUENCER_135 0x3087
472
#define WM8994_WRITE_SEQUENCER_136 0x3088
473
#define WM8994_WRITE_SEQUENCER_137 0x3089
474
#define WM8994_WRITE_SEQUENCER_138 0x308A
475
#define WM8994_WRITE_SEQUENCER_139 0x308B
476
#define WM8994_WRITE_SEQUENCER_140 0x308C
477
#define WM8994_WRITE_SEQUENCER_141 0x308D
478
#define WM8994_WRITE_SEQUENCER_142 0x308E
479
#define WM8994_WRITE_SEQUENCER_143 0x308F
480
#define WM8994_WRITE_SEQUENCER_144 0x3090
481
#define WM8994_WRITE_SEQUENCER_145 0x3091
482
#define WM8994_WRITE_SEQUENCER_146 0x3092
483
#define WM8994_WRITE_SEQUENCER_147 0x3093
484
#define WM8994_WRITE_SEQUENCER_148 0x3094
485
#define WM8994_WRITE_SEQUENCER_149 0x3095
486
#define WM8994_WRITE_SEQUENCER_150 0x3096
487
#define WM8994_WRITE_SEQUENCER_151 0x3097
488
#define WM8994_WRITE_SEQUENCER_152 0x3098
489
#define WM8994_WRITE_SEQUENCER_153 0x3099
490
#define WM8994_WRITE_SEQUENCER_154 0x309A
491
#define WM8994_WRITE_SEQUENCER_155 0x309B
492
#define WM8994_WRITE_SEQUENCER_156 0x309C
493
#define WM8994_WRITE_SEQUENCER_157 0x309D
494
#define WM8994_WRITE_SEQUENCER_158 0x309E
495
#define WM8994_WRITE_SEQUENCER_159 0x309F
496
#define WM8994_WRITE_SEQUENCER_160 0x30A0
497
#define WM8994_WRITE_SEQUENCER_161 0x30A1
498
#define WM8994_WRITE_SEQUENCER_162 0x30A2
499
#define WM8994_WRITE_SEQUENCER_163 0x30A3
500
#define WM8994_WRITE_SEQUENCER_164 0x30A4
501
#define WM8994_WRITE_SEQUENCER_165 0x30A5
502
#define WM8994_WRITE_SEQUENCER_166 0x30A6
503
#define WM8994_WRITE_SEQUENCER_167 0x30A7
504
#define WM8994_WRITE_SEQUENCER_168 0x30A8
505
#define WM8994_WRITE_SEQUENCER_169 0x30A9
506
#define WM8994_WRITE_SEQUENCER_170 0x30AA
507
#define WM8994_WRITE_SEQUENCER_171 0x30AB
508
#define WM8994_WRITE_SEQUENCER_172 0x30AC
509
#define WM8994_WRITE_SEQUENCER_173 0x30AD
510
#define WM8994_WRITE_SEQUENCER_174 0x30AE
511
#define WM8994_WRITE_SEQUENCER_175 0x30AF
512
#define WM8994_WRITE_SEQUENCER_176 0x30B0
513
#define WM8994_WRITE_SEQUENCER_177 0x30B1
514
#define WM8994_WRITE_SEQUENCER_178 0x30B2
515
#define WM8994_WRITE_SEQUENCER_179 0x30B3
516
#define WM8994_WRITE_SEQUENCER_180 0x30B4
517
#define WM8994_WRITE_SEQUENCER_181 0x30B5
518
#define WM8994_WRITE_SEQUENCER_182 0x30B6
519
#define WM8994_WRITE_SEQUENCER_183 0x30B7
520
#define WM8994_WRITE_SEQUENCER_184 0x30B8
521
#define WM8994_WRITE_SEQUENCER_185 0x30B9
522
#define WM8994_WRITE_SEQUENCER_186 0x30BA
523
#define WM8994_WRITE_SEQUENCER_187 0x30BB
524
#define WM8994_WRITE_SEQUENCER_188 0x30BC
525
#define WM8994_WRITE_SEQUENCER_189 0x30BD
526
#define WM8994_WRITE_SEQUENCER_190 0x30BE
527
#define WM8994_WRITE_SEQUENCER_191 0x30BF
528
#define WM8994_WRITE_SEQUENCER_192 0x30C0
529
#define WM8994_WRITE_SEQUENCER_193 0x30C1
530
#define WM8994_WRITE_SEQUENCER_194 0x30C2
531
#define WM8994_WRITE_SEQUENCER_195 0x30C3
532
#define WM8994_WRITE_SEQUENCER_196 0x30C4
533
#define WM8994_WRITE_SEQUENCER_197 0x30C5
534
#define WM8994_WRITE_SEQUENCER_198 0x30C6
535
#define WM8994_WRITE_SEQUENCER_199 0x30C7
536
#define WM8994_WRITE_SEQUENCER_200 0x30C8
537
#define WM8994_WRITE_SEQUENCER_201 0x30C9
538
#define WM8994_WRITE_SEQUENCER_202 0x30CA
539
#define WM8994_WRITE_SEQUENCER_203 0x30CB
540
#define WM8994_WRITE_SEQUENCER_204 0x30CC
541
#define WM8994_WRITE_SEQUENCER_205 0x30CD
542
#define WM8994_WRITE_SEQUENCER_206 0x30CE
543
#define WM8994_WRITE_SEQUENCER_207 0x30CF
544
#define WM8994_WRITE_SEQUENCER_208 0x30D0
545
#define WM8994_WRITE_SEQUENCER_209 0x30D1
546
#define WM8994_WRITE_SEQUENCER_210 0x30D2
547
#define WM8994_WRITE_SEQUENCER_211 0x30D3
548
#define WM8994_WRITE_SEQUENCER_212 0x30D4
549
#define WM8994_WRITE_SEQUENCER_213 0x30D5
550
#define WM8994_WRITE_SEQUENCER_214 0x30D6
551
#define WM8994_WRITE_SEQUENCER_215 0x30D7
552
#define WM8994_WRITE_SEQUENCER_216 0x30D8
553
#define WM8994_WRITE_SEQUENCER_217 0x30D9
554
#define WM8994_WRITE_SEQUENCER_218 0x30DA
555
#define WM8994_WRITE_SEQUENCER_219 0x30DB
556
#define WM8994_WRITE_SEQUENCER_220 0x30DC
557
#define WM8994_WRITE_SEQUENCER_221 0x30DD
558
#define WM8994_WRITE_SEQUENCER_222 0x30DE
559
#define WM8994_WRITE_SEQUENCER_223 0x30DF
560
#define WM8994_WRITE_SEQUENCER_224 0x30E0
561
#define WM8994_WRITE_SEQUENCER_225 0x30E1
562
#define WM8994_WRITE_SEQUENCER_226 0x30E2
563
#define WM8994_WRITE_SEQUENCER_227 0x30E3
564
#define WM8994_WRITE_SEQUENCER_228 0x30E4
565
#define WM8994_WRITE_SEQUENCER_229 0x30E5
566
#define WM8994_WRITE_SEQUENCER_230 0x30E6
567
#define WM8994_WRITE_SEQUENCER_231 0x30E7
568
#define WM8994_WRITE_SEQUENCER_232 0x30E8
569
#define WM8994_WRITE_SEQUENCER_233 0x30E9
570
#define WM8994_WRITE_SEQUENCER_234 0x30EA
571
#define WM8994_WRITE_SEQUENCER_235 0x30EB
572
#define WM8994_WRITE_SEQUENCER_236 0x30EC
573
#define WM8994_WRITE_SEQUENCER_237 0x30ED
574
#define WM8994_WRITE_SEQUENCER_238 0x30EE
575
#define WM8994_WRITE_SEQUENCER_239 0x30EF
576
#define WM8994_WRITE_SEQUENCER_240 0x30F0
577
#define WM8994_WRITE_SEQUENCER_241 0x30F1
578
#define WM8994_WRITE_SEQUENCER_242 0x30F2
579
#define WM8994_WRITE_SEQUENCER_243 0x30F3
580
#define WM8994_WRITE_SEQUENCER_244 0x30F4
581
#define WM8994_WRITE_SEQUENCER_245 0x30F5
582
#define WM8994_WRITE_SEQUENCER_246 0x30F6
583
#define WM8994_WRITE_SEQUENCER_247 0x30F7
584
#define WM8994_WRITE_SEQUENCER_248 0x30F8
585
#define WM8994_WRITE_SEQUENCER_249 0x30F9
586
#define WM8994_WRITE_SEQUENCER_250 0x30FA
587
#define WM8994_WRITE_SEQUENCER_251 0x30FB
588
#define WM8994_WRITE_SEQUENCER_252 0x30FC
589
#define WM8994_WRITE_SEQUENCER_253 0x30FD
590
#define WM8994_WRITE_SEQUENCER_254 0x30FE
591
#define WM8994_WRITE_SEQUENCER_255 0x30FF
592
#define WM8994_WRITE_SEQUENCER_256 0x3100
593
#define WM8994_WRITE_SEQUENCER_257 0x3101
594
#define WM8994_WRITE_SEQUENCER_258 0x3102
595
#define WM8994_WRITE_SEQUENCER_259 0x3103
596
#define WM8994_WRITE_SEQUENCER_260 0x3104
597
#define WM8994_WRITE_SEQUENCER_261 0x3105
598
#define WM8994_WRITE_SEQUENCER_262 0x3106
599
#define WM8994_WRITE_SEQUENCER_263 0x3107
600
#define WM8994_WRITE_SEQUENCER_264 0x3108
601
#define WM8994_WRITE_SEQUENCER_265 0x3109
602
#define WM8994_WRITE_SEQUENCER_266 0x310A
603
#define WM8994_WRITE_SEQUENCER_267 0x310B
604
#define WM8994_WRITE_SEQUENCER_268 0x310C
605
#define WM8994_WRITE_SEQUENCER_269 0x310D
606
#define WM8994_WRITE_SEQUENCER_270 0x310E
607
#define WM8994_WRITE_SEQUENCER_271 0x310F
608
#define WM8994_WRITE_SEQUENCER_272 0x3110
609
#define WM8994_WRITE_SEQUENCER_273 0x3111
610
#define WM8994_WRITE_SEQUENCER_274 0x3112
611
#define WM8994_WRITE_SEQUENCER_275 0x3113
612
#define WM8994_WRITE_SEQUENCER_276 0x3114
613
#define WM8994_WRITE_SEQUENCER_277 0x3115
614
#define WM8994_WRITE_SEQUENCER_278 0x3116
615
#define WM8994_WRITE_SEQUENCER_279 0x3117
616
#define WM8994_WRITE_SEQUENCER_280 0x3118
617
#define WM8994_WRITE_SEQUENCER_281 0x3119
618
#define WM8994_WRITE_SEQUENCER_282 0x311A
619
#define WM8994_WRITE_SEQUENCER_283 0x311B
620
#define WM8994_WRITE_SEQUENCER_284 0x311C
621
#define WM8994_WRITE_SEQUENCER_285 0x311D
622
#define WM8994_WRITE_SEQUENCER_286 0x311E
623
#define WM8994_WRITE_SEQUENCER_287 0x311F
624
#define WM8994_WRITE_SEQUENCER_288 0x3120
625
#define WM8994_WRITE_SEQUENCER_289 0x3121
626
#define WM8994_WRITE_SEQUENCER_290 0x3122
627
#define WM8994_WRITE_SEQUENCER_291 0x3123
628
#define WM8994_WRITE_SEQUENCER_292 0x3124
629
#define WM8994_WRITE_SEQUENCER_293 0x3125
630
#define WM8994_WRITE_SEQUENCER_294 0x3126
631
#define WM8994_WRITE_SEQUENCER_295 0x3127
632
#define WM8994_WRITE_SEQUENCER_296 0x3128
633
#define WM8994_WRITE_SEQUENCER_297 0x3129
634
#define WM8994_WRITE_SEQUENCER_298 0x312A
635
#define WM8994_WRITE_SEQUENCER_299 0x312B
636
#define WM8994_WRITE_SEQUENCER_300 0x312C
637
#define WM8994_WRITE_SEQUENCER_301 0x312D
638
#define WM8994_WRITE_SEQUENCER_302 0x312E
639
#define WM8994_WRITE_SEQUENCER_303 0x312F
640
#define WM8994_WRITE_SEQUENCER_304 0x3130
641
#define WM8994_WRITE_SEQUENCER_305 0x3131
642
#define WM8994_WRITE_SEQUENCER_306 0x3132
643
#define WM8994_WRITE_SEQUENCER_307 0x3133
644
#define WM8994_WRITE_SEQUENCER_308 0x3134
645
#define WM8994_WRITE_SEQUENCER_309 0x3135
646
#define WM8994_WRITE_SEQUENCER_310 0x3136
647
#define WM8994_WRITE_SEQUENCER_311 0x3137
648
#define WM8994_WRITE_SEQUENCER_312 0x3138
649
#define WM8994_WRITE_SEQUENCER_313 0x3139
650
#define WM8994_WRITE_SEQUENCER_314 0x313A
651
#define WM8994_WRITE_SEQUENCER_315 0x313B
652
#define WM8994_WRITE_SEQUENCER_316 0x313C
653
#define WM8994_WRITE_SEQUENCER_317 0x313D
654
#define WM8994_WRITE_SEQUENCER_318 0x313E
655
#define WM8994_WRITE_SEQUENCER_319 0x313F
656
#define WM8994_WRITE_SEQUENCER_320 0x3140
657
#define WM8994_WRITE_SEQUENCER_321 0x3141
658
#define WM8994_WRITE_SEQUENCER_322 0x3142
659
#define WM8994_WRITE_SEQUENCER_323 0x3143
660
#define WM8994_WRITE_SEQUENCER_324 0x3144
661
#define WM8994_WRITE_SEQUENCER_325 0x3145
662
#define WM8994_WRITE_SEQUENCER_326 0x3146
663
#define WM8994_WRITE_SEQUENCER_327 0x3147
664
#define WM8994_WRITE_SEQUENCER_328 0x3148
665
#define WM8994_WRITE_SEQUENCER_329 0x3149
666
#define WM8994_WRITE_SEQUENCER_330 0x314A
667
#define WM8994_WRITE_SEQUENCER_331 0x314B
668
#define WM8994_WRITE_SEQUENCER_332 0x314C
669
#define WM8994_WRITE_SEQUENCER_333 0x314D
670
#define WM8994_WRITE_SEQUENCER_334 0x314E
671
#define WM8994_WRITE_SEQUENCER_335 0x314F
672
#define WM8994_WRITE_SEQUENCER_336 0x3150
673
#define WM8994_WRITE_SEQUENCER_337 0x3151
674
#define WM8994_WRITE_SEQUENCER_338 0x3152
675
#define WM8994_WRITE_SEQUENCER_339 0x3153
676
#define WM8994_WRITE_SEQUENCER_340 0x3154
677
#define WM8994_WRITE_SEQUENCER_341 0x3155
678
#define WM8994_WRITE_SEQUENCER_342 0x3156
679
#define WM8994_WRITE_SEQUENCER_343 0x3157
680
#define WM8994_WRITE_SEQUENCER_344 0x3158
681
#define WM8994_WRITE_SEQUENCER_345 0x3159
682
#define WM8994_WRITE_SEQUENCER_346 0x315A
683
#define WM8994_WRITE_SEQUENCER_347 0x315B
684
#define WM8994_WRITE_SEQUENCER_348 0x315C
685
#define WM8994_WRITE_SEQUENCER_349 0x315D
686
#define WM8994_WRITE_SEQUENCER_350 0x315E
687
#define WM8994_WRITE_SEQUENCER_351 0x315F
688
#define WM8994_WRITE_SEQUENCER_352 0x3160
689
#define WM8994_WRITE_SEQUENCER_353 0x3161
690
#define WM8994_WRITE_SEQUENCER_354 0x3162
691
#define WM8994_WRITE_SEQUENCER_355 0x3163
692
#define WM8994_WRITE_SEQUENCER_356 0x3164
693
#define WM8994_WRITE_SEQUENCER_357 0x3165
694
#define WM8994_WRITE_SEQUENCER_358 0x3166
695
#define WM8994_WRITE_SEQUENCER_359 0x3167
696
#define WM8994_WRITE_SEQUENCER_360 0x3168
697
#define WM8994_WRITE_SEQUENCER_361 0x3169
698
#define WM8994_WRITE_SEQUENCER_362 0x316A
699
#define WM8994_WRITE_SEQUENCER_363 0x316B
700
#define WM8994_WRITE_SEQUENCER_364 0x316C
701
#define WM8994_WRITE_SEQUENCER_365 0x316D
702
#define WM8994_WRITE_SEQUENCER_366 0x316E
703
#define WM8994_WRITE_SEQUENCER_367 0x316F
704
#define WM8994_WRITE_SEQUENCER_368 0x3170
705
#define WM8994_WRITE_SEQUENCER_369 0x3171
706
#define WM8994_WRITE_SEQUENCER_370 0x3172
707
#define WM8994_WRITE_SEQUENCER_371 0x3173
708
#define WM8994_WRITE_SEQUENCER_372 0x3174
709
#define WM8994_WRITE_SEQUENCER_373 0x3175
710
#define WM8994_WRITE_SEQUENCER_374 0x3176
711
#define WM8994_WRITE_SEQUENCER_375 0x3177
712
#define WM8994_WRITE_SEQUENCER_376 0x3178
713
#define WM8994_WRITE_SEQUENCER_377 0x3179
714
#define WM8994_WRITE_SEQUENCER_378 0x317A
715
#define WM8994_WRITE_SEQUENCER_379 0x317B
716
#define WM8994_WRITE_SEQUENCER_380 0x317C
717
#define WM8994_WRITE_SEQUENCER_381 0x317D
718
#define WM8994_WRITE_SEQUENCER_382 0x317E
719
#define WM8994_WRITE_SEQUENCER_383 0x317F
720
#define WM8994_WRITE_SEQUENCER_384 0x3180
721
#define WM8994_WRITE_SEQUENCER_385 0x3181
722
#define WM8994_WRITE_SEQUENCER_386 0x3182
723
#define WM8994_WRITE_SEQUENCER_387 0x3183
724
#define WM8994_WRITE_SEQUENCER_388 0x3184
725
#define WM8994_WRITE_SEQUENCER_389 0x3185
726
#define WM8994_WRITE_SEQUENCER_390 0x3186
727
#define WM8994_WRITE_SEQUENCER_391 0x3187
728
#define WM8994_WRITE_SEQUENCER_392 0x3188
729
#define WM8994_WRITE_SEQUENCER_393 0x3189
730
#define WM8994_WRITE_SEQUENCER_394 0x318A
731
#define WM8994_WRITE_SEQUENCER_395 0x318B
732
#define WM8994_WRITE_SEQUENCER_396 0x318C
733
#define WM8994_WRITE_SEQUENCER_397 0x318D
734
#define WM8994_WRITE_SEQUENCER_398 0x318E
735
#define WM8994_WRITE_SEQUENCER_399 0x318F
736
#define WM8994_WRITE_SEQUENCER_400 0x3190
737
#define WM8994_WRITE_SEQUENCER_401 0x3191
738
#define WM8994_WRITE_SEQUENCER_402 0x3192
739
#define WM8994_WRITE_SEQUENCER_403 0x3193
740
#define WM8994_WRITE_SEQUENCER_404 0x3194
741
#define WM8994_WRITE_SEQUENCER_405 0x3195
742
#define WM8994_WRITE_SEQUENCER_406 0x3196
743
#define WM8994_WRITE_SEQUENCER_407 0x3197
744
#define WM8994_WRITE_SEQUENCER_408 0x3198
745
#define WM8994_WRITE_SEQUENCER_409 0x3199
746
#define WM8994_WRITE_SEQUENCER_410 0x319A
747
#define WM8994_WRITE_SEQUENCER_411 0x319B
748
#define WM8994_WRITE_SEQUENCER_412 0x319C
749
#define WM8994_WRITE_SEQUENCER_413 0x319D
750
#define WM8994_WRITE_SEQUENCER_414 0x319E
751
#define WM8994_WRITE_SEQUENCER_415 0x319F
752
#define WM8994_WRITE_SEQUENCER_416 0x31A0
753
#define WM8994_WRITE_SEQUENCER_417 0x31A1
754
#define WM8994_WRITE_SEQUENCER_418 0x31A2
755
#define WM8994_WRITE_SEQUENCER_419 0x31A3
756
#define WM8994_WRITE_SEQUENCER_420 0x31A4
757
#define WM8994_WRITE_SEQUENCER_421 0x31A5
758
#define WM8994_WRITE_SEQUENCER_422 0x31A6
759
#define WM8994_WRITE_SEQUENCER_423 0x31A7
760
#define WM8994_WRITE_SEQUENCER_424 0x31A8
761
#define WM8994_WRITE_SEQUENCER_425 0x31A9
762
#define WM8994_WRITE_SEQUENCER_426 0x31AA
763
#define WM8994_WRITE_SEQUENCER_427 0x31AB
764
#define WM8994_WRITE_SEQUENCER_428 0x31AC
765
#define WM8994_WRITE_SEQUENCER_429 0x31AD
766
#define WM8994_WRITE_SEQUENCER_430 0x31AE
767
#define WM8994_WRITE_SEQUENCER_431 0x31AF
768
#define WM8994_WRITE_SEQUENCER_432 0x31B0
769
#define WM8994_WRITE_SEQUENCER_433 0x31B1
770
#define WM8994_WRITE_SEQUENCER_434 0x31B2
771
#define WM8994_WRITE_SEQUENCER_435 0x31B3
772
#define WM8994_WRITE_SEQUENCER_436 0x31B4
773
#define WM8994_WRITE_SEQUENCER_437 0x31B5
774
#define WM8994_WRITE_SEQUENCER_438 0x31B6
775
#define WM8994_WRITE_SEQUENCER_439 0x31B7
776
#define WM8994_WRITE_SEQUENCER_440 0x31B8
777
#define WM8994_WRITE_SEQUENCER_441 0x31B9
778
#define WM8994_WRITE_SEQUENCER_442 0x31BA
779
#define WM8994_WRITE_SEQUENCER_443 0x31BB
780
#define WM8994_WRITE_SEQUENCER_444 0x31BC
781
#define WM8994_WRITE_SEQUENCER_445 0x31BD
782
#define WM8994_WRITE_SEQUENCER_446 0x31BE
783
#define WM8994_WRITE_SEQUENCER_447 0x31BF
784
#define WM8994_WRITE_SEQUENCER_448 0x31C0
785
#define WM8994_WRITE_SEQUENCER_449 0x31C1
786
#define WM8994_WRITE_SEQUENCER_450 0x31C2
787
#define WM8994_WRITE_SEQUENCER_451 0x31C3
788
#define WM8994_WRITE_SEQUENCER_452 0x31C4
789
#define WM8994_WRITE_SEQUENCER_453 0x31C5
790
#define WM8994_WRITE_SEQUENCER_454 0x31C6
791
#define WM8994_WRITE_SEQUENCER_455 0x31C7
792
#define WM8994_WRITE_SEQUENCER_456 0x31C8
793
#define WM8994_WRITE_SEQUENCER_457 0x31C9
794
#define WM8994_WRITE_SEQUENCER_458 0x31CA
795
#define WM8994_WRITE_SEQUENCER_459 0x31CB
796
#define WM8994_WRITE_SEQUENCER_460 0x31CC
797
#define WM8994_WRITE_SEQUENCER_461 0x31CD
798
#define WM8994_WRITE_SEQUENCER_462 0x31CE
799
#define WM8994_WRITE_SEQUENCER_463 0x31CF
800
#define WM8994_WRITE_SEQUENCER_464 0x31D0
801
#define WM8994_WRITE_SEQUENCER_465 0x31D1
802
#define WM8994_WRITE_SEQUENCER_466 0x31D2
803
#define WM8994_WRITE_SEQUENCER_467 0x31D3
804
#define WM8994_WRITE_SEQUENCER_468 0x31D4
805
#define WM8994_WRITE_SEQUENCER_469 0x31D5
806
#define WM8994_WRITE_SEQUENCER_470 0x31D6
807
#define WM8994_WRITE_SEQUENCER_471 0x31D7
808
#define WM8994_WRITE_SEQUENCER_472 0x31D8
809
#define WM8994_WRITE_SEQUENCER_473 0x31D9
810
#define WM8994_WRITE_SEQUENCER_474 0x31DA
811
#define WM8994_WRITE_SEQUENCER_475 0x31DB
812
#define WM8994_WRITE_SEQUENCER_476 0x31DC
813
#define WM8994_WRITE_SEQUENCER_477 0x31DD
814
#define WM8994_WRITE_SEQUENCER_478 0x31DE
815
#define WM8994_WRITE_SEQUENCER_479 0x31DF
816
#define WM8994_WRITE_SEQUENCER_480 0x31E0
817
#define WM8994_WRITE_SEQUENCER_481 0x31E1
818
#define WM8994_WRITE_SEQUENCER_482 0x31E2
819
#define WM8994_WRITE_SEQUENCER_483 0x31E3
820
#define WM8994_WRITE_SEQUENCER_484 0x31E4
821
#define WM8994_WRITE_SEQUENCER_485 0x31E5
822
#define WM8994_WRITE_SEQUENCER_486 0x31E6
823
#define WM8994_WRITE_SEQUENCER_487 0x31E7
824
#define WM8994_WRITE_SEQUENCER_488 0x31E8
825
#define WM8994_WRITE_SEQUENCER_489 0x31E9
826
#define WM8994_WRITE_SEQUENCER_490 0x31EA
827
#define WM8994_WRITE_SEQUENCER_491 0x31EB
828
#define WM8994_WRITE_SEQUENCER_492 0x31EC
829
#define WM8994_WRITE_SEQUENCER_493 0x31ED
830
#define WM8994_WRITE_SEQUENCER_494 0x31EE
831
#define WM8994_WRITE_SEQUENCER_495 0x31EF
832
#define WM8994_WRITE_SEQUENCER_496 0x31F0
833
#define WM8994_WRITE_SEQUENCER_497 0x31F1
834
#define WM8994_WRITE_SEQUENCER_498 0x31F2
835
#define WM8994_WRITE_SEQUENCER_499 0x31F3
836
#define WM8994_WRITE_SEQUENCER_500 0x31F4
837
#define WM8994_WRITE_SEQUENCER_501 0x31F5
838
#define WM8994_WRITE_SEQUENCER_502 0x31F6
839
#define WM8994_WRITE_SEQUENCER_503 0x31F7
840
#define WM8994_WRITE_SEQUENCER_504 0x31F8
841
#define WM8994_WRITE_SEQUENCER_505 0x31F9
842
#define WM8994_WRITE_SEQUENCER_506 0x31FA
843
#define WM8994_WRITE_SEQUENCER_507 0x31FB
844
#define WM8994_WRITE_SEQUENCER_508 0x31FC
845
#define WM8994_WRITE_SEQUENCER_509 0x31FD
846
#define WM8994_WRITE_SEQUENCER_510 0x31FE
847
#define WM8994_WRITE_SEQUENCER_511 0x31FF
849
#define WM8994_REGISTER_COUNT 736
850
#define WM8994_MAX_REGISTER 0x31FF
851
#define WM8994_MAX_CACHED_REGISTER 0x749
858
* R0 (0x00) - Software Reset
860
#define WM8994_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
861
#define WM8994_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
862
#define WM8994_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
865
* R1 (0x01) - Power Management (1)
867
#define WM8994_SPKOUTR_ENA 0x2000 /* SPKOUTR_ENA */
868
#define WM8994_SPKOUTR_ENA_MASK 0x2000 /* SPKOUTR_ENA */
869
#define WM8994_SPKOUTR_ENA_SHIFT 13 /* SPKOUTR_ENA */
870
#define WM8994_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */
871
#define WM8994_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */
872
#define WM8994_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */
873
#define WM8994_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */
874
#define WM8994_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */
875
#define WM8994_HPOUT2_ENA 0x0800 /* HPOUT2_ENA */
876
#define WM8994_HPOUT2_ENA_MASK 0x0800 /* HPOUT2_ENA */
877
#define WM8994_HPOUT2_ENA_SHIFT 11 /* HPOUT2_ENA */
878
#define WM8994_HPOUT2_ENA_WIDTH 1 /* HPOUT2_ENA */
879
#define WM8994_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */
880
#define WM8994_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */
881
#define WM8994_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */
882
#define WM8994_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
883
#define WM8994_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */
884
#define WM8994_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */
885
#define WM8994_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */
886
#define WM8994_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
887
#define WM8994_MICB2_ENA 0x0020 /* MICB2_ENA */
888
#define WM8994_MICB2_ENA_MASK 0x0020 /* MICB2_ENA */
889
#define WM8994_MICB2_ENA_SHIFT 5 /* MICB2_ENA */
890
#define WM8994_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
891
#define WM8994_MICB1_ENA 0x0010 /* MICB1_ENA */
892
#define WM8994_MICB1_ENA_MASK 0x0010 /* MICB1_ENA */
893
#define WM8994_MICB1_ENA_SHIFT 4 /* MICB1_ENA */
894
#define WM8994_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
895
#define WM8994_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
896
#define WM8994_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
897
#define WM8994_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
898
#define WM8994_BIAS_ENA 0x0001 /* BIAS_ENA */
899
#define WM8994_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
900
#define WM8994_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
901
#define WM8994_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
904
* R2 (0x02) - Power Management (2)
906
#define WM8994_TSHUT_ENA 0x4000 /* TSHUT_ENA */
907
#define WM8994_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
908
#define WM8994_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
909
#define WM8994_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
910
#define WM8994_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
911
#define WM8994_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
912
#define WM8994_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
913
#define WM8994_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
914
#define WM8994_OPCLK_ENA 0x0800 /* OPCLK_ENA */
915
#define WM8994_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
916
#define WM8994_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
917
#define WM8994_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
918
#define WM8994_MIXINL_ENA 0x0200 /* MIXINL_ENA */
919
#define WM8994_MIXINL_ENA_MASK 0x0200 /* MIXINL_ENA */
920
#define WM8994_MIXINL_ENA_SHIFT 9 /* MIXINL_ENA */
921
#define WM8994_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */
922
#define WM8994_MIXINR_ENA 0x0100 /* MIXINR_ENA */
923
#define WM8994_MIXINR_ENA_MASK 0x0100 /* MIXINR_ENA */
924
#define WM8994_MIXINR_ENA_SHIFT 8 /* MIXINR_ENA */
925
#define WM8994_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */
926
#define WM8994_IN2L_ENA 0x0080 /* IN2L_ENA */
927
#define WM8994_IN2L_ENA_MASK 0x0080 /* IN2L_ENA */
928
#define WM8994_IN2L_ENA_SHIFT 7 /* IN2L_ENA */
929
#define WM8994_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
930
#define WM8994_IN1L_ENA 0x0040 /* IN1L_ENA */
931
#define WM8994_IN1L_ENA_MASK 0x0040 /* IN1L_ENA */
932
#define WM8994_IN1L_ENA_SHIFT 6 /* IN1L_ENA */
933
#define WM8994_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
934
#define WM8994_IN2R_ENA 0x0020 /* IN2R_ENA */
935
#define WM8994_IN2R_ENA_MASK 0x0020 /* IN2R_ENA */
936
#define WM8994_IN2R_ENA_SHIFT 5 /* IN2R_ENA */
937
#define WM8994_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
938
#define WM8994_IN1R_ENA 0x0010 /* IN1R_ENA */
939
#define WM8994_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */
940
#define WM8994_IN1R_ENA_SHIFT 4 /* IN1R_ENA */
941
#define WM8994_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
944
* R3 (0x03) - Power Management (3)
946
#define WM8994_LINEOUT1N_ENA 0x2000 /* LINEOUT1N_ENA */
947
#define WM8994_LINEOUT1N_ENA_MASK 0x2000 /* LINEOUT1N_ENA */
948
#define WM8994_LINEOUT1N_ENA_SHIFT 13 /* LINEOUT1N_ENA */
949
#define WM8994_LINEOUT1N_ENA_WIDTH 1 /* LINEOUT1N_ENA */
950
#define WM8994_LINEOUT1P_ENA 0x1000 /* LINEOUT1P_ENA */
951
#define WM8994_LINEOUT1P_ENA_MASK 0x1000 /* LINEOUT1P_ENA */
952
#define WM8994_LINEOUT1P_ENA_SHIFT 12 /* LINEOUT1P_ENA */
953
#define WM8994_LINEOUT1P_ENA_WIDTH 1 /* LINEOUT1P_ENA */
954
#define WM8994_LINEOUT2N_ENA 0x0800 /* LINEOUT2N_ENA */
955
#define WM8994_LINEOUT2N_ENA_MASK 0x0800 /* LINEOUT2N_ENA */
956
#define WM8994_LINEOUT2N_ENA_SHIFT 11 /* LINEOUT2N_ENA */
957
#define WM8994_LINEOUT2N_ENA_WIDTH 1 /* LINEOUT2N_ENA */
958
#define WM8994_LINEOUT2P_ENA 0x0400 /* LINEOUT2P_ENA */
959
#define WM8994_LINEOUT2P_ENA_MASK 0x0400 /* LINEOUT2P_ENA */
960
#define WM8994_LINEOUT2P_ENA_SHIFT 10 /* LINEOUT2P_ENA */
961
#define WM8994_LINEOUT2P_ENA_WIDTH 1 /* LINEOUT2P_ENA */
962
#define WM8994_SPKRVOL_ENA 0x0200 /* SPKRVOL_ENA */
963
#define WM8994_SPKRVOL_ENA_MASK 0x0200 /* SPKRVOL_ENA */
964
#define WM8994_SPKRVOL_ENA_SHIFT 9 /* SPKRVOL_ENA */
965
#define WM8994_SPKRVOL_ENA_WIDTH 1 /* SPKRVOL_ENA */
966
#define WM8994_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */
967
#define WM8994_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */
968
#define WM8994_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */
969
#define WM8994_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */
970
#define WM8994_MIXOUTLVOL_ENA 0x0080 /* MIXOUTLVOL_ENA */
971
#define WM8994_MIXOUTLVOL_ENA_MASK 0x0080 /* MIXOUTLVOL_ENA */
972
#define WM8994_MIXOUTLVOL_ENA_SHIFT 7 /* MIXOUTLVOL_ENA */
973
#define WM8994_MIXOUTLVOL_ENA_WIDTH 1 /* MIXOUTLVOL_ENA */
974
#define WM8994_MIXOUTRVOL_ENA 0x0040 /* MIXOUTRVOL_ENA */
975
#define WM8994_MIXOUTRVOL_ENA_MASK 0x0040 /* MIXOUTRVOL_ENA */
976
#define WM8994_MIXOUTRVOL_ENA_SHIFT 6 /* MIXOUTRVOL_ENA */
977
#define WM8994_MIXOUTRVOL_ENA_WIDTH 1 /* MIXOUTRVOL_ENA */
978
#define WM8994_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */
979
#define WM8994_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */
980
#define WM8994_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */
981
#define WM8994_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */
982
#define WM8994_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */
983
#define WM8994_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */
984
#define WM8994_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */
985
#define WM8994_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */
988
* R4 (0x04) - Power Management (4)
990
#define WM8994_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */
991
#define WM8994_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */
992
#define WM8994_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */
993
#define WM8994_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */
994
#define WM8994_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */
995
#define WM8994_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */
996
#define WM8994_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */
997
#define WM8994_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */
998
#define WM8994_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */
999
#define WM8994_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */
1000
#define WM8994_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */
1001
#define WM8994_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */
1002
#define WM8994_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */
1003
#define WM8994_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */
1004
#define WM8994_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */
1005
#define WM8994_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */
1006
#define WM8994_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */
1007
#define WM8994_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */
1008
#define WM8994_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */
1009
#define WM8994_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */
1010
#define WM8994_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */
1011
#define WM8994_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */
1012
#define WM8994_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */
1013
#define WM8994_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */
1014
#define WM8994_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
1015
#define WM8994_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
1016
#define WM8994_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
1017
#define WM8994_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
1018
#define WM8994_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
1019
#define WM8994_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
1020
#define WM8994_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
1021
#define WM8994_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
1022
#define WM8994_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
1023
#define WM8994_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
1024
#define WM8994_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
1025
#define WM8994_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
1026
#define WM8994_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
1027
#define WM8994_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
1028
#define WM8994_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
1029
#define WM8994_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
1030
#define WM8994_ADCL_ENA 0x0002 /* ADCL_ENA */
1031
#define WM8994_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
1032
#define WM8994_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
1033
#define WM8994_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
1034
#define WM8994_ADCR_ENA 0x0001 /* ADCR_ENA */
1035
#define WM8994_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
1036
#define WM8994_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
1037
#define WM8994_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
1040
* R5 (0x05) - Power Management (5)
1042
#define WM8994_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */
1043
#define WM8994_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */
1044
#define WM8994_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */
1045
#define WM8994_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */
1046
#define WM8994_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */
1047
#define WM8994_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */
1048
#define WM8994_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */
1049
#define WM8994_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */
1050
#define WM8994_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */
1051
#define WM8994_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */
1052
#define WM8994_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */
1053
#define WM8994_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */
1054
#define WM8994_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */
1055
#define WM8994_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */
1056
#define WM8994_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */
1057
#define WM8994_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */
1058
#define WM8994_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */
1059
#define WM8994_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */
1060
#define WM8994_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */
1061
#define WM8994_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */
1062
#define WM8994_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */
1063
#define WM8994_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */
1064
#define WM8994_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */
1065
#define WM8994_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */
1066
#define WM8994_DAC2L_ENA 0x0008 /* DAC2L_ENA */
1067
#define WM8994_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
1068
#define WM8994_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
1069
#define WM8994_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
1070
#define WM8994_DAC2R_ENA 0x0004 /* DAC2R_ENA */
1071
#define WM8994_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
1072
#define WM8994_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
1073
#define WM8994_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
1074
#define WM8994_DAC1L_ENA 0x0002 /* DAC1L_ENA */
1075
#define WM8994_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
1076
#define WM8994_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
1077
#define WM8994_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
1078
#define WM8994_DAC1R_ENA 0x0001 /* DAC1R_ENA */
1079
#define WM8994_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
1080
#define WM8994_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
1081
#define WM8994_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
1084
* R6 (0x06) - Power Management (6)
1086
#define WM8958_AIF3ADC_SRC_MASK 0x0600 /* AIF3ADC_SRC - [10:9] */
1087
#define WM8958_AIF3ADC_SRC_SHIFT 9 /* AIF3ADC_SRC - [10:9] */
1088
#define WM8958_AIF3ADC_SRC_WIDTH 2 /* AIF3ADC_SRC - [10:9] */
1089
#define WM8958_AIF2DAC_SRC_MASK 0x0180 /* AIF2DAC_SRC - [8:7] */
1090
#define WM8958_AIF2DAC_SRC_SHIFT 7 /* AIF2DAC_SRC - [8:7] */
1091
#define WM8958_AIF2DAC_SRC_WIDTH 2 /* AIF2DAC_SRC - [8:7] */
1092
#define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */
1093
#define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */
1094
#define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */
1095
#define WM8994_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
1096
#define WM8994_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */
1097
#define WM8994_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */
1098
#define WM8994_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */
1099
#define WM8994_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */
1100
#define WM8994_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */
1101
#define WM8994_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */
1102
#define WM8994_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */
1103
#define WM8994_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */
1104
#define WM8994_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */
1105
#define WM8994_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */
1106
#define WM8994_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */
1107
#define WM8994_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */
1108
#define WM8994_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */
1109
#define WM8994_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */
1110
#define WM8994_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */
1113
* R21 (0x15) - Input Mixer (1)
1115
#define WM8994_IN1RP_MIXINR_BOOST 0x0100 /* IN1RP_MIXINR_BOOST */
1116
#define WM8994_IN1RP_MIXINR_BOOST_MASK 0x0100 /* IN1RP_MIXINR_BOOST */
1117
#define WM8994_IN1RP_MIXINR_BOOST_SHIFT 8 /* IN1RP_MIXINR_BOOST */
1118
#define WM8994_IN1RP_MIXINR_BOOST_WIDTH 1 /* IN1RP_MIXINR_BOOST */
1119
#define WM8994_IN1LP_MIXINL_BOOST 0x0080 /* IN1LP_MIXINL_BOOST */
1120
#define WM8994_IN1LP_MIXINL_BOOST_MASK 0x0080 /* IN1LP_MIXINL_BOOST */
1121
#define WM8994_IN1LP_MIXINL_BOOST_SHIFT 7 /* IN1LP_MIXINL_BOOST */
1122
#define WM8994_IN1LP_MIXINL_BOOST_WIDTH 1 /* IN1LP_MIXINL_BOOST */
1123
#define WM8994_INPUTS_CLAMP 0x0040 /* INPUTS_CLAMP */
1124
#define WM8994_INPUTS_CLAMP_MASK 0x0040 /* INPUTS_CLAMP */
1125
#define WM8994_INPUTS_CLAMP_SHIFT 6 /* INPUTS_CLAMP */
1126
#define WM8994_INPUTS_CLAMP_WIDTH 1 /* INPUTS_CLAMP */
1129
* R24 (0x18) - Left Line Input 1&2 Volume
1131
#define WM8994_IN1_VU 0x0100 /* IN1_VU */
1132
#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */
1133
#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */
1134
#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */
1135
#define WM8994_IN1L_MUTE 0x0080 /* IN1L_MUTE */
1136
#define WM8994_IN1L_MUTE_MASK 0x0080 /* IN1L_MUTE */
1137
#define WM8994_IN1L_MUTE_SHIFT 7 /* IN1L_MUTE */
1138
#define WM8994_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
1139
#define WM8994_IN1L_ZC 0x0040 /* IN1L_ZC */
1140
#define WM8994_IN1L_ZC_MASK 0x0040 /* IN1L_ZC */
1141
#define WM8994_IN1L_ZC_SHIFT 6 /* IN1L_ZC */
1142
#define WM8994_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
1143
#define WM8994_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
1144
#define WM8994_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
1145
#define WM8994_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
1148
* R25 (0x19) - Left Line Input 3&4 Volume
1150
#define WM8994_IN2_VU 0x0100 /* IN2_VU */
1151
#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */
1152
#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */
1153
#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */
1154
#define WM8994_IN2L_MUTE 0x0080 /* IN2L_MUTE */
1155
#define WM8994_IN2L_MUTE_MASK 0x0080 /* IN2L_MUTE */
1156
#define WM8994_IN2L_MUTE_SHIFT 7 /* IN2L_MUTE */
1157
#define WM8994_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
1158
#define WM8994_IN2L_ZC 0x0040 /* IN2L_ZC */
1159
#define WM8994_IN2L_ZC_MASK 0x0040 /* IN2L_ZC */
1160
#define WM8994_IN2L_ZC_SHIFT 6 /* IN2L_ZC */
1161
#define WM8994_IN2L_ZC_WIDTH 1 /* IN2L_ZC */
1162
#define WM8994_IN2L_VOL_MASK 0x001F /* IN2L_VOL - [4:0] */
1163
#define WM8994_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [4:0] */
1164
#define WM8994_IN2L_VOL_WIDTH 5 /* IN2L_VOL - [4:0] */
1167
* R26 (0x1A) - Right Line Input 1&2 Volume
1169
#define WM8994_IN1_VU 0x0100 /* IN1_VU */
1170
#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */
1171
#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */
1172
#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */
1173
#define WM8994_IN1R_MUTE 0x0080 /* IN1R_MUTE */
1174
#define WM8994_IN1R_MUTE_MASK 0x0080 /* IN1R_MUTE */
1175
#define WM8994_IN1R_MUTE_SHIFT 7 /* IN1R_MUTE */
1176
#define WM8994_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
1177
#define WM8994_IN1R_ZC 0x0040 /* IN1R_ZC */
1178
#define WM8994_IN1R_ZC_MASK 0x0040 /* IN1R_ZC */
1179
#define WM8994_IN1R_ZC_SHIFT 6 /* IN1R_ZC */
1180
#define WM8994_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
1181
#define WM8994_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
1182
#define WM8994_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
1183
#define WM8994_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
1186
* R27 (0x1B) - Right Line Input 3&4 Volume
1188
#define WM8994_IN2_VU 0x0100 /* IN2_VU */
1189
#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */
1190
#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */
1191
#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */
1192
#define WM8994_IN2R_MUTE 0x0080 /* IN2R_MUTE */
1193
#define WM8994_IN2R_MUTE_MASK 0x0080 /* IN2R_MUTE */
1194
#define WM8994_IN2R_MUTE_SHIFT 7 /* IN2R_MUTE */
1195
#define WM8994_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
1196
#define WM8994_IN2R_ZC 0x0040 /* IN2R_ZC */
1197
#define WM8994_IN2R_ZC_MASK 0x0040 /* IN2R_ZC */
1198
#define WM8994_IN2R_ZC_SHIFT 6 /* IN2R_ZC */
1199
#define WM8994_IN2R_ZC_WIDTH 1 /* IN2R_ZC */
1200
#define WM8994_IN2R_VOL_MASK 0x001F /* IN2R_VOL - [4:0] */
1201
#define WM8994_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [4:0] */
1202
#define WM8994_IN2R_VOL_WIDTH 5 /* IN2R_VOL - [4:0] */
1205
* R28 (0x1C) - Left Output Volume
1207
#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */
1208
#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
1209
#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
1210
#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
1211
#define WM8994_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
1212
#define WM8994_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
1213
#define WM8994_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */
1214
#define WM8994_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
1215
#define WM8994_HPOUT1L_MUTE_N 0x0040 /* HPOUT1L_MUTE_N */
1216
#define WM8994_HPOUT1L_MUTE_N_MASK 0x0040 /* HPOUT1L_MUTE_N */
1217
#define WM8994_HPOUT1L_MUTE_N_SHIFT 6 /* HPOUT1L_MUTE_N */
1218
#define WM8994_HPOUT1L_MUTE_N_WIDTH 1 /* HPOUT1L_MUTE_N */
1219
#define WM8994_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */
1220
#define WM8994_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */
1221
#define WM8994_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */
1224
* R29 (0x1D) - Right Output Volume
1226
#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */
1227
#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
1228
#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
1229
#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
1230
#define WM8994_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
1231
#define WM8994_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
1232
#define WM8994_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */
1233
#define WM8994_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
1234
#define WM8994_HPOUT1R_MUTE_N 0x0040 /* HPOUT1R_MUTE_N */
1235
#define WM8994_HPOUT1R_MUTE_N_MASK 0x0040 /* HPOUT1R_MUTE_N */
1236
#define WM8994_HPOUT1R_MUTE_N_SHIFT 6 /* HPOUT1R_MUTE_N */
1237
#define WM8994_HPOUT1R_MUTE_N_WIDTH 1 /* HPOUT1R_MUTE_N */
1238
#define WM8994_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */
1239
#define WM8994_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */
1240
#define WM8994_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */
1243
* R30 (0x1E) - Line Outputs Volume
1245
#define WM8994_LINEOUT1N_MUTE 0x0040 /* LINEOUT1N_MUTE */
1246
#define WM8994_LINEOUT1N_MUTE_MASK 0x0040 /* LINEOUT1N_MUTE */
1247
#define WM8994_LINEOUT1N_MUTE_SHIFT 6 /* LINEOUT1N_MUTE */
1248
#define WM8994_LINEOUT1N_MUTE_WIDTH 1 /* LINEOUT1N_MUTE */
1249
#define WM8994_LINEOUT1P_MUTE 0x0020 /* LINEOUT1P_MUTE */
1250
#define WM8994_LINEOUT1P_MUTE_MASK 0x0020 /* LINEOUT1P_MUTE */
1251
#define WM8994_LINEOUT1P_MUTE_SHIFT 5 /* LINEOUT1P_MUTE */
1252
#define WM8994_LINEOUT1P_MUTE_WIDTH 1 /* LINEOUT1P_MUTE */
1253
#define WM8994_LINEOUT1_VOL 0x0010 /* LINEOUT1_VOL */
1254
#define WM8994_LINEOUT1_VOL_MASK 0x0010 /* LINEOUT1_VOL */
1255
#define WM8994_LINEOUT1_VOL_SHIFT 4 /* LINEOUT1_VOL */
1256
#define WM8994_LINEOUT1_VOL_WIDTH 1 /* LINEOUT1_VOL */
1257
#define WM8994_LINEOUT2N_MUTE 0x0004 /* LINEOUT2N_MUTE */
1258
#define WM8994_LINEOUT2N_MUTE_MASK 0x0004 /* LINEOUT2N_MUTE */
1259
#define WM8994_LINEOUT2N_MUTE_SHIFT 2 /* LINEOUT2N_MUTE */
1260
#define WM8994_LINEOUT2N_MUTE_WIDTH 1 /* LINEOUT2N_MUTE */
1261
#define WM8994_LINEOUT2P_MUTE 0x0002 /* LINEOUT2P_MUTE */
1262
#define WM8994_LINEOUT2P_MUTE_MASK 0x0002 /* LINEOUT2P_MUTE */
1263
#define WM8994_LINEOUT2P_MUTE_SHIFT 1 /* LINEOUT2P_MUTE */
1264
#define WM8994_LINEOUT2P_MUTE_WIDTH 1 /* LINEOUT2P_MUTE */
1265
#define WM8994_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */
1266
#define WM8994_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */
1267
#define WM8994_LINEOUT2_VOL_SHIFT 0 /* LINEOUT2_VOL */
1268
#define WM8994_LINEOUT2_VOL_WIDTH 1 /* LINEOUT2_VOL */
1271
* R31 (0x1F) - HPOUT2 Volume
1273
#define WM8994_HPOUT2_MUTE 0x0020 /* HPOUT2_MUTE */
1274
#define WM8994_HPOUT2_MUTE_MASK 0x0020 /* HPOUT2_MUTE */
1275
#define WM8994_HPOUT2_MUTE_SHIFT 5 /* HPOUT2_MUTE */
1276
#define WM8994_HPOUT2_MUTE_WIDTH 1 /* HPOUT2_MUTE */
1277
#define WM8994_HPOUT2_VOL 0x0010 /* HPOUT2_VOL */
1278
#define WM8994_HPOUT2_VOL_MASK 0x0010 /* HPOUT2_VOL */
1279
#define WM8994_HPOUT2_VOL_SHIFT 4 /* HPOUT2_VOL */
1280
#define WM8994_HPOUT2_VOL_WIDTH 1 /* HPOUT2_VOL */
1283
* R32 (0x20) - Left OPGA Volume
1285
#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */
1286
#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */
1287
#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */
1288
#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */
1289
#define WM8994_MIXOUTL_ZC 0x0080 /* MIXOUTL_ZC */
1290
#define WM8994_MIXOUTL_ZC_MASK 0x0080 /* MIXOUTL_ZC */
1291
#define WM8994_MIXOUTL_ZC_SHIFT 7 /* MIXOUTL_ZC */
1292
#define WM8994_MIXOUTL_ZC_WIDTH 1 /* MIXOUTL_ZC */
1293
#define WM8994_MIXOUTL_MUTE_N 0x0040 /* MIXOUTL_MUTE_N */
1294
#define WM8994_MIXOUTL_MUTE_N_MASK 0x0040 /* MIXOUTL_MUTE_N */
1295
#define WM8994_MIXOUTL_MUTE_N_SHIFT 6 /* MIXOUTL_MUTE_N */
1296
#define WM8994_MIXOUTL_MUTE_N_WIDTH 1 /* MIXOUTL_MUTE_N */
1297
#define WM8994_MIXOUTL_VOL_MASK 0x003F /* MIXOUTL_VOL - [5:0] */
1298
#define WM8994_MIXOUTL_VOL_SHIFT 0 /* MIXOUTL_VOL - [5:0] */
1299
#define WM8994_MIXOUTL_VOL_WIDTH 6 /* MIXOUTL_VOL - [5:0] */
1302
* R33 (0x21) - Right OPGA Volume
1304
#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */
1305
#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */
1306
#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */
1307
#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */
1308
#define WM8994_MIXOUTR_ZC 0x0080 /* MIXOUTR_ZC */
1309
#define WM8994_MIXOUTR_ZC_MASK 0x0080 /* MIXOUTR_ZC */
1310
#define WM8994_MIXOUTR_ZC_SHIFT 7 /* MIXOUTR_ZC */
1311
#define WM8994_MIXOUTR_ZC_WIDTH 1 /* MIXOUTR_ZC */
1312
#define WM8994_MIXOUTR_MUTE_N 0x0040 /* MIXOUTR_MUTE_N */
1313
#define WM8994_MIXOUTR_MUTE_N_MASK 0x0040 /* MIXOUTR_MUTE_N */
1314
#define WM8994_MIXOUTR_MUTE_N_SHIFT 6 /* MIXOUTR_MUTE_N */
1315
#define WM8994_MIXOUTR_MUTE_N_WIDTH 1 /* MIXOUTR_MUTE_N */
1316
#define WM8994_MIXOUTR_VOL_MASK 0x003F /* MIXOUTR_VOL - [5:0] */
1317
#define WM8994_MIXOUTR_VOL_SHIFT 0 /* MIXOUTR_VOL - [5:0] */
1318
#define WM8994_MIXOUTR_VOL_WIDTH 6 /* MIXOUTR_VOL - [5:0] */
1321
* R34 (0x22) - SPKMIXL Attenuation
1323
#define WM8994_DAC2L_SPKMIXL_VOL 0x0040 /* DAC2L_SPKMIXL_VOL */
1324
#define WM8994_DAC2L_SPKMIXL_VOL_MASK 0x0040 /* DAC2L_SPKMIXL_VOL */
1325
#define WM8994_DAC2L_SPKMIXL_VOL_SHIFT 6 /* DAC2L_SPKMIXL_VOL */
1326
#define WM8994_DAC2L_SPKMIXL_VOL_WIDTH 1 /* DAC2L_SPKMIXL_VOL */
1327
#define WM8994_MIXINL_SPKMIXL_VOL 0x0020 /* MIXINL_SPKMIXL_VOL */
1328
#define WM8994_MIXINL_SPKMIXL_VOL_MASK 0x0020 /* MIXINL_SPKMIXL_VOL */
1329
#define WM8994_MIXINL_SPKMIXL_VOL_SHIFT 5 /* MIXINL_SPKMIXL_VOL */
1330
#define WM8994_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */
1331
#define WM8994_IN1LP_SPKMIXL_VOL 0x0010 /* IN1LP_SPKMIXL_VOL */
1332
#define WM8994_IN1LP_SPKMIXL_VOL_MASK 0x0010 /* IN1LP_SPKMIXL_VOL */
1333
#define WM8994_IN1LP_SPKMIXL_VOL_SHIFT 4 /* IN1LP_SPKMIXL_VOL */
1334
#define WM8994_IN1LP_SPKMIXL_VOL_WIDTH 1 /* IN1LP_SPKMIXL_VOL */
1335
#define WM8994_MIXOUTL_SPKMIXL_VOL 0x0008 /* MIXOUTL_SPKMIXL_VOL */
1336
#define WM8994_MIXOUTL_SPKMIXL_VOL_MASK 0x0008 /* MIXOUTL_SPKMIXL_VOL */
1337
#define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT 3 /* MIXOUTL_SPKMIXL_VOL */
1338
#define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH 1 /* MIXOUTL_SPKMIXL_VOL */
1339
#define WM8994_DAC1L_SPKMIXL_VOL 0x0004 /* DAC1L_SPKMIXL_VOL */
1340
#define WM8994_DAC1L_SPKMIXL_VOL_MASK 0x0004 /* DAC1L_SPKMIXL_VOL */
1341
#define WM8994_DAC1L_SPKMIXL_VOL_SHIFT 2 /* DAC1L_SPKMIXL_VOL */
1342
#define WM8994_DAC1L_SPKMIXL_VOL_WIDTH 1 /* DAC1L_SPKMIXL_VOL */
1343
#define WM8994_SPKMIXL_VOL_MASK 0x0003 /* SPKMIXL_VOL - [1:0] */
1344
#define WM8994_SPKMIXL_VOL_SHIFT 0 /* SPKMIXL_VOL - [1:0] */
1345
#define WM8994_SPKMIXL_VOL_WIDTH 2 /* SPKMIXL_VOL - [1:0] */
1348
* R35 (0x23) - SPKMIXR Attenuation
1350
#define WM8994_SPKOUT_CLASSAB 0x0100 /* SPKOUT_CLASSAB */
1351
#define WM8994_SPKOUT_CLASSAB_MASK 0x0100 /* SPKOUT_CLASSAB */
1352
#define WM8994_SPKOUT_CLASSAB_SHIFT 8 /* SPKOUT_CLASSAB */
1353
#define WM8994_SPKOUT_CLASSAB_WIDTH 1 /* SPKOUT_CLASSAB */
1354
#define WM8994_DAC2R_SPKMIXR_VOL 0x0040 /* DAC2R_SPKMIXR_VOL */
1355
#define WM8994_DAC2R_SPKMIXR_VOL_MASK 0x0040 /* DAC2R_SPKMIXR_VOL */
1356
#define WM8994_DAC2R_SPKMIXR_VOL_SHIFT 6 /* DAC2R_SPKMIXR_VOL */
1357
#define WM8994_DAC2R_SPKMIXR_VOL_WIDTH 1 /* DAC2R_SPKMIXR_VOL */
1358
#define WM8994_MIXINR_SPKMIXR_VOL 0x0020 /* MIXINR_SPKMIXR_VOL */
1359
#define WM8994_MIXINR_SPKMIXR_VOL_MASK 0x0020 /* MIXINR_SPKMIXR_VOL */
1360
#define WM8994_MIXINR_SPKMIXR_VOL_SHIFT 5 /* MIXINR_SPKMIXR_VOL */
1361
#define WM8994_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */
1362
#define WM8994_IN1RP_SPKMIXR_VOL 0x0010 /* IN1RP_SPKMIXR_VOL */
1363
#define WM8994_IN1RP_SPKMIXR_VOL_MASK 0x0010 /* IN1RP_SPKMIXR_VOL */
1364
#define WM8994_IN1RP_SPKMIXR_VOL_SHIFT 4 /* IN1RP_SPKMIXR_VOL */
1365
#define WM8994_IN1RP_SPKMIXR_VOL_WIDTH 1 /* IN1RP_SPKMIXR_VOL */
1366
#define WM8994_MIXOUTR_SPKMIXR_VOL 0x0008 /* MIXOUTR_SPKMIXR_VOL */
1367
#define WM8994_MIXOUTR_SPKMIXR_VOL_MASK 0x0008 /* MIXOUTR_SPKMIXR_VOL */
1368
#define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT 3 /* MIXOUTR_SPKMIXR_VOL */
1369
#define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH 1 /* MIXOUTR_SPKMIXR_VOL */
1370
#define WM8994_DAC1R_SPKMIXR_VOL 0x0004 /* DAC1R_SPKMIXR_VOL */
1371
#define WM8994_DAC1R_SPKMIXR_VOL_MASK 0x0004 /* DAC1R_SPKMIXR_VOL */
1372
#define WM8994_DAC1R_SPKMIXR_VOL_SHIFT 2 /* DAC1R_SPKMIXR_VOL */
1373
#define WM8994_DAC1R_SPKMIXR_VOL_WIDTH 1 /* DAC1R_SPKMIXR_VOL */
1374
#define WM8994_SPKMIXR_VOL_MASK 0x0003 /* SPKMIXR_VOL - [1:0] */
1375
#define WM8994_SPKMIXR_VOL_SHIFT 0 /* SPKMIXR_VOL - [1:0] */
1376
#define WM8994_SPKMIXR_VOL_WIDTH 2 /* SPKMIXR_VOL - [1:0] */
1379
* R36 (0x24) - SPKOUT Mixers
1381
#define WM8994_IN2LRP_TO_SPKOUTL 0x0020 /* IN2LRP_TO_SPKOUTL */
1382
#define WM8994_IN2LRP_TO_SPKOUTL_MASK 0x0020 /* IN2LRP_TO_SPKOUTL */
1383
#define WM8994_IN2LRP_TO_SPKOUTL_SHIFT 5 /* IN2LRP_TO_SPKOUTL */
1384
#define WM8994_IN2LRP_TO_SPKOUTL_WIDTH 1 /* IN2LRP_TO_SPKOUTL */
1385
#define WM8994_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */
1386
#define WM8994_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */
1387
#define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */
1388
#define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */
1389
#define WM8994_SPKMIXR_TO_SPKOUTL 0x0008 /* SPKMIXR_TO_SPKOUTL */
1390
#define WM8994_SPKMIXR_TO_SPKOUTL_MASK 0x0008 /* SPKMIXR_TO_SPKOUTL */
1391
#define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT 3 /* SPKMIXR_TO_SPKOUTL */
1392
#define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH 1 /* SPKMIXR_TO_SPKOUTL */
1393
#define WM8994_IN2LRP_TO_SPKOUTR 0x0004 /* IN2LRP_TO_SPKOUTR */
1394
#define WM8994_IN2LRP_TO_SPKOUTR_MASK 0x0004 /* IN2LRP_TO_SPKOUTR */
1395
#define WM8994_IN2LRP_TO_SPKOUTR_SHIFT 2 /* IN2LRP_TO_SPKOUTR */
1396
#define WM8994_IN2LRP_TO_SPKOUTR_WIDTH 1 /* IN2LRP_TO_SPKOUTR */
1397
#define WM8994_SPKMIXL_TO_SPKOUTR 0x0002 /* SPKMIXL_TO_SPKOUTR */
1398
#define WM8994_SPKMIXL_TO_SPKOUTR_MASK 0x0002 /* SPKMIXL_TO_SPKOUTR */
1399
#define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT 1 /* SPKMIXL_TO_SPKOUTR */
1400
#define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH 1 /* SPKMIXL_TO_SPKOUTR */
1401
#define WM8994_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */
1402
#define WM8994_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */
1403
#define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT 0 /* SPKMIXR_TO_SPKOUTR */
1404
#define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH 1 /* SPKMIXR_TO_SPKOUTR */
1407
* R37 (0x25) - ClassD
1409
#define WM8994_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */
1410
#define WM8994_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */
1411
#define WM8994_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */
1412
#define WM8994_SPKOUTR_BOOST_MASK 0x0007 /* SPKOUTR_BOOST - [2:0] */
1413
#define WM8994_SPKOUTR_BOOST_SHIFT 0 /* SPKOUTR_BOOST - [2:0] */
1414
#define WM8994_SPKOUTR_BOOST_WIDTH 3 /* SPKOUTR_BOOST - [2:0] */
1417
* R38 (0x26) - Speaker Volume Left
1419
#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */
1420
#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
1421
#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
1422
#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
1423
#define WM8994_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */
1424
#define WM8994_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */
1425
#define WM8994_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */
1426
#define WM8994_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */
1427
#define WM8994_SPKOUTL_MUTE_N 0x0040 /* SPKOUTL_MUTE_N */
1428
#define WM8994_SPKOUTL_MUTE_N_MASK 0x0040 /* SPKOUTL_MUTE_N */
1429
#define WM8994_SPKOUTL_MUTE_N_SHIFT 6 /* SPKOUTL_MUTE_N */
1430
#define WM8994_SPKOUTL_MUTE_N_WIDTH 1 /* SPKOUTL_MUTE_N */
1431
#define WM8994_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */
1432
#define WM8994_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */
1433
#define WM8994_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */
1436
* R39 (0x27) - Speaker Volume Right
1438
#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */
1439
#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
1440
#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
1441
#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
1442
#define WM8994_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */
1443
#define WM8994_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */
1444
#define WM8994_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */
1445
#define WM8994_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */
1446
#define WM8994_SPKOUTR_MUTE_N 0x0040 /* SPKOUTR_MUTE_N */
1447
#define WM8994_SPKOUTR_MUTE_N_MASK 0x0040 /* SPKOUTR_MUTE_N */
1448
#define WM8994_SPKOUTR_MUTE_N_SHIFT 6 /* SPKOUTR_MUTE_N */
1449
#define WM8994_SPKOUTR_MUTE_N_WIDTH 1 /* SPKOUTR_MUTE_N */
1450
#define WM8994_SPKOUTR_VOL_MASK 0x003F /* SPKOUTR_VOL - [5:0] */
1451
#define WM8994_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [5:0] */
1452
#define WM8994_SPKOUTR_VOL_WIDTH 6 /* SPKOUTR_VOL - [5:0] */
1455
* R40 (0x28) - Input Mixer (2)
1457
#define WM8994_IN2LP_TO_IN2L 0x0080 /* IN2LP_TO_IN2L */
1458
#define WM8994_IN2LP_TO_IN2L_MASK 0x0080 /* IN2LP_TO_IN2L */
1459
#define WM8994_IN2LP_TO_IN2L_SHIFT 7 /* IN2LP_TO_IN2L */
1460
#define WM8994_IN2LP_TO_IN2L_WIDTH 1 /* IN2LP_TO_IN2L */
1461
#define WM8994_IN2LN_TO_IN2L 0x0040 /* IN2LN_TO_IN2L */
1462
#define WM8994_IN2LN_TO_IN2L_MASK 0x0040 /* IN2LN_TO_IN2L */
1463
#define WM8994_IN2LN_TO_IN2L_SHIFT 6 /* IN2LN_TO_IN2L */
1464
#define WM8994_IN2LN_TO_IN2L_WIDTH 1 /* IN2LN_TO_IN2L */
1465
#define WM8994_IN1LP_TO_IN1L 0x0020 /* IN1LP_TO_IN1L */
1466
#define WM8994_IN1LP_TO_IN1L_MASK 0x0020 /* IN1LP_TO_IN1L */
1467
#define WM8994_IN1LP_TO_IN1L_SHIFT 5 /* IN1LP_TO_IN1L */
1468
#define WM8994_IN1LP_TO_IN1L_WIDTH 1 /* IN1LP_TO_IN1L */
1469
#define WM8994_IN1LN_TO_IN1L 0x0010 /* IN1LN_TO_IN1L */
1470
#define WM8994_IN1LN_TO_IN1L_MASK 0x0010 /* IN1LN_TO_IN1L */
1471
#define WM8994_IN1LN_TO_IN1L_SHIFT 4 /* IN1LN_TO_IN1L */
1472
#define WM8994_IN1LN_TO_IN1L_WIDTH 1 /* IN1LN_TO_IN1L */
1473
#define WM8994_IN2RP_TO_IN2R 0x0008 /* IN2RP_TO_IN2R */
1474
#define WM8994_IN2RP_TO_IN2R_MASK 0x0008 /* IN2RP_TO_IN2R */
1475
#define WM8994_IN2RP_TO_IN2R_SHIFT 3 /* IN2RP_TO_IN2R */
1476
#define WM8994_IN2RP_TO_IN2R_WIDTH 1 /* IN2RP_TO_IN2R */
1477
#define WM8994_IN2RN_TO_IN2R 0x0004 /* IN2RN_TO_IN2R */
1478
#define WM8994_IN2RN_TO_IN2R_MASK 0x0004 /* IN2RN_TO_IN2R */
1479
#define WM8994_IN2RN_TO_IN2R_SHIFT 2 /* IN2RN_TO_IN2R */
1480
#define WM8994_IN2RN_TO_IN2R_WIDTH 1 /* IN2RN_TO_IN2R */
1481
#define WM8994_IN1RP_TO_IN1R 0x0002 /* IN1RP_TO_IN1R */
1482
#define WM8994_IN1RP_TO_IN1R_MASK 0x0002 /* IN1RP_TO_IN1R */
1483
#define WM8994_IN1RP_TO_IN1R_SHIFT 1 /* IN1RP_TO_IN1R */
1484
#define WM8994_IN1RP_TO_IN1R_WIDTH 1 /* IN1RP_TO_IN1R */
1485
#define WM8994_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */
1486
#define WM8994_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */
1487
#define WM8994_IN1RN_TO_IN1R_SHIFT 0 /* IN1RN_TO_IN1R */
1488
#define WM8994_IN1RN_TO_IN1R_WIDTH 1 /* IN1RN_TO_IN1R */
1491
* R41 (0x29) - Input Mixer (3)
1493
#define WM8994_IN2L_TO_MIXINL 0x0100 /* IN2L_TO_MIXINL */
1494
#define WM8994_IN2L_TO_MIXINL_MASK 0x0100 /* IN2L_TO_MIXINL */
1495
#define WM8994_IN2L_TO_MIXINL_SHIFT 8 /* IN2L_TO_MIXINL */
1496
#define WM8994_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */
1497
#define WM8994_IN2L_MIXINL_VOL 0x0080 /* IN2L_MIXINL_VOL */
1498
#define WM8994_IN2L_MIXINL_VOL_MASK 0x0080 /* IN2L_MIXINL_VOL */
1499
#define WM8994_IN2L_MIXINL_VOL_SHIFT 7 /* IN2L_MIXINL_VOL */
1500
#define WM8994_IN2L_MIXINL_VOL_WIDTH 1 /* IN2L_MIXINL_VOL */
1501
#define WM8994_IN1L_TO_MIXINL 0x0020 /* IN1L_TO_MIXINL */
1502
#define WM8994_IN1L_TO_MIXINL_MASK 0x0020 /* IN1L_TO_MIXINL */
1503
#define WM8994_IN1L_TO_MIXINL_SHIFT 5 /* IN1L_TO_MIXINL */
1504
#define WM8994_IN1L_TO_MIXINL_WIDTH 1 /* IN1L_TO_MIXINL */
1505
#define WM8994_IN1L_MIXINL_VOL 0x0010 /* IN1L_MIXINL_VOL */
1506
#define WM8994_IN1L_MIXINL_VOL_MASK 0x0010 /* IN1L_MIXINL_VOL */
1507
#define WM8994_IN1L_MIXINL_VOL_SHIFT 4 /* IN1L_MIXINL_VOL */
1508
#define WM8994_IN1L_MIXINL_VOL_WIDTH 1 /* IN1L_MIXINL_VOL */
1509
#define WM8994_MIXOUTL_MIXINL_VOL_MASK 0x0007 /* MIXOUTL_MIXINL_VOL - [2:0] */
1510
#define WM8994_MIXOUTL_MIXINL_VOL_SHIFT 0 /* MIXOUTL_MIXINL_VOL - [2:0] */
1511
#define WM8994_MIXOUTL_MIXINL_VOL_WIDTH 3 /* MIXOUTL_MIXINL_VOL - [2:0] */
1514
* R42 (0x2A) - Input Mixer (4)
1516
#define WM8994_IN2R_TO_MIXINR 0x0100 /* IN2R_TO_MIXINR */
1517
#define WM8994_IN2R_TO_MIXINR_MASK 0x0100 /* IN2R_TO_MIXINR */
1518
#define WM8994_IN2R_TO_MIXINR_SHIFT 8 /* IN2R_TO_MIXINR */
1519
#define WM8994_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */
1520
#define WM8994_IN2R_MIXINR_VOL 0x0080 /* IN2R_MIXINR_VOL */
1521
#define WM8994_IN2R_MIXINR_VOL_MASK 0x0080 /* IN2R_MIXINR_VOL */
1522
#define WM8994_IN2R_MIXINR_VOL_SHIFT 7 /* IN2R_MIXINR_VOL */
1523
#define WM8994_IN2R_MIXINR_VOL_WIDTH 1 /* IN2R_MIXINR_VOL */
1524
#define WM8994_IN1R_TO_MIXINR 0x0020 /* IN1R_TO_MIXINR */
1525
#define WM8994_IN1R_TO_MIXINR_MASK 0x0020 /* IN1R_TO_MIXINR */
1526
#define WM8994_IN1R_TO_MIXINR_SHIFT 5 /* IN1R_TO_MIXINR */
1527
#define WM8994_IN1R_TO_MIXINR_WIDTH 1 /* IN1R_TO_MIXINR */
1528
#define WM8994_IN1R_MIXINR_VOL 0x0010 /* IN1R_MIXINR_VOL */
1529
#define WM8994_IN1R_MIXINR_VOL_MASK 0x0010 /* IN1R_MIXINR_VOL */
1530
#define WM8994_IN1R_MIXINR_VOL_SHIFT 4 /* IN1R_MIXINR_VOL */
1531
#define WM8994_IN1R_MIXINR_VOL_WIDTH 1 /* IN1R_MIXINR_VOL */
1532
#define WM8994_MIXOUTR_MIXINR_VOL_MASK 0x0007 /* MIXOUTR_MIXINR_VOL - [2:0] */
1533
#define WM8994_MIXOUTR_MIXINR_VOL_SHIFT 0 /* MIXOUTR_MIXINR_VOL - [2:0] */
1534
#define WM8994_MIXOUTR_MIXINR_VOL_WIDTH 3 /* MIXOUTR_MIXINR_VOL - [2:0] */
1537
* R43 (0x2B) - Input Mixer (5)
1539
#define WM8994_IN1LP_MIXINL_VOL_MASK 0x01C0 /* IN1LP_MIXINL_VOL - [8:6] */
1540
#define WM8994_IN1LP_MIXINL_VOL_SHIFT 6 /* IN1LP_MIXINL_VOL - [8:6] */
1541
#define WM8994_IN1LP_MIXINL_VOL_WIDTH 3 /* IN1LP_MIXINL_VOL - [8:6] */
1542
#define WM8994_IN2LRP_MIXINL_VOL_MASK 0x0007 /* IN2LRP_MIXINL_VOL - [2:0] */
1543
#define WM8994_IN2LRP_MIXINL_VOL_SHIFT 0 /* IN2LRP_MIXINL_VOL - [2:0] */
1544
#define WM8994_IN2LRP_MIXINL_VOL_WIDTH 3 /* IN2LRP_MIXINL_VOL - [2:0] */
1547
* R44 (0x2C) - Input Mixer (6)
1549
#define WM8994_IN1RP_MIXINR_VOL_MASK 0x01C0 /* IN1RP_MIXINR_VOL - [8:6] */
1550
#define WM8994_IN1RP_MIXINR_VOL_SHIFT 6 /* IN1RP_MIXINR_VOL - [8:6] */
1551
#define WM8994_IN1RP_MIXINR_VOL_WIDTH 3 /* IN1RP_MIXINR_VOL - [8:6] */
1552
#define WM8994_IN2LRP_MIXINR_VOL_MASK 0x0007 /* IN2LRP_MIXINR_VOL - [2:0] */
1553
#define WM8994_IN2LRP_MIXINR_VOL_SHIFT 0 /* IN2LRP_MIXINR_VOL - [2:0] */
1554
#define WM8994_IN2LRP_MIXINR_VOL_WIDTH 3 /* IN2LRP_MIXINR_VOL - [2:0] */
1557
* R45 (0x2D) - Output Mixer (1)
1559
#define WM8994_DAC1L_TO_HPOUT1L 0x0100 /* DAC1L_TO_HPOUT1L */
1560
#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 /* DAC1L_TO_HPOUT1L */
1561
#define WM8994_DAC1L_TO_HPOUT1L_SHIFT 8 /* DAC1L_TO_HPOUT1L */
1562
#define WM8994_DAC1L_TO_HPOUT1L_WIDTH 1 /* DAC1L_TO_HPOUT1L */
1563
#define WM8994_MIXINR_TO_MIXOUTL 0x0080 /* MIXINR_TO_MIXOUTL */
1564
#define WM8994_MIXINR_TO_MIXOUTL_MASK 0x0080 /* MIXINR_TO_MIXOUTL */
1565
#define WM8994_MIXINR_TO_MIXOUTL_SHIFT 7 /* MIXINR_TO_MIXOUTL */
1566
#define WM8994_MIXINR_TO_MIXOUTL_WIDTH 1 /* MIXINR_TO_MIXOUTL */
1567
#define WM8994_MIXINL_TO_MIXOUTL 0x0040 /* MIXINL_TO_MIXOUTL */
1568
#define WM8994_MIXINL_TO_MIXOUTL_MASK 0x0040 /* MIXINL_TO_MIXOUTL */
1569
#define WM8994_MIXINL_TO_MIXOUTL_SHIFT 6 /* MIXINL_TO_MIXOUTL */
1570
#define WM8994_MIXINL_TO_MIXOUTL_WIDTH 1 /* MIXINL_TO_MIXOUTL */
1571
#define WM8994_IN2RN_TO_MIXOUTL 0x0020 /* IN2RN_TO_MIXOUTL */
1572
#define WM8994_IN2RN_TO_MIXOUTL_MASK 0x0020 /* IN2RN_TO_MIXOUTL */
1573
#define WM8994_IN2RN_TO_MIXOUTL_SHIFT 5 /* IN2RN_TO_MIXOUTL */
1574
#define WM8994_IN2RN_TO_MIXOUTL_WIDTH 1 /* IN2RN_TO_MIXOUTL */
1575
#define WM8994_IN2LN_TO_MIXOUTL 0x0010 /* IN2LN_TO_MIXOUTL */
1576
#define WM8994_IN2LN_TO_MIXOUTL_MASK 0x0010 /* IN2LN_TO_MIXOUTL */
1577
#define WM8994_IN2LN_TO_MIXOUTL_SHIFT 4 /* IN2LN_TO_MIXOUTL */
1578
#define WM8994_IN2LN_TO_MIXOUTL_WIDTH 1 /* IN2LN_TO_MIXOUTL */
1579
#define WM8994_IN1R_TO_MIXOUTL 0x0008 /* IN1R_TO_MIXOUTL */
1580
#define WM8994_IN1R_TO_MIXOUTL_MASK 0x0008 /* IN1R_TO_MIXOUTL */
1581
#define WM8994_IN1R_TO_MIXOUTL_SHIFT 3 /* IN1R_TO_MIXOUTL */
1582
#define WM8994_IN1R_TO_MIXOUTL_WIDTH 1 /* IN1R_TO_MIXOUTL */
1583
#define WM8994_IN1L_TO_MIXOUTL 0x0004 /* IN1L_TO_MIXOUTL */
1584
#define WM8994_IN1L_TO_MIXOUTL_MASK 0x0004 /* IN1L_TO_MIXOUTL */
1585
#define WM8994_IN1L_TO_MIXOUTL_SHIFT 2 /* IN1L_TO_MIXOUTL */
1586
#define WM8994_IN1L_TO_MIXOUTL_WIDTH 1 /* IN1L_TO_MIXOUTL */
1587
#define WM8994_IN2LP_TO_MIXOUTL 0x0002 /* IN2LP_TO_MIXOUTL */
1588
#define WM8994_IN2LP_TO_MIXOUTL_MASK 0x0002 /* IN2LP_TO_MIXOUTL */
1589
#define WM8994_IN2LP_TO_MIXOUTL_SHIFT 1 /* IN2LP_TO_MIXOUTL */
1590
#define WM8994_IN2LP_TO_MIXOUTL_WIDTH 1 /* IN2LP_TO_MIXOUTL */
1591
#define WM8994_DAC1L_TO_MIXOUTL 0x0001 /* DAC1L_TO_MIXOUTL */
1592
#define WM8994_DAC1L_TO_MIXOUTL_MASK 0x0001 /* DAC1L_TO_MIXOUTL */
1593
#define WM8994_DAC1L_TO_MIXOUTL_SHIFT 0 /* DAC1L_TO_MIXOUTL */
1594
#define WM8994_DAC1L_TO_MIXOUTL_WIDTH 1 /* DAC1L_TO_MIXOUTL */
1597
* R46 (0x2E) - Output Mixer (2)
1599
#define WM8994_DAC1R_TO_HPOUT1R 0x0100 /* DAC1R_TO_HPOUT1R */
1600
#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 /* DAC1R_TO_HPOUT1R */
1601
#define WM8994_DAC1R_TO_HPOUT1R_SHIFT 8 /* DAC1R_TO_HPOUT1R */
1602
#define WM8994_DAC1R_TO_HPOUT1R_WIDTH 1 /* DAC1R_TO_HPOUT1R */
1603
#define WM8994_MIXINL_TO_MIXOUTR 0x0080 /* MIXINL_TO_MIXOUTR */
1604
#define WM8994_MIXINL_TO_MIXOUTR_MASK 0x0080 /* MIXINL_TO_MIXOUTR */
1605
#define WM8994_MIXINL_TO_MIXOUTR_SHIFT 7 /* MIXINL_TO_MIXOUTR */
1606
#define WM8994_MIXINL_TO_MIXOUTR_WIDTH 1 /* MIXINL_TO_MIXOUTR */
1607
#define WM8994_MIXINR_TO_MIXOUTR 0x0040 /* MIXINR_TO_MIXOUTR */
1608
#define WM8994_MIXINR_TO_MIXOUTR_MASK 0x0040 /* MIXINR_TO_MIXOUTR */
1609
#define WM8994_MIXINR_TO_MIXOUTR_SHIFT 6 /* MIXINR_TO_MIXOUTR */
1610
#define WM8994_MIXINR_TO_MIXOUTR_WIDTH 1 /* MIXINR_TO_MIXOUTR */
1611
#define WM8994_IN2LN_TO_MIXOUTR 0x0020 /* IN2LN_TO_MIXOUTR */
1612
#define WM8994_IN2LN_TO_MIXOUTR_MASK 0x0020 /* IN2LN_TO_MIXOUTR */
1613
#define WM8994_IN2LN_TO_MIXOUTR_SHIFT 5 /* IN2LN_TO_MIXOUTR */
1614
#define WM8994_IN2LN_TO_MIXOUTR_WIDTH 1 /* IN2LN_TO_MIXOUTR */
1615
#define WM8994_IN2RN_TO_MIXOUTR 0x0010 /* IN2RN_TO_MIXOUTR */
1616
#define WM8994_IN2RN_TO_MIXOUTR_MASK 0x0010 /* IN2RN_TO_MIXOUTR */
1617
#define WM8994_IN2RN_TO_MIXOUTR_SHIFT 4 /* IN2RN_TO_MIXOUTR */
1618
#define WM8994_IN2RN_TO_MIXOUTR_WIDTH 1 /* IN2RN_TO_MIXOUTR */
1619
#define WM8994_IN1L_TO_MIXOUTR 0x0008 /* IN1L_TO_MIXOUTR */
1620
#define WM8994_IN1L_TO_MIXOUTR_MASK 0x0008 /* IN1L_TO_MIXOUTR */
1621
#define WM8994_IN1L_TO_MIXOUTR_SHIFT 3 /* IN1L_TO_MIXOUTR */
1622
#define WM8994_IN1L_TO_MIXOUTR_WIDTH 1 /* IN1L_TO_MIXOUTR */
1623
#define WM8994_IN1R_TO_MIXOUTR 0x0004 /* IN1R_TO_MIXOUTR */
1624
#define WM8994_IN1R_TO_MIXOUTR_MASK 0x0004 /* IN1R_TO_MIXOUTR */
1625
#define WM8994_IN1R_TO_MIXOUTR_SHIFT 2 /* IN1R_TO_MIXOUTR */
1626
#define WM8994_IN1R_TO_MIXOUTR_WIDTH 1 /* IN1R_TO_MIXOUTR */
1627
#define WM8994_IN2RP_TO_MIXOUTR 0x0002 /* IN2RP_TO_MIXOUTR */
1628
#define WM8994_IN2RP_TO_MIXOUTR_MASK 0x0002 /* IN2RP_TO_MIXOUTR */
1629
#define WM8994_IN2RP_TO_MIXOUTR_SHIFT 1 /* IN2RP_TO_MIXOUTR */
1630
#define WM8994_IN2RP_TO_MIXOUTR_WIDTH 1 /* IN2RP_TO_MIXOUTR */
1631
#define WM8994_DAC1R_TO_MIXOUTR 0x0001 /* DAC1R_TO_MIXOUTR */
1632
#define WM8994_DAC1R_TO_MIXOUTR_MASK 0x0001 /* DAC1R_TO_MIXOUTR */
1633
#define WM8994_DAC1R_TO_MIXOUTR_SHIFT 0 /* DAC1R_TO_MIXOUTR */
1634
#define WM8994_DAC1R_TO_MIXOUTR_WIDTH 1 /* DAC1R_TO_MIXOUTR */
1637
* R47 (0x2F) - Output Mixer (3)
1639
#define WM8994_IN2LP_MIXOUTL_VOL_MASK 0x0E00 /* IN2LP_MIXOUTL_VOL - [11:9] */
1640
#define WM8994_IN2LP_MIXOUTL_VOL_SHIFT 9 /* IN2LP_MIXOUTL_VOL - [11:9] */
1641
#define WM8994_IN2LP_MIXOUTL_VOL_WIDTH 3 /* IN2LP_MIXOUTL_VOL - [11:9] */
1642
#define WM8994_IN2LN_MIXOUTL_VOL_MASK 0x01C0 /* IN2LN_MIXOUTL_VOL - [8:6] */
1643
#define WM8994_IN2LN_MIXOUTL_VOL_SHIFT 6 /* IN2LN_MIXOUTL_VOL - [8:6] */
1644
#define WM8994_IN2LN_MIXOUTL_VOL_WIDTH 3 /* IN2LN_MIXOUTL_VOL - [8:6] */
1645
#define WM8994_IN1R_MIXOUTL_VOL_MASK 0x0038 /* IN1R_MIXOUTL_VOL - [5:3] */
1646
#define WM8994_IN1R_MIXOUTL_VOL_SHIFT 3 /* IN1R_MIXOUTL_VOL - [5:3] */
1647
#define WM8994_IN1R_MIXOUTL_VOL_WIDTH 3 /* IN1R_MIXOUTL_VOL - [5:3] */
1648
#define WM8994_IN1L_MIXOUTL_VOL_MASK 0x0007 /* IN1L_MIXOUTL_VOL - [2:0] */
1649
#define WM8994_IN1L_MIXOUTL_VOL_SHIFT 0 /* IN1L_MIXOUTL_VOL - [2:0] */
1650
#define WM8994_IN1L_MIXOUTL_VOL_WIDTH 3 /* IN1L_MIXOUTL_VOL - [2:0] */
1653
* R48 (0x30) - Output Mixer (4)
1655
#define WM8994_IN2RP_MIXOUTR_VOL_MASK 0x0E00 /* IN2RP_MIXOUTR_VOL - [11:9] */
1656
#define WM8994_IN2RP_MIXOUTR_VOL_SHIFT 9 /* IN2RP_MIXOUTR_VOL - [11:9] */
1657
#define WM8994_IN2RP_MIXOUTR_VOL_WIDTH 3 /* IN2RP_MIXOUTR_VOL - [11:9] */
1658
#define WM8994_IN2RN_MIXOUTR_VOL_MASK 0x01C0 /* IN2RN_MIXOUTR_VOL - [8:6] */
1659
#define WM8994_IN2RN_MIXOUTR_VOL_SHIFT 6 /* IN2RN_MIXOUTR_VOL - [8:6] */
1660
#define WM8994_IN2RN_MIXOUTR_VOL_WIDTH 3 /* IN2RN_MIXOUTR_VOL - [8:6] */
1661
#define WM8994_IN1L_MIXOUTR_VOL_MASK 0x0038 /* IN1L_MIXOUTR_VOL - [5:3] */
1662
#define WM8994_IN1L_MIXOUTR_VOL_SHIFT 3 /* IN1L_MIXOUTR_VOL - [5:3] */
1663
#define WM8994_IN1L_MIXOUTR_VOL_WIDTH 3 /* IN1L_MIXOUTR_VOL - [5:3] */
1664
#define WM8994_IN1R_MIXOUTR_VOL_MASK 0x0007 /* IN1R_MIXOUTR_VOL - [2:0] */
1665
#define WM8994_IN1R_MIXOUTR_VOL_SHIFT 0 /* IN1R_MIXOUTR_VOL - [2:0] */
1666
#define WM8994_IN1R_MIXOUTR_VOL_WIDTH 3 /* IN1R_MIXOUTR_VOL - [2:0] */
1669
* R49 (0x31) - Output Mixer (5)
1671
#define WM8994_DAC1L_MIXOUTL_VOL_MASK 0x0E00 /* DAC1L_MIXOUTL_VOL - [11:9] */
1672
#define WM8994_DAC1L_MIXOUTL_VOL_SHIFT 9 /* DAC1L_MIXOUTL_VOL - [11:9] */
1673
#define WM8994_DAC1L_MIXOUTL_VOL_WIDTH 3 /* DAC1L_MIXOUTL_VOL - [11:9] */
1674
#define WM8994_IN2RN_MIXOUTL_VOL_MASK 0x01C0 /* IN2RN_MIXOUTL_VOL - [8:6] */
1675
#define WM8994_IN2RN_MIXOUTL_VOL_SHIFT 6 /* IN2RN_MIXOUTL_VOL - [8:6] */
1676
#define WM8994_IN2RN_MIXOUTL_VOL_WIDTH 3 /* IN2RN_MIXOUTL_VOL - [8:6] */
1677
#define WM8994_MIXINR_MIXOUTL_VOL_MASK 0x0038 /* MIXINR_MIXOUTL_VOL - [5:3] */
1678
#define WM8994_MIXINR_MIXOUTL_VOL_SHIFT 3 /* MIXINR_MIXOUTL_VOL - [5:3] */
1679
#define WM8994_MIXINR_MIXOUTL_VOL_WIDTH 3 /* MIXINR_MIXOUTL_VOL - [5:3] */
1680
#define WM8994_MIXINL_MIXOUTL_VOL_MASK 0x0007 /* MIXINL_MIXOUTL_VOL - [2:0] */
1681
#define WM8994_MIXINL_MIXOUTL_VOL_SHIFT 0 /* MIXINL_MIXOUTL_VOL - [2:0] */
1682
#define WM8994_MIXINL_MIXOUTL_VOL_WIDTH 3 /* MIXINL_MIXOUTL_VOL - [2:0] */
1685
* R50 (0x32) - Output Mixer (6)
1687
#define WM8994_DAC1R_MIXOUTR_VOL_MASK 0x0E00 /* DAC1R_MIXOUTR_VOL - [11:9] */
1688
#define WM8994_DAC1R_MIXOUTR_VOL_SHIFT 9 /* DAC1R_MIXOUTR_VOL - [11:9] */
1689
#define WM8994_DAC1R_MIXOUTR_VOL_WIDTH 3 /* DAC1R_MIXOUTR_VOL - [11:9] */
1690
#define WM8994_IN2LN_MIXOUTR_VOL_MASK 0x01C0 /* IN2LN_MIXOUTR_VOL - [8:6] */
1691
#define WM8994_IN2LN_MIXOUTR_VOL_SHIFT 6 /* IN2LN_MIXOUTR_VOL - [8:6] */
1692
#define WM8994_IN2LN_MIXOUTR_VOL_WIDTH 3 /* IN2LN_MIXOUTR_VOL - [8:6] */
1693
#define WM8994_MIXINL_MIXOUTR_VOL_MASK 0x0038 /* MIXINL_MIXOUTR_VOL - [5:3] */
1694
#define WM8994_MIXINL_MIXOUTR_VOL_SHIFT 3 /* MIXINL_MIXOUTR_VOL - [5:3] */
1695
#define WM8994_MIXINL_MIXOUTR_VOL_WIDTH 3 /* MIXINL_MIXOUTR_VOL - [5:3] */
1696
#define WM8994_MIXINR_MIXOUTR_VOL_MASK 0x0007 /* MIXINR_MIXOUTR_VOL - [2:0] */
1697
#define WM8994_MIXINR_MIXOUTR_VOL_SHIFT 0 /* MIXINR_MIXOUTR_VOL - [2:0] */
1698
#define WM8994_MIXINR_MIXOUTR_VOL_WIDTH 3 /* MIXINR_MIXOUTR_VOL - [2:0] */
1701
* R51 (0x33) - HPOUT2 Mixer
1703
#define WM8994_IN2LRP_TO_HPOUT2 0x0020 /* IN2LRP_TO_HPOUT2 */
1704
#define WM8994_IN2LRP_TO_HPOUT2_MASK 0x0020 /* IN2LRP_TO_HPOUT2 */
1705
#define WM8994_IN2LRP_TO_HPOUT2_SHIFT 5 /* IN2LRP_TO_HPOUT2 */
1706
#define WM8994_IN2LRP_TO_HPOUT2_WIDTH 1 /* IN2LRP_TO_HPOUT2 */
1707
#define WM8994_MIXOUTLVOL_TO_HPOUT2 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */
1708
#define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */
1709
#define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT 4 /* MIXOUTLVOL_TO_HPOUT2 */
1710
#define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTLVOL_TO_HPOUT2 */
1711
#define WM8994_MIXOUTRVOL_TO_HPOUT2 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */
1712
#define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */
1713
#define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT 3 /* MIXOUTRVOL_TO_HPOUT2 */
1714
#define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTRVOL_TO_HPOUT2 */
1717
* R52 (0x34) - Line Mixer (1)
1719
#define WM8994_MIXOUTL_TO_LINEOUT1N 0x0040 /* MIXOUTL_TO_LINEOUT1N */
1720
#define WM8994_MIXOUTL_TO_LINEOUT1N_MASK 0x0040 /* MIXOUTL_TO_LINEOUT1N */
1721
#define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT 6 /* MIXOUTL_TO_LINEOUT1N */
1722
#define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH 1 /* MIXOUTL_TO_LINEOUT1N */
1723
#define WM8994_MIXOUTR_TO_LINEOUT1N 0x0020 /* MIXOUTR_TO_LINEOUT1N */
1724
#define WM8994_MIXOUTR_TO_LINEOUT1N_MASK 0x0020 /* MIXOUTR_TO_LINEOUT1N */
1725
#define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT 5 /* MIXOUTR_TO_LINEOUT1N */
1726
#define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH 1 /* MIXOUTR_TO_LINEOUT1N */
1727
#define WM8994_LINEOUT1_MODE 0x0010 /* LINEOUT1_MODE */
1728
#define WM8994_LINEOUT1_MODE_MASK 0x0010 /* LINEOUT1_MODE */
1729
#define WM8994_LINEOUT1_MODE_SHIFT 4 /* LINEOUT1_MODE */
1730
#define WM8994_LINEOUT1_MODE_WIDTH 1 /* LINEOUT1_MODE */
1731
#define WM8994_IN1R_TO_LINEOUT1P 0x0004 /* IN1R_TO_LINEOUT1P */
1732
#define WM8994_IN1R_TO_LINEOUT1P_MASK 0x0004 /* IN1R_TO_LINEOUT1P */
1733
#define WM8994_IN1R_TO_LINEOUT1P_SHIFT 2 /* IN1R_TO_LINEOUT1P */
1734
#define WM8994_IN1R_TO_LINEOUT1P_WIDTH 1 /* IN1R_TO_LINEOUT1P */
1735
#define WM8994_IN1L_TO_LINEOUT1P 0x0002 /* IN1L_TO_LINEOUT1P */
1736
#define WM8994_IN1L_TO_LINEOUT1P_MASK 0x0002 /* IN1L_TO_LINEOUT1P */
1737
#define WM8994_IN1L_TO_LINEOUT1P_SHIFT 1 /* IN1L_TO_LINEOUT1P */
1738
#define WM8994_IN1L_TO_LINEOUT1P_WIDTH 1 /* IN1L_TO_LINEOUT1P */
1739
#define WM8994_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */
1740
#define WM8994_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */
1741
#define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT 0 /* MIXOUTL_TO_LINEOUT1P */
1742
#define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH 1 /* MIXOUTL_TO_LINEOUT1P */
1745
* R53 (0x35) - Line Mixer (2)
1747
#define WM8994_MIXOUTR_TO_LINEOUT2N 0x0040 /* MIXOUTR_TO_LINEOUT2N */
1748
#define WM8994_MIXOUTR_TO_LINEOUT2N_MASK 0x0040 /* MIXOUTR_TO_LINEOUT2N */
1749
#define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT 6 /* MIXOUTR_TO_LINEOUT2N */
1750
#define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH 1 /* MIXOUTR_TO_LINEOUT2N */
1751
#define WM8994_MIXOUTL_TO_LINEOUT2N 0x0020 /* MIXOUTL_TO_LINEOUT2N */
1752
#define WM8994_MIXOUTL_TO_LINEOUT2N_MASK 0x0020 /* MIXOUTL_TO_LINEOUT2N */
1753
#define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT 5 /* MIXOUTL_TO_LINEOUT2N */
1754
#define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH 1 /* MIXOUTL_TO_LINEOUT2N */
1755
#define WM8994_LINEOUT2_MODE 0x0010 /* LINEOUT2_MODE */
1756
#define WM8994_LINEOUT2_MODE_MASK 0x0010 /* LINEOUT2_MODE */
1757
#define WM8994_LINEOUT2_MODE_SHIFT 4 /* LINEOUT2_MODE */
1758
#define WM8994_LINEOUT2_MODE_WIDTH 1 /* LINEOUT2_MODE */
1759
#define WM8994_IN1L_TO_LINEOUT2P 0x0004 /* IN1L_TO_LINEOUT2P */
1760
#define WM8994_IN1L_TO_LINEOUT2P_MASK 0x0004 /* IN1L_TO_LINEOUT2P */
1761
#define WM8994_IN1L_TO_LINEOUT2P_SHIFT 2 /* IN1L_TO_LINEOUT2P */
1762
#define WM8994_IN1L_TO_LINEOUT2P_WIDTH 1 /* IN1L_TO_LINEOUT2P */
1763
#define WM8994_IN1R_TO_LINEOUT2P 0x0002 /* IN1R_TO_LINEOUT2P */
1764
#define WM8994_IN1R_TO_LINEOUT2P_MASK 0x0002 /* IN1R_TO_LINEOUT2P */
1765
#define WM8994_IN1R_TO_LINEOUT2P_SHIFT 1 /* IN1R_TO_LINEOUT2P */
1766
#define WM8994_IN1R_TO_LINEOUT2P_WIDTH 1 /* IN1R_TO_LINEOUT2P */
1767
#define WM8994_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */
1768
#define WM8994_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */
1769
#define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT 0 /* MIXOUTR_TO_LINEOUT2P */
1770
#define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH 1 /* MIXOUTR_TO_LINEOUT2P */
1773
* R54 (0x36) - Speaker Mixer
1775
#define WM8994_DAC2L_TO_SPKMIXL 0x0200 /* DAC2L_TO_SPKMIXL */
1776
#define WM8994_DAC2L_TO_SPKMIXL_MASK 0x0200 /* DAC2L_TO_SPKMIXL */
1777
#define WM8994_DAC2L_TO_SPKMIXL_SHIFT 9 /* DAC2L_TO_SPKMIXL */
1778
#define WM8994_DAC2L_TO_SPKMIXL_WIDTH 1 /* DAC2L_TO_SPKMIXL */
1779
#define WM8994_DAC2R_TO_SPKMIXR 0x0100 /* DAC2R_TO_SPKMIXR */
1780
#define WM8994_DAC2R_TO_SPKMIXR_MASK 0x0100 /* DAC2R_TO_SPKMIXR */
1781
#define WM8994_DAC2R_TO_SPKMIXR_SHIFT 8 /* DAC2R_TO_SPKMIXR */
1782
#define WM8994_DAC2R_TO_SPKMIXR_WIDTH 1 /* DAC2R_TO_SPKMIXR */
1783
#define WM8994_MIXINL_TO_SPKMIXL 0x0080 /* MIXINL_TO_SPKMIXL */
1784
#define WM8994_MIXINL_TO_SPKMIXL_MASK 0x0080 /* MIXINL_TO_SPKMIXL */
1785
#define WM8994_MIXINL_TO_SPKMIXL_SHIFT 7 /* MIXINL_TO_SPKMIXL */
1786
#define WM8994_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */
1787
#define WM8994_MIXINR_TO_SPKMIXR 0x0040 /* MIXINR_TO_SPKMIXR */
1788
#define WM8994_MIXINR_TO_SPKMIXR_MASK 0x0040 /* MIXINR_TO_SPKMIXR */
1789
#define WM8994_MIXINR_TO_SPKMIXR_SHIFT 6 /* MIXINR_TO_SPKMIXR */
1790
#define WM8994_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */
1791
#define WM8994_IN1LP_TO_SPKMIXL 0x0020 /* IN1LP_TO_SPKMIXL */
1792
#define WM8994_IN1LP_TO_SPKMIXL_MASK 0x0020 /* IN1LP_TO_SPKMIXL */
1793
#define WM8994_IN1LP_TO_SPKMIXL_SHIFT 5 /* IN1LP_TO_SPKMIXL */
1794
#define WM8994_IN1LP_TO_SPKMIXL_WIDTH 1 /* IN1LP_TO_SPKMIXL */
1795
#define WM8994_IN1RP_TO_SPKMIXR 0x0010 /* IN1RP_TO_SPKMIXR */
1796
#define WM8994_IN1RP_TO_SPKMIXR_MASK 0x0010 /* IN1RP_TO_SPKMIXR */
1797
#define WM8994_IN1RP_TO_SPKMIXR_SHIFT 4 /* IN1RP_TO_SPKMIXR */
1798
#define WM8994_IN1RP_TO_SPKMIXR_WIDTH 1 /* IN1RP_TO_SPKMIXR */
1799
#define WM8994_MIXOUTL_TO_SPKMIXL 0x0008 /* MIXOUTL_TO_SPKMIXL */
1800
#define WM8994_MIXOUTL_TO_SPKMIXL_MASK 0x0008 /* MIXOUTL_TO_SPKMIXL */
1801
#define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT 3 /* MIXOUTL_TO_SPKMIXL */
1802
#define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH 1 /* MIXOUTL_TO_SPKMIXL */
1803
#define WM8994_MIXOUTR_TO_SPKMIXR 0x0004 /* MIXOUTR_TO_SPKMIXR */
1804
#define WM8994_MIXOUTR_TO_SPKMIXR_MASK 0x0004 /* MIXOUTR_TO_SPKMIXR */
1805
#define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT 2 /* MIXOUTR_TO_SPKMIXR */
1806
#define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH 1 /* MIXOUTR_TO_SPKMIXR */
1807
#define WM8994_DAC1L_TO_SPKMIXL 0x0002 /* DAC1L_TO_SPKMIXL */
1808
#define WM8994_DAC1L_TO_SPKMIXL_MASK 0x0002 /* DAC1L_TO_SPKMIXL */
1809
#define WM8994_DAC1L_TO_SPKMIXL_SHIFT 1 /* DAC1L_TO_SPKMIXL */
1810
#define WM8994_DAC1L_TO_SPKMIXL_WIDTH 1 /* DAC1L_TO_SPKMIXL */
1811
#define WM8994_DAC1R_TO_SPKMIXR 0x0001 /* DAC1R_TO_SPKMIXR */
1812
#define WM8994_DAC1R_TO_SPKMIXR_MASK 0x0001 /* DAC1R_TO_SPKMIXR */
1813
#define WM8994_DAC1R_TO_SPKMIXR_SHIFT 0 /* DAC1R_TO_SPKMIXR */
1814
#define WM8994_DAC1R_TO_SPKMIXR_WIDTH 1 /* DAC1R_TO_SPKMIXR */
1817
* R55 (0x37) - Additional Control
1819
#define WM8994_LINEOUT1_FB 0x0080 /* LINEOUT1_FB */
1820
#define WM8994_LINEOUT1_FB_MASK 0x0080 /* LINEOUT1_FB */
1821
#define WM8994_LINEOUT1_FB_SHIFT 7 /* LINEOUT1_FB */
1822
#define WM8994_LINEOUT1_FB_WIDTH 1 /* LINEOUT1_FB */
1823
#define WM8994_LINEOUT2_FB 0x0040 /* LINEOUT2_FB */
1824
#define WM8994_LINEOUT2_FB_MASK 0x0040 /* LINEOUT2_FB */
1825
#define WM8994_LINEOUT2_FB_SHIFT 6 /* LINEOUT2_FB */
1826
#define WM8994_LINEOUT2_FB_WIDTH 1 /* LINEOUT2_FB */
1827
#define WM8994_VROI 0x0001 /* VROI */
1828
#define WM8994_VROI_MASK 0x0001 /* VROI */
1829
#define WM8994_VROI_SHIFT 0 /* VROI */
1830
#define WM8994_VROI_WIDTH 1 /* VROI */
1833
* R56 (0x38) - AntiPOP (1)
1835
#define WM8994_LINEOUT_VMID_BUF_ENA 0x0080 /* LINEOUT_VMID_BUF_ENA */
1836
#define WM8994_LINEOUT_VMID_BUF_ENA_MASK 0x0080 /* LINEOUT_VMID_BUF_ENA */
1837
#define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT 7 /* LINEOUT_VMID_BUF_ENA */
1838
#define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH 1 /* LINEOUT_VMID_BUF_ENA */
1839
#define WM8994_HPOUT2_IN_ENA 0x0040 /* HPOUT2_IN_ENA */
1840
#define WM8994_HPOUT2_IN_ENA_MASK 0x0040 /* HPOUT2_IN_ENA */
1841
#define WM8994_HPOUT2_IN_ENA_SHIFT 6 /* HPOUT2_IN_ENA */
1842
#define WM8994_HPOUT2_IN_ENA_WIDTH 1 /* HPOUT2_IN_ENA */
1843
#define WM8994_LINEOUT1_DISCH 0x0020 /* LINEOUT1_DISCH */
1844
#define WM8994_LINEOUT1_DISCH_MASK 0x0020 /* LINEOUT1_DISCH */
1845
#define WM8994_LINEOUT1_DISCH_SHIFT 5 /* LINEOUT1_DISCH */
1846
#define WM8994_LINEOUT1_DISCH_WIDTH 1 /* LINEOUT1_DISCH */
1847
#define WM8994_LINEOUT2_DISCH 0x0010 /* LINEOUT2_DISCH */
1848
#define WM8994_LINEOUT2_DISCH_MASK 0x0010 /* LINEOUT2_DISCH */
1849
#define WM8994_LINEOUT2_DISCH_SHIFT 4 /* LINEOUT2_DISCH */
1850
#define WM8994_LINEOUT2_DISCH_WIDTH 1 /* LINEOUT2_DISCH */
1853
* R57 (0x39) - AntiPOP (2)
1855
#define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */
1856
#define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */
1857
#define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */
1858
#define WM8994_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1859
#define WM8994_MICB1_DISCH 0x0080 /* MICB1_DISCH */
1860
#define WM8994_MICB1_DISCH_MASK 0x0080 /* MICB1_DISCH */
1861
#define WM8994_MICB1_DISCH_SHIFT 7 /* MICB1_DISCH */
1862
#define WM8994_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1863
#define WM8994_VMID_RAMP_MASK 0x0060 /* VMID_RAMP - [6:5] */
1864
#define WM8994_VMID_RAMP_SHIFT 5 /* VMID_RAMP - [6:5] */
1865
#define WM8994_VMID_RAMP_WIDTH 2 /* VMID_RAMP - [6:5] */
1866
#define WM8994_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */
1867
#define WM8994_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */
1868
#define WM8994_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */
1869
#define WM8994_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
1870
#define WM8994_STARTUP_BIAS_ENA 0x0004 /* STARTUP_BIAS_ENA */
1871
#define WM8994_STARTUP_BIAS_ENA_MASK 0x0004 /* STARTUP_BIAS_ENA */
1872
#define WM8994_STARTUP_BIAS_ENA_SHIFT 2 /* STARTUP_BIAS_ENA */
1873
#define WM8994_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
1874
#define WM8994_BIAS_SRC 0x0002 /* BIAS_SRC */
1875
#define WM8994_BIAS_SRC_MASK 0x0002 /* BIAS_SRC */
1876
#define WM8994_BIAS_SRC_SHIFT 1 /* BIAS_SRC */
1877
#define WM8994_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
1878
#define WM8994_VMID_DISCH 0x0001 /* VMID_DISCH */
1879
#define WM8994_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */
1880
#define WM8994_VMID_DISCH_SHIFT 0 /* VMID_DISCH */
1881
#define WM8994_VMID_DISCH_WIDTH 1 /* VMID_DISCH */
1884
* R58 (0x3A) - MICBIAS
1886
#define WM8994_MICD_SCTHR_MASK 0x00C0 /* MICD_SCTHR - [7:6] */
1887
#define WM8994_MICD_SCTHR_SHIFT 6 /* MICD_SCTHR - [7:6] */
1888
#define WM8994_MICD_SCTHR_WIDTH 2 /* MICD_SCTHR - [7:6] */
1889
#define WM8994_MICD_THR_MASK 0x0038 /* MICD_THR - [5:3] */
1890
#define WM8994_MICD_THR_SHIFT 3 /* MICD_THR - [5:3] */
1891
#define WM8994_MICD_THR_WIDTH 3 /* MICD_THR - [5:3] */
1892
#define WM8994_MICD_ENA 0x0004 /* MICD_ENA */
1893
#define WM8994_MICD_ENA_MASK 0x0004 /* MICD_ENA */
1894
#define WM8994_MICD_ENA_SHIFT 2 /* MICD_ENA */
1895
#define WM8994_MICD_ENA_WIDTH 1 /* MICD_ENA */
1896
#define WM8994_MICB2_LVL 0x0002 /* MICB2_LVL */
1897
#define WM8994_MICB2_LVL_MASK 0x0002 /* MICB2_LVL */
1898
#define WM8994_MICB2_LVL_SHIFT 1 /* MICB2_LVL */
1899
#define WM8994_MICB2_LVL_WIDTH 1 /* MICB2_LVL */
1900
#define WM8994_MICB1_LVL 0x0001 /* MICB1_LVL */
1901
#define WM8994_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */
1902
#define WM8994_MICB1_LVL_SHIFT 0 /* MICB1_LVL */
1903
#define WM8994_MICB1_LVL_WIDTH 1 /* MICB1_LVL */
1906
* R59 (0x3B) - LDO 1
1908
#define WM8994_LDO1_VSEL_MASK 0x000E /* LDO1_VSEL - [3:1] */
1909
#define WM8994_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [3:1] */
1910
#define WM8994_LDO1_VSEL_WIDTH 3 /* LDO1_VSEL - [3:1] */
1911
#define WM8994_LDO1_DISCH 0x0001 /* LDO1_DISCH */
1912
#define WM8994_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
1913
#define WM8994_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
1914
#define WM8994_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1917
* R60 (0x3C) - LDO 2
1919
#define WM8994_LDO2_VSEL_MASK 0x0006 /* LDO2_VSEL - [2:1] */
1920
#define WM8994_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [2:1] */
1921
#define WM8994_LDO2_VSEL_WIDTH 2 /* LDO2_VSEL - [2:1] */
1922
#define WM8994_LDO2_DISCH 0x0001 /* LDO2_DISCH */
1923
#define WM8994_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
1924
#define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
1925
#define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1928
* R61 (0x3D) - MICBIAS1
1930
#define WM8958_MICB1_RATE 0x0020 /* MICB1_RATE */
1931
#define WM8958_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
1932
#define WM8958_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
1933
#define WM8958_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
1934
#define WM8958_MICB1_MODE 0x0010 /* MICB1_MODE */
1935
#define WM8958_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */
1936
#define WM8958_MICB1_MODE_SHIFT 4 /* MICB1_MODE */
1937
#define WM8958_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
1938
#define WM8958_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */
1939
#define WM8958_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */
1940
#define WM8958_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */
1941
#define WM8958_MICB1_DISCH 0x0001 /* MICB1_DISCH */
1942
#define WM8958_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
1943
#define WM8958_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */
1944
#define WM8958_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1947
* R62 (0x3E) - MICBIAS2
1949
#define WM8958_MICB2_RATE 0x0020 /* MICB2_RATE */
1950
#define WM8958_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
1951
#define WM8958_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
1952
#define WM8958_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
1953
#define WM8958_MICB2_MODE 0x0010 /* MICB2_MODE */
1954
#define WM8958_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */
1955
#define WM8958_MICB2_MODE_SHIFT 4 /* MICB2_MODE */
1956
#define WM8958_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
1957
#define WM8958_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */
1958
#define WM8958_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */
1959
#define WM8958_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */
1960
#define WM8958_MICB2_DISCH 0x0001 /* MICB2_DISCH */
1961
#define WM8958_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
1962
#define WM8958_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */
1963
#define WM8958_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1966
* R210 (0xD2) - Mic Detect 3
1968
#define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
1969
#define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
1970
#define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
1971
#define WM8958_MICD_VALID 0x0002 /* MICD_VALID */
1972
#define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */
1973
#define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */
1974
#define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */
1975
#define WM8958_MICD_STS 0x0001 /* MICD_STS */
1976
#define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */
1977
#define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */
1978
#define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */
1981
* R76 (0x4C) - Charge Pump (1)
1983
#define WM8994_CP_ENA 0x8000 /* CP_ENA */
1984
#define WM8994_CP_ENA_MASK 0x8000 /* CP_ENA */
1985
#define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */
1986
#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */
1989
* R77 (0x4D) - Charge Pump (2)
1991
#define WM8958_CP_DISCH 0x8000 /* CP_DISCH */
1992
#define WM8958_CP_DISCH_MASK 0x8000 /* CP_DISCH */
1993
#define WM8958_CP_DISCH_SHIFT 15 /* CP_DISCH */
1994
#define WM8958_CP_DISCH_WIDTH 1 /* CP_DISCH */
1997
* R81 (0x51) - Class W (1)
1999
#define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
2000
#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */
2001
#define WM8994_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */
2002
#define WM8994_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
2003
#define WM8994_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
2004
#define WM8994_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */
2005
#define WM8994_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
2008
* R84 (0x54) - DC Servo (1)
2010
#define WM8994_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
2011
#define WM8994_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
2012
#define WM8994_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
2013
#define WM8994_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
2014
#define WM8994_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
2015
#define WM8994_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
2016
#define WM8994_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
2017
#define WM8994_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
2018
#define WM8994_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
2019
#define WM8994_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
2020
#define WM8994_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
2021
#define WM8994_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
2022
#define WM8994_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
2023
#define WM8994_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
2024
#define WM8994_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
2025
#define WM8994_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
2026
#define WM8994_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
2027
#define WM8994_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
2028
#define WM8994_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
2029
#define WM8994_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
2030
#define WM8994_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
2031
#define WM8994_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
2032
#define WM8994_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
2033
#define WM8994_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
2034
#define WM8994_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */
2035
#define WM8994_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */
2036
#define WM8994_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */
2037
#define WM8994_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
2038
#define WM8994_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */
2039
#define WM8994_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */
2040
#define WM8994_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */
2041
#define WM8994_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
2042
#define WM8994_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
2043
#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
2044
#define WM8994_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
2045
#define WM8994_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
2046
#define WM8994_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
2047
#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
2048
#define WM8994_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
2049
#define WM8994_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
2052
* R85 (0x55) - DC Servo (2)
2054
#define WM8994_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */
2055
#define WM8994_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */
2056
#define WM8994_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */
2057
#define WM8994_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
2058
#define WM8994_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
2059
#define WM8994_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
2062
* R87 (0x57) - DC Servo (4)
2064
#define WM8994_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
2065
#define WM8994_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
2066
#define WM8994_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
2067
#define WM8994_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
2068
#define WM8994_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
2069
#define WM8994_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
2072
* R88 (0x58) - DC Servo Readback
2074
#define WM8994_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */
2075
#define WM8994_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */
2076
#define WM8994_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */
2077
#define WM8994_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */
2078
#define WM8994_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */
2079
#define WM8994_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */
2080
#define WM8994_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */
2081
#define WM8994_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */
2082
#define WM8994_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */
2085
* R96 (0x60) - Analogue HP (1)
2087
#define WM1811_HPOUT1_ATTN 0x0100 /* HPOUT1_ATTN */
2088
#define WM1811_HPOUT1_ATTN_MASK 0x0100 /* HPOUT1_ATTN */
2089
#define WM1811_HPOUT1_ATTN_SHIFT 8 /* HPOUT1_ATTN */
2090
#define WM1811_HPOUT1_ATTN_WIDTH 1 /* HPOUT1_ATTN */
2091
#define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
2092
#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
2093
#define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
2094
#define WM8994_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
2095
#define WM8994_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
2096
#define WM8994_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
2097
#define WM8994_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
2098
#define WM8994_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
2099
#define WM8994_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
2100
#define WM8994_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
2101
#define WM8994_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
2102
#define WM8994_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
2103
#define WM8994_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
2104
#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
2105
#define WM8994_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
2106
#define WM8994_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
2107
#define WM8994_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
2108
#define WM8994_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
2109
#define WM8994_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
2110
#define WM8994_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
2111
#define WM8994_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
2112
#define WM8994_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
2113
#define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
2114
#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
2117
* R208 (0xD0) - Mic Detect 1
2119
#define WM8958_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
2120
#define WM8958_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
2121
#define WM8958_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
2122
#define WM8958_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
2123
#define WM8958_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
2124
#define WM8958_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
2125
#define WM8958_MICD_DBTIME 0x0002 /* MICD_DBTIME */
2126
#define WM8958_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
2127
#define WM8958_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
2128
#define WM8958_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
2129
#define WM8958_MICD_ENA 0x0001 /* MICD_ENA */
2130
#define WM8958_MICD_ENA_MASK 0x0001 /* MICD_ENA */
2131
#define WM8958_MICD_ENA_SHIFT 0 /* MICD_ENA */
2132
#define WM8958_MICD_ENA_WIDTH 1 /* MICD_ENA */
2135
* R209 (0xD1) - Mic Detect 2
2137
#define WM8958_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
2138
#define WM8958_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
2139
#define WM8958_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
2142
* R210 (0xD2) - Mic Detect 3
2144
#define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
2145
#define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
2146
#define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
2147
#define WM8958_MICD_VALID 0x0002 /* MICD_VALID */
2148
#define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */
2149
#define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */
2150
#define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */
2151
#define WM8958_MICD_STS 0x0001 /* MICD_STS */
2152
#define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */
2153
#define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */
2154
#define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */
2157
* R256 (0x100) - Chip Revision
2159
#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
2160
#define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
2161
#define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
2164
* R257 (0x101) - Control Interface
2166
#define WM8994_SPI_CONTRD 0x0040 /* SPI_CONTRD */
2167
#define WM8994_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */
2168
#define WM8994_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */
2169
#define WM8994_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
2170
#define WM8994_SPI_4WIRE 0x0020 /* SPI_4WIRE */
2171
#define WM8994_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */
2172
#define WM8994_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */
2173
#define WM8994_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
2174
#define WM8994_SPI_CFG 0x0010 /* SPI_CFG */
2175
#define WM8994_SPI_CFG_MASK 0x0010 /* SPI_CFG */
2176
#define WM8994_SPI_CFG_SHIFT 4 /* SPI_CFG */
2177
#define WM8994_SPI_CFG_WIDTH 1 /* SPI_CFG */
2178
#define WM8994_AUTO_INC 0x0004 /* AUTO_INC */
2179
#define WM8994_AUTO_INC_MASK 0x0004 /* AUTO_INC */
2180
#define WM8994_AUTO_INC_SHIFT 2 /* AUTO_INC */
2181
#define WM8994_AUTO_INC_WIDTH 1 /* AUTO_INC */
2184
* R272 (0x110) - Write Sequencer Ctrl (1)
2186
#define WM8994_WSEQ_ENA 0x8000 /* WSEQ_ENA */
2187
#define WM8994_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
2188
#define WM8994_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
2189
#define WM8994_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
2190
#define WM8994_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
2191
#define WM8994_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
2192
#define WM8994_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
2193
#define WM8994_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
2194
#define WM8994_WSEQ_START 0x0100 /* WSEQ_START */
2195
#define WM8994_WSEQ_START_MASK 0x0100 /* WSEQ_START */
2196
#define WM8994_WSEQ_START_SHIFT 8 /* WSEQ_START */
2197
#define WM8994_WSEQ_START_WIDTH 1 /* WSEQ_START */
2198
#define WM8994_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
2199
#define WM8994_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
2200
#define WM8994_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
2203
* R273 (0x111) - Write Sequencer Ctrl (2)
2205
#define WM8994_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
2206
#define WM8994_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
2207
#define WM8994_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
2208
#define WM8994_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
2209
#define WM8994_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
2210
#define WM8994_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
2211
#define WM8994_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
2214
* R512 (0x200) - AIF1 Clocking (1)
2216
#define WM8994_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */
2217
#define WM8994_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */
2218
#define WM8994_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */
2219
#define WM8994_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */
2220
#define WM8994_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */
2221
#define WM8994_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */
2222
#define WM8994_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */
2223
#define WM8994_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */
2224
#define WM8994_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */
2225
#define WM8994_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */
2226
#define WM8994_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */
2227
#define WM8994_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */
2228
#define WM8994_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */
2229
#define WM8994_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */
2230
#define WM8994_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */
2233
* R513 (0x201) - AIF1 Clocking (2)
2235
#define WM8994_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */
2236
#define WM8994_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */
2237
#define WM8994_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */
2238
#define WM8994_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */
2239
#define WM8994_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */
2240
#define WM8994_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */
2243
* R516 (0x204) - AIF2 Clocking (1)
2245
#define WM8994_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */
2246
#define WM8994_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */
2247
#define WM8994_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */
2248
#define WM8994_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */
2249
#define WM8994_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */
2250
#define WM8994_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */
2251
#define WM8994_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */
2252
#define WM8994_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */
2253
#define WM8994_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */
2254
#define WM8994_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */
2255
#define WM8994_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */
2256
#define WM8994_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */
2257
#define WM8994_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */
2258
#define WM8994_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */
2259
#define WM8994_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */
2262
* R517 (0x205) - AIF2 Clocking (2)
2264
#define WM8994_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */
2265
#define WM8994_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */
2266
#define WM8994_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */
2267
#define WM8994_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */
2268
#define WM8994_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */
2269
#define WM8994_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */
2272
* R520 (0x208) - Clocking (1)
2274
#define WM8958_DSP2CLK_ENA 0x4000 /* DSP2CLK_ENA */
2275
#define WM8958_DSP2CLK_ENA_MASK 0x4000 /* DSP2CLK_ENA */
2276
#define WM8958_DSP2CLK_ENA_SHIFT 14 /* DSP2CLK_ENA */
2277
#define WM8958_DSP2CLK_ENA_WIDTH 1 /* DSP2CLK_ENA */
2278
#define WM8958_DSP2CLK_SRC 0x1000 /* DSP2CLK_SRC */
2279
#define WM8958_DSP2CLK_SRC_MASK 0x1000 /* DSP2CLK_SRC */
2280
#define WM8958_DSP2CLK_SRC_SHIFT 12 /* DSP2CLK_SRC */
2281
#define WM8958_DSP2CLK_SRC_WIDTH 1 /* DSP2CLK_SRC */
2282
#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */
2283
#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
2284
#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
2285
#define WM8994_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
2286
#define WM8994_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */
2287
#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */
2288
#define WM8994_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */
2289
#define WM8994_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */
2290
#define WM8994_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */
2291
#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */
2292
#define WM8994_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */
2293
#define WM8994_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */
2294
#define WM8994_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */
2295
#define WM8994_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */
2296
#define WM8994_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
2297
#define WM8994_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
2298
#define WM8994_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */
2299
#define WM8994_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */
2300
#define WM8994_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */
2301
#define WM8994_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
2304
* R521 (0x209) - Clocking (2)
2306
#define WM8994_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
2307
#define WM8994_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
2308
#define WM8994_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
2309
#define WM8994_DBCLK_DIV_MASK 0x0070 /* DBCLK_DIV - [6:4] */
2310
#define WM8994_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [6:4] */
2311
#define WM8994_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [6:4] */
2312
#define WM8994_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
2313
#define WM8994_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
2314
#define WM8994_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
2317
* R528 (0x210) - AIF1 Rate
2319
#define WM8994_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */
2320
#define WM8994_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */
2321
#define WM8994_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */
2322
#define WM8994_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */
2323
#define WM8994_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */
2324
#define WM8994_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */
2327
* R529 (0x211) - AIF2 Rate
2329
#define WM8994_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */
2330
#define WM8994_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */
2331
#define WM8994_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */
2332
#define WM8994_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */
2333
#define WM8994_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */
2334
#define WM8994_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */
2337
* R530 (0x212) - Rate Status
2339
#define WM8994_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */
2340
#define WM8994_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */
2341
#define WM8994_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */
2344
* R544 (0x220) - FLL1 Control (1)
2346
#define WM8994_FLL1_FRAC 0x0004 /* FLL1_FRAC */
2347
#define WM8994_FLL1_FRAC_MASK 0x0004 /* FLL1_FRAC */
2348
#define WM8994_FLL1_FRAC_SHIFT 2 /* FLL1_FRAC */
2349
#define WM8994_FLL1_FRAC_WIDTH 1 /* FLL1_FRAC */
2350
#define WM8994_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */
2351
#define WM8994_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */
2352
#define WM8994_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */
2353
#define WM8994_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */
2354
#define WM8994_FLL1_ENA 0x0001 /* FLL1_ENA */
2355
#define WM8994_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
2356
#define WM8994_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
2357
#define WM8994_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
2360
* R545 (0x221) - FLL1 Control (2)
2362
#define WM8994_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
2363
#define WM8994_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
2364
#define WM8994_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
2365
#define WM8994_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */
2366
#define WM8994_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */
2367
#define WM8994_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */
2368
#define WM8994_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
2369
#define WM8994_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
2370
#define WM8994_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
2373
* R546 (0x222) - FLL1 Control (3)
2375
#define WM8994_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */
2376
#define WM8994_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */
2377
#define WM8994_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */
2380
* R547 (0x223) - FLL1 Control (4)
2382
#define WM8994_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */
2383
#define WM8994_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */
2384
#define WM8994_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */
2385
#define WM8994_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */
2386
#define WM8994_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */
2387
#define WM8994_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */
2390
* R548 (0x224) - FLL1 Control (5)
2392
#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
2393
#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
2394
#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
2395
#define WM8994_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */
2396
#define WM8994_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */
2397
#define WM8994_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */
2398
#define WM8994_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */
2399
#define WM8994_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */
2400
#define WM8994_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */
2401
#define WM8994_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */
2402
#define WM8994_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */
2403
#define WM8994_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */
2404
#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
2407
* R576 (0x240) - FLL2 Control (1)
2409
#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */
2410
#define WM8994_FLL2_FRAC_MASK 0x0004 /* FLL2_FRAC */
2411
#define WM8994_FLL2_FRAC_SHIFT 2 /* FLL2_FRAC */
2412
#define WM8994_FLL2_FRAC_WIDTH 1 /* FLL2_FRAC */
2413
#define WM8994_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */
2414
#define WM8994_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */
2415
#define WM8994_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */
2416
#define WM8994_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */
2417
#define WM8994_FLL2_ENA 0x0001 /* FLL2_ENA */
2418
#define WM8994_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
2419
#define WM8994_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
2420
#define WM8994_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
2423
* R577 (0x241) - FLL2 Control (2)
2425
#define WM8994_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
2426
#define WM8994_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
2427
#define WM8994_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
2428
#define WM8994_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */
2429
#define WM8994_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */
2430
#define WM8994_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */
2431
#define WM8994_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
2432
#define WM8994_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
2433
#define WM8994_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
2436
* R578 (0x242) - FLL2 Control (3)
2438
#define WM8994_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */
2439
#define WM8994_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */
2440
#define WM8994_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */
2443
* R579 (0x243) - FLL2 Control (4)
2445
#define WM8994_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */
2446
#define WM8994_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */
2447
#define WM8994_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */
2448
#define WM8994_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */
2449
#define WM8994_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */
2450
#define WM8994_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */
2453
* R580 (0x244) - FLL2 Control (5)
2455
#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
2456
#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
2457
#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
2458
#define WM8994_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */
2459
#define WM8994_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */
2460
#define WM8994_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */
2461
#define WM8994_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */
2462
#define WM8994_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */
2463
#define WM8994_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */
2464
#define WM8994_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */
2465
#define WM8994_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */
2466
#define WM8994_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */
2467
#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
2470
* R768 (0x300) - AIF1 Control (1)
2472
#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
2473
#define WM8994_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */
2474
#define WM8994_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */
2475
#define WM8994_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */
2476
#define WM8994_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */
2477
#define WM8994_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */
2478
#define WM8994_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */
2479
#define WM8994_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */
2480
#define WM8994_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */
2481
#define WM8994_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */
2482
#define WM8994_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */
2483
#define WM8994_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */
2484
#define WM8994_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */
2485
#define WM8994_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */
2486
#define WM8994_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */
2487
#define WM8994_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
2488
#define WM8994_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */
2489
#define WM8994_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */
2490
#define WM8994_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */
2491
#define WM8994_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
2492
#define WM8994_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */
2493
#define WM8994_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */
2494
#define WM8994_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */
2495
#define WM8994_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */
2496
#define WM8994_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */
2497
#define WM8994_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */
2500
* R769 (0x301) - AIF1 Control (2)
2502
#define WM8994_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */
2503
#define WM8994_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */
2504
#define WM8994_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */
2505
#define WM8994_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */
2506
#define WM8994_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */
2507
#define WM8994_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */
2508
#define WM8994_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */
2509
#define WM8994_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */
2510
#define WM8994_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */
2511
#define WM8994_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */
2512
#define WM8994_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */
2513
#define WM8994_AIF1_MONO 0x0100 /* AIF1_MONO */
2514
#define WM8994_AIF1_MONO_MASK 0x0100 /* AIF1_MONO */
2515
#define WM8994_AIF1_MONO_SHIFT 8 /* AIF1_MONO */
2516
#define WM8994_AIF1_MONO_WIDTH 1 /* AIF1_MONO */
2517
#define WM8994_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */
2518
#define WM8994_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */
2519
#define WM8994_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */
2520
#define WM8994_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */
2521
#define WM8994_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */
2522
#define WM8994_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */
2523
#define WM8994_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */
2524
#define WM8994_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */
2525
#define WM8994_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */
2526
#define WM8994_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */
2527
#define WM8994_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */
2528
#define WM8994_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */
2529
#define WM8994_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */
2530
#define WM8994_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */
2531
#define WM8994_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */
2532
#define WM8994_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */
2533
#define WM8994_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */
2534
#define WM8994_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */
2535
#define WM8994_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */
2536
#define WM8994_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */
2539
* R770 (0x302) - AIF1 Master/Slave
2541
#define WM8994_AIF1_TRI 0x8000 /* AIF1_TRI */
2542
#define WM8994_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */
2543
#define WM8994_AIF1_TRI_SHIFT 15 /* AIF1_TRI */
2544
#define WM8994_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
2545
#define WM8994_AIF1_MSTR 0x4000 /* AIF1_MSTR */
2546
#define WM8994_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */
2547
#define WM8994_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */
2548
#define WM8994_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */
2549
#define WM8994_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */
2550
#define WM8994_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */
2551
#define WM8994_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */
2552
#define WM8994_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */
2553
#define WM8994_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */
2554
#define WM8994_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */
2555
#define WM8994_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */
2556
#define WM8994_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */
2559
* R771 (0x303) - AIF1 BCLK
2561
#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 /* AIF1_BCLK_DIV - [8:4] */
2562
#define WM8994_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [8:4] */
2563
#define WM8994_AIF1_BCLK_DIV_WIDTH 5 /* AIF1_BCLK_DIV - [8:4] */
2566
* R772 (0x304) - AIF1ADC LRCLK
2568
#define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */
2569
#define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */
2570
#define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */
2571
#define WM8994_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */
2572
#define WM8994_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */
2573
#define WM8994_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */
2574
#define WM8994_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */
2577
* R773 (0x305) - AIF1DAC LRCLK
2579
#define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */
2580
#define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */
2581
#define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */
2582
#define WM8994_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */
2583
#define WM8994_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */
2584
#define WM8994_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */
2585
#define WM8994_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */
2588
* R774 (0x306) - AIF1DAC Data
2590
#define WM8994_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */
2591
#define WM8994_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */
2592
#define WM8994_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */
2593
#define WM8994_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */
2594
#define WM8994_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */
2595
#define WM8994_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */
2596
#define WM8994_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */
2597
#define WM8994_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */
2600
* R775 (0x307) - AIF1ADC Data
2602
#define WM8994_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */
2603
#define WM8994_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */
2604
#define WM8994_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */
2605
#define WM8994_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */
2606
#define WM8994_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */
2607
#define WM8994_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */
2608
#define WM8994_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */
2609
#define WM8994_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */
2612
* R784 (0x310) - AIF2 Control (1)
2614
#define WM8994_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */
2615
#define WM8994_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */
2616
#define WM8994_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */
2617
#define WM8994_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */
2618
#define WM8994_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */
2619
#define WM8994_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */
2620
#define WM8994_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */
2621
#define WM8994_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */
2622
#define WM8994_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */
2623
#define WM8994_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */
2624
#define WM8994_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */
2625
#define WM8994_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */
2626
#define WM8994_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */
2627
#define WM8994_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */
2628
#define WM8994_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */
2629
#define WM8994_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */
2630
#define WM8994_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */
2631
#define WM8994_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */
2632
#define WM8994_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */
2633
#define WM8994_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
2634
#define WM8994_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */
2635
#define WM8994_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */
2636
#define WM8994_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */
2637
#define WM8994_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */
2638
#define WM8994_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */
2639
#define WM8994_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */
2640
#define WM8994_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */
2641
#define WM8994_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */
2642
#define WM8994_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */
2643
#define WM8994_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */
2646
* R785 (0x311) - AIF2 Control (2)
2648
#define WM8994_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */
2649
#define WM8994_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */
2650
#define WM8994_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */
2651
#define WM8994_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */
2652
#define WM8994_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */
2653
#define WM8994_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */
2654
#define WM8994_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */
2655
#define WM8994_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */
2656
#define WM8994_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */
2657
#define WM8994_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */
2658
#define WM8994_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */
2659
#define WM8994_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */
2660
#define WM8994_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */
2661
#define WM8994_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */
2662
#define WM8994_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */
2663
#define WM8994_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */
2664
#define WM8994_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */
2665
#define WM8994_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */
2666
#define WM8994_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */
2667
#define WM8994_AIF2_MONO 0x0100 /* AIF2_MONO */
2668
#define WM8994_AIF2_MONO_MASK 0x0100 /* AIF2_MONO */
2669
#define WM8994_AIF2_MONO_SHIFT 8 /* AIF2_MONO */
2670
#define WM8994_AIF2_MONO_WIDTH 1 /* AIF2_MONO */
2671
#define WM8994_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */
2672
#define WM8994_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */
2673
#define WM8994_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */
2674
#define WM8994_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */
2675
#define WM8994_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */
2676
#define WM8994_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */
2677
#define WM8994_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */
2678
#define WM8994_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */
2679
#define WM8994_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */
2680
#define WM8994_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */
2681
#define WM8994_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */
2682
#define WM8994_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */
2683
#define WM8994_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */
2684
#define WM8994_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */
2685
#define WM8994_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */
2686
#define WM8994_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */
2687
#define WM8994_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */
2688
#define WM8994_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */
2689
#define WM8994_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */
2690
#define WM8994_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */
2693
* R786 (0x312) - AIF2 Master/Slave
2695
#define WM8994_AIF2_TRI 0x8000 /* AIF2_TRI */
2696
#define WM8994_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */
2697
#define WM8994_AIF2_TRI_SHIFT 15 /* AIF2_TRI */
2698
#define WM8994_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
2699
#define WM8994_AIF2_MSTR 0x4000 /* AIF2_MSTR */
2700
#define WM8994_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */
2701
#define WM8994_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */
2702
#define WM8994_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */
2703
#define WM8994_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */
2704
#define WM8994_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */
2705
#define WM8994_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */
2706
#define WM8994_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */
2707
#define WM8994_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */
2708
#define WM8994_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */
2709
#define WM8994_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */
2710
#define WM8994_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */
2713
* R787 (0x313) - AIF2 BCLK
2715
#define WM8994_AIF2_BCLK_DIV_MASK 0x01F0 /* AIF2_BCLK_DIV - [8:4] */
2716
#define WM8994_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [8:4] */
2717
#define WM8994_AIF2_BCLK_DIV_WIDTH 5 /* AIF2_BCLK_DIV - [8:4] */
2720
* R788 (0x314) - AIF2ADC LRCLK
2722
#define WM8994_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */
2723
#define WM8994_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */
2724
#define WM8994_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */
2725
#define WM8994_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */
2726
#define WM8994_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */
2727
#define WM8994_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */
2728
#define WM8994_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */
2731
* R789 (0x315) - AIF2DAC LRCLK
2733
#define WM8994_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */
2734
#define WM8994_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */
2735
#define WM8994_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */
2736
#define WM8994_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */
2737
#define WM8994_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */
2738
#define WM8994_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */
2739
#define WM8994_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */
2742
* R790 (0x316) - AIF2DAC Data
2744
#define WM8994_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */
2745
#define WM8994_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */
2746
#define WM8994_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */
2747
#define WM8994_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */
2748
#define WM8994_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */
2749
#define WM8994_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */
2750
#define WM8994_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */
2751
#define WM8994_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */
2754
* R791 (0x317) - AIF2ADC Data
2756
#define WM8994_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */
2757
#define WM8994_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */
2758
#define WM8994_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */
2759
#define WM8994_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */
2760
#define WM8994_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */
2761
#define WM8994_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */
2762
#define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */
2763
#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
2766
* R800 (0x320) - AIF3 Control (1)
2768
#define WM8958_AIF3_LRCLK_INV 0x0080 /* AIF3_LRCLK_INV */
2769
#define WM8958_AIF3_LRCLK_INV_MASK 0x0080 /* AIF3_LRCLK_INV */
2770
#define WM8958_AIF3_LRCLK_INV_SHIFT 7 /* AIF3_LRCLK_INV */
2771
#define WM8958_AIF3_LRCLK_INV_WIDTH 1 /* AIF3_LRCLK_INV */
2772
#define WM8958_AIF3_WL_MASK 0x0060 /* AIF3_WL - [6:5] */
2773
#define WM8958_AIF3_WL_SHIFT 5 /* AIF3_WL - [6:5] */
2774
#define WM8958_AIF3_WL_WIDTH 2 /* AIF3_WL - [6:5] */
2775
#define WM8958_AIF3_FMT_MASK 0x0018 /* AIF3_FMT - [4:3] */
2776
#define WM8958_AIF3_FMT_SHIFT 3 /* AIF3_FMT - [4:3] */
2777
#define WM8958_AIF3_FMT_WIDTH 2 /* AIF3_FMT - [4:3] */
2780
* R801 (0x321) - AIF3 Control (2)
2782
#define WM8958_AIF3DAC_BOOST_MASK 0x0C00 /* AIF3DAC_BOOST - [11:10] */
2783
#define WM8958_AIF3DAC_BOOST_SHIFT 10 /* AIF3DAC_BOOST - [11:10] */
2784
#define WM8958_AIF3DAC_BOOST_WIDTH 2 /* AIF3DAC_BOOST - [11:10] */
2785
#define WM8958_AIF3DAC_COMP 0x0010 /* AIF3DAC_COMP */
2786
#define WM8958_AIF3DAC_COMP_MASK 0x0010 /* AIF3DAC_COMP */
2787
#define WM8958_AIF3DAC_COMP_SHIFT 4 /* AIF3DAC_COMP */
2788
#define WM8958_AIF3DAC_COMP_WIDTH 1 /* AIF3DAC_COMP */
2789
#define WM8958_AIF3DAC_COMPMODE 0x0008 /* AIF3DAC_COMPMODE */
2790
#define WM8958_AIF3DAC_COMPMODE_MASK 0x0008 /* AIF3DAC_COMPMODE */
2791
#define WM8958_AIF3DAC_COMPMODE_SHIFT 3 /* AIF3DAC_COMPMODE */
2792
#define WM8958_AIF3DAC_COMPMODE_WIDTH 1 /* AIF3DAC_COMPMODE */
2793
#define WM8958_AIF3ADC_COMP 0x0004 /* AIF3ADC_COMP */
2794
#define WM8958_AIF3ADC_COMP_MASK 0x0004 /* AIF3ADC_COMP */
2795
#define WM8958_AIF3ADC_COMP_SHIFT 2 /* AIF3ADC_COMP */
2796
#define WM8958_AIF3ADC_COMP_WIDTH 1 /* AIF3ADC_COMP */
2797
#define WM8958_AIF3ADC_COMPMODE 0x0002 /* AIF3ADC_COMPMODE */
2798
#define WM8958_AIF3ADC_COMPMODE_MASK 0x0002 /* AIF3ADC_COMPMODE */
2799
#define WM8958_AIF3ADC_COMPMODE_SHIFT 1 /* AIF3ADC_COMPMODE */
2800
#define WM8958_AIF3ADC_COMPMODE_WIDTH 1 /* AIF3ADC_COMPMODE */
2801
#define WM8958_AIF3_LOOPBACK 0x0001 /* AIF3_LOOPBACK */
2802
#define WM8958_AIF3_LOOPBACK_MASK 0x0001 /* AIF3_LOOPBACK */
2803
#define WM8958_AIF3_LOOPBACK_SHIFT 0 /* AIF3_LOOPBACK */
2804
#define WM8958_AIF3_LOOPBACK_WIDTH 1 /* AIF3_LOOPBACK */
2807
* R802 (0x322) - AIF3DAC Data
2809
#define WM8958_AIF3DAC_DAT_INV 0x0001 /* AIF3DAC_DAT_INV */
2810
#define WM8958_AIF3DAC_DAT_INV_MASK 0x0001 /* AIF3DAC_DAT_INV */
2811
#define WM8958_AIF3DAC_DAT_INV_SHIFT 0 /* AIF3DAC_DAT_INV */
2812
#define WM8958_AIF3DAC_DAT_INV_WIDTH 1 /* AIF3DAC_DAT_INV */
2815
* R803 (0x323) - AIF3ADC Data
2817
#define WM8958_AIF3ADC_DAT_INV 0x0001 /* AIF3ADC_DAT_INV */
2818
#define WM8958_AIF3ADC_DAT_INV_MASK 0x0001 /* AIF3ADC_DAT_INV */
2819
#define WM8958_AIF3ADC_DAT_INV_SHIFT 0 /* AIF3ADC_DAT_INV */
2820
#define WM8958_AIF3ADC_DAT_INV_WIDTH 1 /* AIF3ADC_DAT_INV */
2823
* R1024 (0x400) - AIF1 ADC1 Left Volume
2825
#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2826
#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2827
#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2828
#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2829
#define WM8994_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */
2830
#define WM8994_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */
2831
#define WM8994_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */
2834
* R1025 (0x401) - AIF1 ADC1 Right Volume
2836
#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2837
#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2838
#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2839
#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2840
#define WM8994_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */
2841
#define WM8994_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */
2842
#define WM8994_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */
2845
* R1026 (0x402) - AIF1 DAC1 Left Volume
2847
#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2848
#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2849
#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2850
#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2851
#define WM8994_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */
2852
#define WM8994_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */
2853
#define WM8994_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */
2856
* R1027 (0x403) - AIF1 DAC1 Right Volume
2858
#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2859
#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2860
#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2861
#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2862
#define WM8994_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */
2863
#define WM8994_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */
2864
#define WM8994_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */
2867
* R1028 (0x404) - AIF1 ADC2 Left Volume
2869
#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2870
#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2871
#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2872
#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2873
#define WM8994_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */
2874
#define WM8994_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */
2875
#define WM8994_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */
2878
* R1029 (0x405) - AIF1 ADC2 Right Volume
2880
#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2881
#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2882
#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2883
#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2884
#define WM8994_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */
2885
#define WM8994_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */
2886
#define WM8994_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */
2889
* R1030 (0x406) - AIF1 DAC2 Left Volume
2891
#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2892
#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2893
#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2894
#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2895
#define WM8994_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */
2896
#define WM8994_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */
2897
#define WM8994_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */
2900
* R1031 (0x407) - AIF1 DAC2 Right Volume
2902
#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2903
#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2904
#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2905
#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2906
#define WM8994_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */
2907
#define WM8994_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */
2908
#define WM8994_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */
2911
* R1040 (0x410) - AIF1 ADC1 Filters
2913
#define WM8994_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */
2914
#define WM8994_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */
2915
#define WM8994_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */
2916
#define WM8994_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */
2917
#define WM8994_AIF1ADC1_HPF_CUT_MASK 0x6000 /* AIF1ADC1_HPF_CUT - [14:13] */
2918
#define WM8994_AIF1ADC1_HPF_CUT_SHIFT 13 /* AIF1ADC1_HPF_CUT - [14:13] */
2919
#define WM8994_AIF1ADC1_HPF_CUT_WIDTH 2 /* AIF1ADC1_HPF_CUT - [14:13] */
2920
#define WM8994_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */
2921
#define WM8994_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */
2922
#define WM8994_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */
2923
#define WM8994_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */
2924
#define WM8994_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */
2925
#define WM8994_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */
2926
#define WM8994_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */
2927
#define WM8994_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */
2930
* R1041 (0x411) - AIF1 ADC2 Filters
2932
#define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */
2933
#define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */
2934
#define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */
2935
#define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */
2936
#define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */
2937
#define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */
2938
#define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
2939
#define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */
2940
#define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */
2941
#define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */
2942
#define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
2945
* R1056 (0x420) - AIF1 DAC1 Filters (1)
2947
#define WM8994_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */
2948
#define WM8994_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */
2949
#define WM8994_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */
2950
#define WM8994_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */
2951
#define WM8994_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */
2952
#define WM8994_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */
2953
#define WM8994_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */
2954
#define WM8994_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */
2955
#define WM8994_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */
2956
#define WM8994_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */
2957
#define WM8994_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */
2958
#define WM8994_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */
2959
#define WM8994_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2960
#define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2961
#define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */
2962
#define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */
2963
#define WM8994_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */
2964
#define WM8994_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */
2965
#define WM8994_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */
2968
* R1057 (0x421) - AIF1 DAC1 Filters (2)
2970
#define WM8994_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */
2971
#define WM8994_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */
2972
#define WM8994_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */
2973
#define WM8994_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */
2974
#define WM8994_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */
2975
#define WM8994_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */
2976
#define WM8994_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */
2979
* R1058 (0x422) - AIF1 DAC2 Filters (1)
2981
#define WM8994_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */
2982
#define WM8994_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */
2983
#define WM8994_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */
2984
#define WM8994_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */
2985
#define WM8994_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */
2986
#define WM8994_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */
2987
#define WM8994_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */
2988
#define WM8994_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */
2989
#define WM8994_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */
2990
#define WM8994_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */
2991
#define WM8994_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */
2992
#define WM8994_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */
2993
#define WM8994_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2994
#define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2995
#define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */
2996
#define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */
2997
#define WM8994_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */
2998
#define WM8994_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */
2999
#define WM8994_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */
3002
* R1059 (0x423) - AIF1 DAC2 Filters (2)
3004
#define WM8994_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */
3005
#define WM8994_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */
3006
#define WM8994_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */
3007
#define WM8994_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */
3008
#define WM8994_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */
3009
#define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */
3010
#define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
3013
* R1072 (0x430) - AIF1 DAC1 Noise Gate
3015
#define WM8958_AIF1DAC1_NG_HLD_MASK 0x0060 /* AIF1DAC1_NG_HLD - [6:5] */
3016
#define WM8958_AIF1DAC1_NG_HLD_SHIFT 5 /* AIF1DAC1_NG_HLD - [6:5] */
3017
#define WM8958_AIF1DAC1_NG_HLD_WIDTH 2 /* AIF1DAC1_NG_HLD - [6:5] */
3018
#define WM8958_AIF1DAC1_NG_THR_MASK 0x000E /* AIF1DAC1_NG_THR - [3:1] */
3019
#define WM8958_AIF1DAC1_NG_THR_SHIFT 1 /* AIF1DAC1_NG_THR - [3:1] */
3020
#define WM8958_AIF1DAC1_NG_THR_WIDTH 3 /* AIF1DAC1_NG_THR - [3:1] */
3021
#define WM8958_AIF1DAC1_NG_ENA 0x0001 /* AIF1DAC1_NG_ENA */
3022
#define WM8958_AIF1DAC1_NG_ENA_MASK 0x0001 /* AIF1DAC1_NG_ENA */
3023
#define WM8958_AIF1DAC1_NG_ENA_SHIFT 0 /* AIF1DAC1_NG_ENA */
3024
#define WM8958_AIF1DAC1_NG_ENA_WIDTH 1 /* AIF1DAC1_NG_ENA */
3027
* R1073 (0x431) - AIF1 DAC2 Noise Gate
3029
#define WM8958_AIF1DAC2_NG_HLD_MASK 0x0060 /* AIF1DAC2_NG_HLD - [6:5] */
3030
#define WM8958_AIF1DAC2_NG_HLD_SHIFT 5 /* AIF1DAC2_NG_HLD - [6:5] */
3031
#define WM8958_AIF1DAC2_NG_HLD_WIDTH 2 /* AIF1DAC2_NG_HLD - [6:5] */
3032
#define WM8958_AIF1DAC2_NG_THR_MASK 0x000E /* AIF1DAC2_NG_THR - [3:1] */
3033
#define WM8958_AIF1DAC2_NG_THR_SHIFT 1 /* AIF1DAC2_NG_THR - [3:1] */
3034
#define WM8958_AIF1DAC2_NG_THR_WIDTH 3 /* AIF1DAC2_NG_THR - [3:1] */
3035
#define WM8958_AIF1DAC2_NG_ENA 0x0001 /* AIF1DAC2_NG_ENA */
3036
#define WM8958_AIF1DAC2_NG_ENA_MASK 0x0001 /* AIF1DAC2_NG_ENA */
3037
#define WM8958_AIF1DAC2_NG_ENA_SHIFT 0 /* AIF1DAC2_NG_ENA */
3038
#define WM8958_AIF1DAC2_NG_ENA_WIDTH 1 /* AIF1DAC2_NG_ENA */
3041
* R1088 (0x440) - AIF1 DRC1 (1)
3043
#define WM8994_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3044
#define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3045
#define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3046
#define WM8994_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */
3047
#define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */
3048
#define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */
3049
#define WM8994_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */
3050
#define WM8994_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */
3051
#define WM8994_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */
3052
#define WM8994_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */
3053
#define WM8994_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */
3054
#define WM8994_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */
3055
#define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */
3056
#define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */
3057
#define WM8994_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */
3058
#define WM8994_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */
3059
#define WM8994_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */
3060
#define WM8994_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */
3061
#define WM8994_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
3062
#define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
3063
#define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */
3064
#define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */
3065
#define WM8994_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */
3066
#define WM8994_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */
3067
#define WM8994_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */
3068
#define WM8994_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */
3069
#define WM8994_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */
3070
#define WM8994_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */
3071
#define WM8994_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */
3072
#define WM8994_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */
3073
#define WM8994_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */
3074
#define WM8994_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */
3075
#define WM8994_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */
3076
#define WM8994_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */
3077
#define WM8994_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */
3078
#define WM8994_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */
3079
#define WM8994_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */
3080
#define WM8994_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */
3081
#define WM8994_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */
3082
#define WM8994_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */
3083
#define WM8994_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */
3084
#define WM8994_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */
3087
* R1089 (0x441) - AIF1 DRC1 (2)
3089
#define WM8994_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */
3090
#define WM8994_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */
3091
#define WM8994_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */
3092
#define WM8994_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */
3093
#define WM8994_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */
3094
#define WM8994_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */
3095
#define WM8994_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */
3096
#define WM8994_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */
3097
#define WM8994_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */
3098
#define WM8994_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */
3099
#define WM8994_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */
3100
#define WM8994_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */
3103
* R1090 (0x442) - AIF1 DRC1 (3)
3105
#define WM8994_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */
3106
#define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */
3107
#define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */
3108
#define WM8994_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */
3109
#define WM8994_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */
3110
#define WM8994_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */
3111
#define WM8994_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */
3112
#define WM8994_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */
3113
#define WM8994_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */
3114
#define WM8994_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */
3115
#define WM8994_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */
3116
#define WM8994_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */
3117
#define WM8994_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */
3118
#define WM8994_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */
3119
#define WM8994_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */
3120
#define WM8994_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */
3121
#define WM8994_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */
3122
#define WM8994_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */
3125
* R1091 (0x443) - AIF1 DRC1 (4)
3127
#define WM8994_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */
3128
#define WM8994_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */
3129
#define WM8994_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */
3130
#define WM8994_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */
3131
#define WM8994_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */
3132
#define WM8994_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */
3135
* R1092 (0x444) - AIF1 DRC1 (5)
3137
#define WM8994_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */
3138
#define WM8994_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
3139
#define WM8994_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
3140
#define WM8994_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */
3141
#define WM8994_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */
3142
#define WM8994_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */
3145
* R1104 (0x450) - AIF1 DRC2 (1)
3147
#define WM8994_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3148
#define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3149
#define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3150
#define WM8994_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */
3151
#define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */
3152
#define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */
3153
#define WM8994_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */
3154
#define WM8994_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */
3155
#define WM8994_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */
3156
#define WM8994_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */
3157
#define WM8994_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */
3158
#define WM8994_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */
3159
#define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */
3160
#define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */
3161
#define WM8994_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */
3162
#define WM8994_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */
3163
#define WM8994_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */
3164
#define WM8994_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */
3165
#define WM8994_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
3166
#define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
3167
#define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */
3168
#define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */
3169
#define WM8994_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */
3170
#define WM8994_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */
3171
#define WM8994_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */
3172
#define WM8994_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */
3173
#define WM8994_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */
3174
#define WM8994_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */
3175
#define WM8994_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */
3176
#define WM8994_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */
3177
#define WM8994_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */
3178
#define WM8994_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */
3179
#define WM8994_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */
3180
#define WM8994_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */
3181
#define WM8994_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */
3182
#define WM8994_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */
3183
#define WM8994_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */
3184
#define WM8994_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */
3185
#define WM8994_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */
3186
#define WM8994_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */
3187
#define WM8994_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */
3188
#define WM8994_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */
3191
* R1105 (0x451) - AIF1 DRC2 (2)
3193
#define WM8994_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */
3194
#define WM8994_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */
3195
#define WM8994_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */
3196
#define WM8994_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */
3197
#define WM8994_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */
3198
#define WM8994_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */
3199
#define WM8994_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */
3200
#define WM8994_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */
3201
#define WM8994_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */
3202
#define WM8994_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */
3203
#define WM8994_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */
3204
#define WM8994_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */
3207
* R1106 (0x452) - AIF1 DRC2 (3)
3209
#define WM8994_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */
3210
#define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */
3211
#define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */
3212
#define WM8994_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */
3213
#define WM8994_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */
3214
#define WM8994_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */
3215
#define WM8994_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */
3216
#define WM8994_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */
3217
#define WM8994_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */
3218
#define WM8994_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */
3219
#define WM8994_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */
3220
#define WM8994_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */
3221
#define WM8994_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */
3222
#define WM8994_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */
3223
#define WM8994_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */
3224
#define WM8994_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */
3225
#define WM8994_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */
3226
#define WM8994_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */
3229
* R1107 (0x453) - AIF1 DRC2 (4)
3231
#define WM8994_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */
3232
#define WM8994_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */
3233
#define WM8994_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */
3234
#define WM8994_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */
3235
#define WM8994_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */
3236
#define WM8994_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */
3239
* R1108 (0x454) - AIF1 DRC2 (5)
3241
#define WM8994_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */
3242
#define WM8994_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
3243
#define WM8994_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
3244
#define WM8994_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */
3245
#define WM8994_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */
3246
#define WM8994_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */
3249
* R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
3251
#define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3252
#define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3253
#define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3254
#define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3255
#define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3256
#define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3257
#define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3258
#define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3259
#define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3260
#define WM8994_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */
3261
#define WM8994_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */
3262
#define WM8994_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */
3263
#define WM8994_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */
3266
* R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
3268
#define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3269
#define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3270
#define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3271
#define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3272
#define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3273
#define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3276
* R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
3278
#define WM8994_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */
3279
#define WM8994_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */
3280
#define WM8994_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */
3283
* R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
3285
#define WM8994_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */
3286
#define WM8994_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */
3287
#define WM8994_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */
3290
* R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
3292
#define WM8994_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */
3293
#define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */
3294
#define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */
3297
* R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
3299
#define WM8994_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */
3300
#define WM8994_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */
3301
#define WM8994_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */
3304
* R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
3306
#define WM8994_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */
3307
#define WM8994_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */
3308
#define WM8994_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */
3311
* R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
3313
#define WM8994_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */
3314
#define WM8994_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */
3315
#define WM8994_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */
3318
* R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
3320
#define WM8994_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */
3321
#define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */
3322
#define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */
3325
* R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
3327
#define WM8994_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */
3328
#define WM8994_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */
3329
#define WM8994_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */
3332
* R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
3334
#define WM8994_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */
3335
#define WM8994_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */
3336
#define WM8994_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */
3339
* R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
3341
#define WM8994_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */
3342
#define WM8994_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */
3343
#define WM8994_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */
3346
* R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
3348
#define WM8994_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */
3349
#define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */
3350
#define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */
3353
* R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
3355
#define WM8994_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */
3356
#define WM8994_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */
3357
#define WM8994_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */
3360
* R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
3362
#define WM8994_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */
3363
#define WM8994_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */
3364
#define WM8994_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */
3367
* R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
3369
#define WM8994_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */
3370
#define WM8994_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */
3371
#define WM8994_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */
3374
* R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
3376
#define WM8994_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */
3377
#define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */
3378
#define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */
3381
* R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
3383
#define WM8994_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */
3384
#define WM8994_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */
3385
#define WM8994_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */
3388
* R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
3390
#define WM8994_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */
3391
#define WM8994_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */
3392
#define WM8994_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */
3395
* R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
3397
#define WM8994_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */
3398
#define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */
3399
#define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */
3402
* R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
3404
#define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3405
#define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3406
#define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3407
#define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3408
#define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3409
#define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3410
#define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3411
#define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3412
#define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3413
#define WM8994_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */
3414
#define WM8994_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */
3415
#define WM8994_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */
3416
#define WM8994_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */
3419
* R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
3421
#define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3422
#define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3423
#define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3424
#define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3425
#define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3426
#define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3429
* R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
3431
#define WM8994_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */
3432
#define WM8994_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */
3433
#define WM8994_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */
3436
* R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
3438
#define WM8994_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */
3439
#define WM8994_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */
3440
#define WM8994_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */
3443
* R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
3445
#define WM8994_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */
3446
#define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */
3447
#define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */
3450
* R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
3452
#define WM8994_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */
3453
#define WM8994_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */
3454
#define WM8994_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */
3457
* R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
3459
#define WM8994_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */
3460
#define WM8994_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */
3461
#define WM8994_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */
3464
* R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
3466
#define WM8994_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */
3467
#define WM8994_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */
3468
#define WM8994_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */
3471
* R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
3473
#define WM8994_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */
3474
#define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */
3475
#define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */
3478
* R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
3480
#define WM8994_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */
3481
#define WM8994_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */
3482
#define WM8994_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */
3485
* R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
3487
#define WM8994_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */
3488
#define WM8994_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */
3489
#define WM8994_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */
3492
* R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
3494
#define WM8994_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */
3495
#define WM8994_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */
3496
#define WM8994_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */
3499
* R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
3501
#define WM8994_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */
3502
#define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */
3503
#define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */
3506
* R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
3508
#define WM8994_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */
3509
#define WM8994_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */
3510
#define WM8994_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */
3513
* R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
3515
#define WM8994_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */
3516
#define WM8994_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */
3517
#define WM8994_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */
3520
* R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
3522
#define WM8994_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */
3523
#define WM8994_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */
3524
#define WM8994_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */
3527
* R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
3529
#define WM8994_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */
3530
#define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */
3531
#define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */
3534
* R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
3536
#define WM8994_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */
3537
#define WM8994_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */
3538
#define WM8994_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */
3541
* R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
3543
#define WM8994_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */
3544
#define WM8994_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */
3545
#define WM8994_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */
3548
* R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
3550
#define WM8994_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */
3551
#define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */
3552
#define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */
3555
* R1280 (0x500) - AIF2 ADC Left Volume
3557
#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
3558
#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
3559
#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
3560
#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
3561
#define WM8994_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */
3562
#define WM8994_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */
3563
#define WM8994_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */
3566
* R1281 (0x501) - AIF2 ADC Right Volume
3568
#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
3569
#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
3570
#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
3571
#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
3572
#define WM8994_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */
3573
#define WM8994_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */
3574
#define WM8994_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */
3577
* R1282 (0x502) - AIF2 DAC Left Volume
3579
#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
3580
#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
3581
#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
3582
#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
3583
#define WM8994_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */
3584
#define WM8994_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */
3585
#define WM8994_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */
3588
* R1283 (0x503) - AIF2 DAC Right Volume
3590
#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
3591
#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
3592
#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
3593
#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
3594
#define WM8994_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */
3595
#define WM8994_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */
3596
#define WM8994_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */
3599
* R1296 (0x510) - AIF2 ADC Filters
3601
#define WM8994_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */
3602
#define WM8994_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */
3603
#define WM8994_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */
3604
#define WM8994_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */
3605
#define WM8994_AIF2ADC_HPF_CUT_MASK 0x6000 /* AIF2ADC_HPF_CUT - [14:13] */
3606
#define WM8994_AIF2ADC_HPF_CUT_SHIFT 13 /* AIF2ADC_HPF_CUT - [14:13] */
3607
#define WM8994_AIF2ADC_HPF_CUT_WIDTH 2 /* AIF2ADC_HPF_CUT - [14:13] */
3608
#define WM8994_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */
3609
#define WM8994_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */
3610
#define WM8994_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */
3611
#define WM8994_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */
3612
#define WM8994_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */
3613
#define WM8994_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */
3614
#define WM8994_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */
3615
#define WM8994_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */
3618
* R1312 (0x520) - AIF2 DAC Filters (1)
3620
#define WM8994_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */
3621
#define WM8994_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */
3622
#define WM8994_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */
3623
#define WM8994_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */
3624
#define WM8994_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */
3625
#define WM8994_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */
3626
#define WM8994_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */
3627
#define WM8994_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */
3628
#define WM8994_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */
3629
#define WM8994_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */
3630
#define WM8994_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */
3631
#define WM8994_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */
3632
#define WM8994_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */
3633
#define WM8994_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */
3634
#define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */
3635
#define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */
3636
#define WM8994_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */
3637
#define WM8994_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */
3638
#define WM8994_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */
3641
* R1313 (0x521) - AIF2 DAC Filters (2)
3643
#define WM8994_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */
3644
#define WM8994_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */
3645
#define WM8994_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */
3646
#define WM8994_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */
3647
#define WM8994_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */
3648
#define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */
3649
#define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
3652
* R1328 (0x530) - AIF2 DAC Noise Gate
3654
#define WM8958_AIF2DAC_NG_HLD_MASK 0x0060 /* AIF2DAC_NG_HLD - [6:5] */
3655
#define WM8958_AIF2DAC_NG_HLD_SHIFT 5 /* AIF2DAC_NG_HLD - [6:5] */
3656
#define WM8958_AIF2DAC_NG_HLD_WIDTH 2 /* AIF2DAC_NG_HLD - [6:5] */
3657
#define WM8958_AIF2DAC_NG_THR_MASK 0x000E /* AIF2DAC_NG_THR - [3:1] */
3658
#define WM8958_AIF2DAC_NG_THR_SHIFT 1 /* AIF2DAC_NG_THR - [3:1] */
3659
#define WM8958_AIF2DAC_NG_THR_WIDTH 3 /* AIF2DAC_NG_THR - [3:1] */
3660
#define WM8958_AIF2DAC_NG_ENA 0x0001 /* AIF2DAC_NG_ENA */
3661
#define WM8958_AIF2DAC_NG_ENA_MASK 0x0001 /* AIF2DAC_NG_ENA */
3662
#define WM8958_AIF2DAC_NG_ENA_SHIFT 0 /* AIF2DAC_NG_ENA */
3663
#define WM8958_AIF2DAC_NG_ENA_WIDTH 1 /* AIF2DAC_NG_ENA */
3666
* R1344 (0x540) - AIF2 DRC (1)
3668
#define WM8994_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */
3669
#define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */
3670
#define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */
3671
#define WM8994_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */
3672
#define WM8994_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */
3673
#define WM8994_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */
3674
#define WM8994_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */
3675
#define WM8994_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */
3676
#define WM8994_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */
3677
#define WM8994_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */
3678
#define WM8994_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */
3679
#define WM8994_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */
3680
#define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */
3681
#define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */
3682
#define WM8994_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */
3683
#define WM8994_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */
3684
#define WM8994_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */
3685
#define WM8994_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */
3686
#define WM8994_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
3687
#define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
3688
#define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */
3689
#define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */
3690
#define WM8994_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */
3691
#define WM8994_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */
3692
#define WM8994_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */
3693
#define WM8994_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */
3694
#define WM8994_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */
3695
#define WM8994_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */
3696
#define WM8994_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */
3697
#define WM8994_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */
3698
#define WM8994_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */
3699
#define WM8994_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */
3700
#define WM8994_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */
3701
#define WM8994_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */
3702
#define WM8994_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */
3703
#define WM8994_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */
3704
#define WM8994_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */
3705
#define WM8994_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */
3706
#define WM8994_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */
3707
#define WM8994_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */
3708
#define WM8994_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */
3709
#define WM8994_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */
3712
* R1345 (0x541) - AIF2 DRC (2)
3714
#define WM8994_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */
3715
#define WM8994_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */
3716
#define WM8994_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */
3717
#define WM8994_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */
3718
#define WM8994_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */
3719
#define WM8994_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */
3720
#define WM8994_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */
3721
#define WM8994_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */
3722
#define WM8994_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */
3723
#define WM8994_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */
3724
#define WM8994_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */
3725
#define WM8994_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */
3728
* R1346 (0x542) - AIF2 DRC (3)
3730
#define WM8994_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */
3731
#define WM8994_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */
3732
#define WM8994_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */
3733
#define WM8994_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */
3734
#define WM8994_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */
3735
#define WM8994_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */
3736
#define WM8994_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */
3737
#define WM8994_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */
3738
#define WM8994_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */
3739
#define WM8994_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */
3740
#define WM8994_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */
3741
#define WM8994_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */
3742
#define WM8994_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */
3743
#define WM8994_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */
3744
#define WM8994_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */
3745
#define WM8994_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */
3746
#define WM8994_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */
3747
#define WM8994_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */
3750
* R1347 (0x543) - AIF2 DRC (4)
3752
#define WM8994_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */
3753
#define WM8994_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */
3754
#define WM8994_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */
3755
#define WM8994_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */
3756
#define WM8994_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */
3757
#define WM8994_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */
3760
* R1348 (0x544) - AIF2 DRC (5)
3762
#define WM8994_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */
3763
#define WM8994_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */
3764
#define WM8994_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */
3765
#define WM8994_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */
3766
#define WM8994_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */
3767
#define WM8994_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */
3770
* R1408 (0x580) - AIF2 EQ Gains (1)
3772
#define WM8994_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3773
#define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3774
#define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3775
#define WM8994_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3776
#define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3777
#define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3778
#define WM8994_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3779
#define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3780
#define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3781
#define WM8994_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */
3782
#define WM8994_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */
3783
#define WM8994_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */
3784
#define WM8994_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */
3787
* R1409 (0x581) - AIF2 EQ Gains (2)
3789
#define WM8994_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3790
#define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3791
#define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3792
#define WM8994_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3793
#define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3794
#define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3797
* R1410 (0x582) - AIF2 EQ Band 1 A
3799
#define WM8994_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */
3800
#define WM8994_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */
3801
#define WM8994_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */
3804
* R1411 (0x583) - AIF2 EQ Band 1 B
3806
#define WM8994_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */
3807
#define WM8994_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */
3808
#define WM8994_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */
3811
* R1412 (0x584) - AIF2 EQ Band 1 PG
3813
#define WM8994_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */
3814
#define WM8994_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */
3815
#define WM8994_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */
3818
* R1413 (0x585) - AIF2 EQ Band 2 A
3820
#define WM8994_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */
3821
#define WM8994_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */
3822
#define WM8994_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */
3825
* R1414 (0x586) - AIF2 EQ Band 2 B
3827
#define WM8994_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */
3828
#define WM8994_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */
3829
#define WM8994_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */
3832
* R1415 (0x587) - AIF2 EQ Band 2 C
3834
#define WM8994_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */
3835
#define WM8994_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */
3836
#define WM8994_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */
3839
* R1416 (0x588) - AIF2 EQ Band 2 PG
3841
#define WM8994_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */
3842
#define WM8994_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */
3843
#define WM8994_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */
3846
* R1417 (0x589) - AIF2 EQ Band 3 A
3848
#define WM8994_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */
3849
#define WM8994_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */
3850
#define WM8994_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */
3853
* R1418 (0x58A) - AIF2 EQ Band 3 B
3855
#define WM8994_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */
3856
#define WM8994_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */
3857
#define WM8994_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */
3860
* R1419 (0x58B) - AIF2 EQ Band 3 C
3862
#define WM8994_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */
3863
#define WM8994_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */
3864
#define WM8994_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */
3867
* R1420 (0x58C) - AIF2 EQ Band 3 PG
3869
#define WM8994_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */
3870
#define WM8994_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */
3871
#define WM8994_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */
3874
* R1421 (0x58D) - AIF2 EQ Band 4 A
3876
#define WM8994_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */
3877
#define WM8994_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */
3878
#define WM8994_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */
3881
* R1422 (0x58E) - AIF2 EQ Band 4 B
3883
#define WM8994_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */
3884
#define WM8994_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */
3885
#define WM8994_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */
3888
* R1423 (0x58F) - AIF2 EQ Band 4 C
3890
#define WM8994_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */
3891
#define WM8994_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */
3892
#define WM8994_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */
3895
* R1424 (0x590) - AIF2 EQ Band 4 PG
3897
#define WM8994_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */
3898
#define WM8994_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */
3899
#define WM8994_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */
3902
* R1425 (0x591) - AIF2 EQ Band 5 A
3904
#define WM8994_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */
3905
#define WM8994_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */
3906
#define WM8994_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */
3909
* R1426 (0x592) - AIF2 EQ Band 5 B
3911
#define WM8994_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */
3912
#define WM8994_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */
3913
#define WM8994_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */
3916
* R1427 (0x593) - AIF2 EQ Band 5 PG
3918
#define WM8994_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */
3919
#define WM8994_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */
3920
#define WM8994_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */
3923
* R1536 (0x600) - DAC1 Mixer Volumes
3925
#define WM8994_ADCR_DAC1_VOL_MASK 0x01E0 /* ADCR_DAC1_VOL - [8:5] */
3926
#define WM8994_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [8:5] */
3927
#define WM8994_ADCR_DAC1_VOL_WIDTH 4 /* ADCR_DAC1_VOL - [8:5] */
3928
#define WM8994_ADCL_DAC1_VOL_MASK 0x000F /* ADCL_DAC1_VOL - [3:0] */
3929
#define WM8994_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [3:0] */
3930
#define WM8994_ADCL_DAC1_VOL_WIDTH 4 /* ADCL_DAC1_VOL - [3:0] */
3933
* R1537 (0x601) - DAC1 Left Mixer Routing
3935
#define WM8994_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */
3936
#define WM8994_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */
3937
#define WM8994_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */
3938
#define WM8994_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
3939
#define WM8994_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */
3940
#define WM8994_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */
3941
#define WM8994_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */
3942
#define WM8994_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
3943
#define WM8994_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */
3944
#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */
3945
#define WM8994_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */
3946
#define WM8994_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */
3947
#define WM8994_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */
3948
#define WM8994_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */
3949
#define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */
3950
#define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */
3951
#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */
3952
#define WM8994_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */
3953
#define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */
3954
#define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */
3957
* R1538 (0x602) - DAC1 Right Mixer Routing
3959
#define WM8994_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */
3960
#define WM8994_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */
3961
#define WM8994_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */
3962
#define WM8994_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
3963
#define WM8994_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */
3964
#define WM8994_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */
3965
#define WM8994_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */
3966
#define WM8994_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
3967
#define WM8994_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */
3968
#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */
3969
#define WM8994_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */
3970
#define WM8994_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */
3971
#define WM8994_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */
3972
#define WM8994_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */
3973
#define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */
3974
#define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */
3975
#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */
3976
#define WM8994_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */
3977
#define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */
3978
#define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */
3981
* R1539 (0x603) - DAC2 Mixer Volumes
3983
#define WM8994_ADCR_DAC2_VOL_MASK 0x01E0 /* ADCR_DAC2_VOL - [8:5] */
3984
#define WM8994_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [8:5] */
3985
#define WM8994_ADCR_DAC2_VOL_WIDTH 4 /* ADCR_DAC2_VOL - [8:5] */
3986
#define WM8994_ADCL_DAC2_VOL_MASK 0x000F /* ADCL_DAC2_VOL - [3:0] */
3987
#define WM8994_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [3:0] */
3988
#define WM8994_ADCL_DAC2_VOL_WIDTH 4 /* ADCL_DAC2_VOL - [3:0] */
3991
* R1540 (0x604) - DAC2 Left Mixer Routing
3993
#define WM8994_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */
3994
#define WM8994_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */
3995
#define WM8994_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */
3996
#define WM8994_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
3997
#define WM8994_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */
3998
#define WM8994_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */
3999
#define WM8994_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */
4000
#define WM8994_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
4001
#define WM8994_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */
4002
#define WM8994_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */
4003
#define WM8994_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */
4004
#define WM8994_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */
4005
#define WM8994_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */
4006
#define WM8994_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */
4007
#define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */
4008
#define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */
4009
#define WM8994_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */
4010
#define WM8994_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */
4011
#define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */
4012
#define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */
4015
* R1541 (0x605) - DAC2 Right Mixer Routing
4017
#define WM8994_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */
4018
#define WM8994_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */
4019
#define WM8994_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */
4020
#define WM8994_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
4021
#define WM8994_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */
4022
#define WM8994_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */
4023
#define WM8994_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */
4024
#define WM8994_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
4025
#define WM8994_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */
4026
#define WM8994_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */
4027
#define WM8994_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */
4028
#define WM8994_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */
4029
#define WM8994_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */
4030
#define WM8994_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */
4031
#define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */
4032
#define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */
4033
#define WM8994_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */
4034
#define WM8994_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */
4035
#define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */
4036
#define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */
4039
* R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
4041
#define WM8994_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */
4042
#define WM8994_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */
4043
#define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */
4044
#define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */
4045
#define WM8994_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
4046
#define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
4047
#define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */
4048
#define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */
4051
* R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
4053
#define WM8994_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */
4054
#define WM8994_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */
4055
#define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */
4056
#define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */
4057
#define WM8994_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
4058
#define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
4059
#define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */
4060
#define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */
4063
* R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
4065
#define WM8994_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */
4066
#define WM8994_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */
4067
#define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */
4068
#define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */
4069
#define WM8994_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
4070
#define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
4071
#define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */
4072
#define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */
4075
* R1545 (0x609) - AIF1 ADC2 Right mixer Routing
4077
#define WM8994_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */
4078
#define WM8994_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */
4079
#define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */
4080
#define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */
4081
#define WM8994_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
4082
#define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
4083
#define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */
4084
#define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */
4087
* R1552 (0x610) - DAC1 Left Volume
4089
#define WM8994_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
4090
#define WM8994_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
4091
#define WM8994_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
4092
#define WM8994_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
4093
#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */
4094
#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */
4095
#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */
4096
#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */
4097
#define WM8994_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
4098
#define WM8994_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
4099
#define WM8994_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
4102
* R1553 (0x611) - DAC1 Right Volume
4104
#define WM8994_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
4105
#define WM8994_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
4106
#define WM8994_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
4107
#define WM8994_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
4108
#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */
4109
#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */
4110
#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */
4111
#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */
4112
#define WM8994_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
4113
#define WM8994_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
4114
#define WM8994_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
4117
* R1554 (0x612) - DAC2 Left Volume
4119
#define WM8994_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
4120
#define WM8994_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
4121
#define WM8994_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
4122
#define WM8994_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
4123
#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */
4124
#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */
4125
#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */
4126
#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */
4127
#define WM8994_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
4128
#define WM8994_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
4129
#define WM8994_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
4132
* R1555 (0x613) - DAC2 Right Volume
4134
#define WM8994_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
4135
#define WM8994_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
4136
#define WM8994_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
4137
#define WM8994_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
4138
#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */
4139
#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */
4140
#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */
4141
#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */
4142
#define WM8994_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
4143
#define WM8994_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
4144
#define WM8994_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
4147
* R1556 (0x614) - DAC Softmute
4149
#define WM8994_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
4150
#define WM8994_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
4151
#define WM8994_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
4152
#define WM8994_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
4153
#define WM8994_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
4154
#define WM8994_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
4155
#define WM8994_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
4156
#define WM8994_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
4159
* R1568 (0x620) - Oversampling
4161
#define WM8994_ADC_OSR128 0x0002 /* ADC_OSR128 */
4162
#define WM8994_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
4163
#define WM8994_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
4164
#define WM8994_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
4165
#define WM8994_DAC_OSR128 0x0001 /* DAC_OSR128 */
4166
#define WM8994_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
4167
#define WM8994_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
4168
#define WM8994_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
4171
* R1569 (0x621) - Sidetone
4173
#define WM8994_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
4174
#define WM8994_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
4175
#define WM8994_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
4176
#define WM8994_ST_HPF 0x0040 /* ST_HPF */
4177
#define WM8994_ST_HPF_MASK 0x0040 /* ST_HPF */
4178
#define WM8994_ST_HPF_SHIFT 6 /* ST_HPF */
4179
#define WM8994_ST_HPF_WIDTH 1 /* ST_HPF */
4180
#define WM8994_STR_SEL 0x0002 /* STR_SEL */
4181
#define WM8994_STR_SEL_MASK 0x0002 /* STR_SEL */
4182
#define WM8994_STR_SEL_SHIFT 1 /* STR_SEL */
4183
#define WM8994_STR_SEL_WIDTH 1 /* STR_SEL */
4184
#define WM8994_STL_SEL 0x0001 /* STL_SEL */
4185
#define WM8994_STL_SEL_MASK 0x0001 /* STL_SEL */
4186
#define WM8994_STL_SEL_SHIFT 0 /* STL_SEL */
4187
#define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */
4190
* R1824 (0x720) - Pull Control (1)
4192
#define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */
4193
#define WM8994_DMICDAT2_PU_MASK 0x0800 /* DMICDAT2_PU */
4194
#define WM8994_DMICDAT2_PU_SHIFT 11 /* DMICDAT2_PU */
4195
#define WM8994_DMICDAT2_PU_WIDTH 1 /* DMICDAT2_PU */
4196
#define WM8994_DMICDAT2_PD 0x0400 /* DMICDAT2_PD */
4197
#define WM8994_DMICDAT2_PD_MASK 0x0400 /* DMICDAT2_PD */
4198
#define WM8994_DMICDAT2_PD_SHIFT 10 /* DMICDAT2_PD */
4199
#define WM8994_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
4200
#define WM8994_DMICDAT1_PU 0x0200 /* DMICDAT1_PU */
4201
#define WM8994_DMICDAT1_PU_MASK 0x0200 /* DMICDAT1_PU */
4202
#define WM8994_DMICDAT1_PU_SHIFT 9 /* DMICDAT1_PU */
4203
#define WM8994_DMICDAT1_PU_WIDTH 1 /* DMICDAT1_PU */
4204
#define WM8994_DMICDAT1_PD 0x0100 /* DMICDAT1_PD */
4205
#define WM8994_DMICDAT1_PD_MASK 0x0100 /* DMICDAT1_PD */
4206
#define WM8994_DMICDAT1_PD_SHIFT 8 /* DMICDAT1_PD */
4207
#define WM8994_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
4208
#define WM8994_MCLK1_PU 0x0080 /* MCLK1_PU */
4209
#define WM8994_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
4210
#define WM8994_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
4211
#define WM8994_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
4212
#define WM8994_MCLK1_PD 0x0040 /* MCLK1_PD */
4213
#define WM8994_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
4214
#define WM8994_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
4215
#define WM8994_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
4216
#define WM8994_DACDAT1_PU 0x0020 /* DACDAT1_PU */
4217
#define WM8994_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
4218
#define WM8994_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
4219
#define WM8994_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
4220
#define WM8994_DACDAT1_PD 0x0010 /* DACDAT1_PD */
4221
#define WM8994_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
4222
#define WM8994_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
4223
#define WM8994_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
4224
#define WM8994_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
4225
#define WM8994_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
4226
#define WM8994_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
4227
#define WM8994_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
4228
#define WM8994_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
4229
#define WM8994_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
4230
#define WM8994_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
4231
#define WM8994_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
4232
#define WM8994_BCLK1_PU 0x0002 /* BCLK1_PU */
4233
#define WM8994_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
4234
#define WM8994_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
4235
#define WM8994_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
4236
#define WM8994_BCLK1_PD 0x0001 /* BCLK1_PD */
4237
#define WM8994_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
4238
#define WM8994_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
4239
#define WM8994_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
4242
* R1825 (0x721) - Pull Control (2)
4244
#define WM8994_CSNADDR_PD 0x0100 /* CSNADDR_PD */
4245
#define WM8994_CSNADDR_PD_MASK 0x0100 /* CSNADDR_PD */
4246
#define WM8994_CSNADDR_PD_SHIFT 8 /* CSNADDR_PD */
4247
#define WM8994_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */
4248
#define WM8994_LDO2ENA_PD 0x0040 /* LDO2ENA_PD */
4249
#define WM8994_LDO2ENA_PD_MASK 0x0040 /* LDO2ENA_PD */
4250
#define WM8994_LDO2ENA_PD_SHIFT 6 /* LDO2ENA_PD */
4251
#define WM8994_LDO2ENA_PD_WIDTH 1 /* LDO2ENA_PD */
4252
#define WM8994_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */
4253
#define WM8994_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */
4254
#define WM8994_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */
4255
#define WM8994_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
4256
#define WM8994_CIFMODE_PD 0x0004 /* CIFMODE_PD */
4257
#define WM8994_CIFMODE_PD_MASK 0x0004 /* CIFMODE_PD */
4258
#define WM8994_CIFMODE_PD_SHIFT 2 /* CIFMODE_PD */
4259
#define WM8994_CIFMODE_PD_WIDTH 1 /* CIFMODE_PD */
4260
#define WM8994_SPKMODE_PU 0x0002 /* SPKMODE_PU */
4261
#define WM8994_SPKMODE_PU_MASK 0x0002 /* SPKMODE_PU */
4262
#define WM8994_SPKMODE_PU_SHIFT 1 /* SPKMODE_PU */
4263
#define WM8994_SPKMODE_PU_WIDTH 1 /* SPKMODE_PU */
4266
* R1840 (0x730) - Interrupt Status 1
4268
#define WM8994_GP11_EINT 0x0400 /* GP11_EINT */
4269
#define WM8994_GP11_EINT_MASK 0x0400 /* GP11_EINT */
4270
#define WM8994_GP11_EINT_SHIFT 10 /* GP11_EINT */
4271
#define WM8994_GP11_EINT_WIDTH 1 /* GP11_EINT */
4272
#define WM8994_GP10_EINT 0x0200 /* GP10_EINT */
4273
#define WM8994_GP10_EINT_MASK 0x0200 /* GP10_EINT */
4274
#define WM8994_GP10_EINT_SHIFT 9 /* GP10_EINT */
4275
#define WM8994_GP10_EINT_WIDTH 1 /* GP10_EINT */
4276
#define WM8994_GP9_EINT 0x0100 /* GP9_EINT */
4277
#define WM8994_GP9_EINT_MASK 0x0100 /* GP9_EINT */
4278
#define WM8994_GP9_EINT_SHIFT 8 /* GP9_EINT */
4279
#define WM8994_GP9_EINT_WIDTH 1 /* GP9_EINT */
4280
#define WM8994_GP8_EINT 0x0080 /* GP8_EINT */
4281
#define WM8994_GP8_EINT_MASK 0x0080 /* GP8_EINT */
4282
#define WM8994_GP8_EINT_SHIFT 7 /* GP8_EINT */
4283
#define WM8994_GP8_EINT_WIDTH 1 /* GP8_EINT */
4284
#define WM8994_GP7_EINT 0x0040 /* GP7_EINT */
4285
#define WM8994_GP7_EINT_MASK 0x0040 /* GP7_EINT */
4286
#define WM8994_GP7_EINT_SHIFT 6 /* GP7_EINT */
4287
#define WM8994_GP7_EINT_WIDTH 1 /* GP7_EINT */
4288
#define WM8994_GP6_EINT 0x0020 /* GP6_EINT */
4289
#define WM8994_GP6_EINT_MASK 0x0020 /* GP6_EINT */
4290
#define WM8994_GP6_EINT_SHIFT 5 /* GP6_EINT */
4291
#define WM8994_GP6_EINT_WIDTH 1 /* GP6_EINT */
4292
#define WM8994_GP5_EINT 0x0010 /* GP5_EINT */
4293
#define WM8994_GP5_EINT_MASK 0x0010 /* GP5_EINT */
4294
#define WM8994_GP5_EINT_SHIFT 4 /* GP5_EINT */
4295
#define WM8994_GP5_EINT_WIDTH 1 /* GP5_EINT */
4296
#define WM8994_GP4_EINT 0x0008 /* GP4_EINT */
4297
#define WM8994_GP4_EINT_MASK 0x0008 /* GP4_EINT */
4298
#define WM8994_GP4_EINT_SHIFT 3 /* GP4_EINT */
4299
#define WM8994_GP4_EINT_WIDTH 1 /* GP4_EINT */
4300
#define WM8994_GP3_EINT 0x0004 /* GP3_EINT */
4301
#define WM8994_GP3_EINT_MASK 0x0004 /* GP3_EINT */
4302
#define WM8994_GP3_EINT_SHIFT 2 /* GP3_EINT */
4303
#define WM8994_GP3_EINT_WIDTH 1 /* GP3_EINT */
4304
#define WM8994_GP2_EINT 0x0002 /* GP2_EINT */
4305
#define WM8994_GP2_EINT_MASK 0x0002 /* GP2_EINT */
4306
#define WM8994_GP2_EINT_SHIFT 1 /* GP2_EINT */
4307
#define WM8994_GP2_EINT_WIDTH 1 /* GP2_EINT */
4308
#define WM8994_GP1_EINT 0x0001 /* GP1_EINT */
4309
#define WM8994_GP1_EINT_MASK 0x0001 /* GP1_EINT */
4310
#define WM8994_GP1_EINT_SHIFT 0 /* GP1_EINT */
4311
#define WM8994_GP1_EINT_WIDTH 1 /* GP1_EINT */
4314
* R1841 (0x731) - Interrupt Status 2
4316
#define WM8994_TEMP_WARN_EINT 0x8000 /* TEMP_WARN_EINT */
4317
#define WM8994_TEMP_WARN_EINT_MASK 0x8000 /* TEMP_WARN_EINT */
4318
#define WM8994_TEMP_WARN_EINT_SHIFT 15 /* TEMP_WARN_EINT */
4319
#define WM8994_TEMP_WARN_EINT_WIDTH 1 /* TEMP_WARN_EINT */
4320
#define WM8994_DCS_DONE_EINT 0x4000 /* DCS_DONE_EINT */
4321
#define WM8994_DCS_DONE_EINT_MASK 0x4000 /* DCS_DONE_EINT */
4322
#define WM8994_DCS_DONE_EINT_SHIFT 14 /* DCS_DONE_EINT */
4323
#define WM8994_DCS_DONE_EINT_WIDTH 1 /* DCS_DONE_EINT */
4324
#define WM8994_WSEQ_DONE_EINT 0x2000 /* WSEQ_DONE_EINT */
4325
#define WM8994_WSEQ_DONE_EINT_MASK 0x2000 /* WSEQ_DONE_EINT */
4326
#define WM8994_WSEQ_DONE_EINT_SHIFT 13 /* WSEQ_DONE_EINT */
4327
#define WM8994_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
4328
#define WM8994_FIFOS_ERR_EINT 0x1000 /* FIFOS_ERR_EINT */
4329
#define WM8994_FIFOS_ERR_EINT_MASK 0x1000 /* FIFOS_ERR_EINT */
4330
#define WM8994_FIFOS_ERR_EINT_SHIFT 12 /* FIFOS_ERR_EINT */
4331
#define WM8994_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
4332
#define WM8994_AIF2DRC_SIG_DET_EINT 0x0800 /* AIF2DRC_SIG_DET_EINT */
4333
#define WM8994_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* AIF2DRC_SIG_DET_EINT */
4334
#define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* AIF2DRC_SIG_DET_EINT */
4335
#define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */
4336
#define WM8994_AIF1DRC2_SIG_DET_EINT 0x0400 /* AIF1DRC2_SIG_DET_EINT */
4337
#define WM8994_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* AIF1DRC2_SIG_DET_EINT */
4338
#define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* AIF1DRC2_SIG_DET_EINT */
4339
#define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */
4340
#define WM8994_AIF1DRC1_SIG_DET_EINT 0x0200 /* AIF1DRC1_SIG_DET_EINT */
4341
#define WM8994_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* AIF1DRC1_SIG_DET_EINT */
4342
#define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* AIF1DRC1_SIG_DET_EINT */
4343
#define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */
4344
#define WM8994_SRC2_LOCK_EINT 0x0100 /* SRC2_LOCK_EINT */
4345
#define WM8994_SRC2_LOCK_EINT_MASK 0x0100 /* SRC2_LOCK_EINT */
4346
#define WM8994_SRC2_LOCK_EINT_SHIFT 8 /* SRC2_LOCK_EINT */
4347
#define WM8994_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */
4348
#define WM8994_SRC1_LOCK_EINT 0x0080 /* SRC1_LOCK_EINT */
4349
#define WM8994_SRC1_LOCK_EINT_MASK 0x0080 /* SRC1_LOCK_EINT */
4350
#define WM8994_SRC1_LOCK_EINT_SHIFT 7 /* SRC1_LOCK_EINT */
4351
#define WM8994_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */
4352
#define WM8994_FLL2_LOCK_EINT 0x0040 /* FLL2_LOCK_EINT */
4353
#define WM8994_FLL2_LOCK_EINT_MASK 0x0040 /* FLL2_LOCK_EINT */
4354
#define WM8994_FLL2_LOCK_EINT_SHIFT 6 /* FLL2_LOCK_EINT */
4355
#define WM8994_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
4356
#define WM8994_FLL1_LOCK_EINT 0x0020 /* FLL1_LOCK_EINT */
4357
#define WM8994_FLL1_LOCK_EINT_MASK 0x0020 /* FLL1_LOCK_EINT */
4358
#define WM8994_FLL1_LOCK_EINT_SHIFT 5 /* FLL1_LOCK_EINT */
4359
#define WM8994_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
4360
#define WM8994_MIC2_SHRT_EINT 0x0010 /* MIC2_SHRT_EINT */
4361
#define WM8994_MIC2_SHRT_EINT_MASK 0x0010 /* MIC2_SHRT_EINT */
4362
#define WM8994_MIC2_SHRT_EINT_SHIFT 4 /* MIC2_SHRT_EINT */
4363
#define WM8994_MIC2_SHRT_EINT_WIDTH 1 /* MIC2_SHRT_EINT */
4364
#define WM8994_MIC2_DET_EINT 0x0008 /* MIC2_DET_EINT */
4365
#define WM8994_MIC2_DET_EINT_MASK 0x0008 /* MIC2_DET_EINT */
4366
#define WM8994_MIC2_DET_EINT_SHIFT 3 /* MIC2_DET_EINT */
4367
#define WM8994_MIC2_DET_EINT_WIDTH 1 /* MIC2_DET_EINT */
4368
#define WM8994_MIC1_SHRT_EINT 0x0004 /* MIC1_SHRT_EINT */
4369
#define WM8994_MIC1_SHRT_EINT_MASK 0x0004 /* MIC1_SHRT_EINT */
4370
#define WM8994_MIC1_SHRT_EINT_SHIFT 2 /* MIC1_SHRT_EINT */
4371
#define WM8994_MIC1_SHRT_EINT_WIDTH 1 /* MIC1_SHRT_EINT */
4372
#define WM8994_MIC1_DET_EINT 0x0002 /* MIC1_DET_EINT */
4373
#define WM8994_MIC1_DET_EINT_MASK 0x0002 /* MIC1_DET_EINT */
4374
#define WM8994_MIC1_DET_EINT_SHIFT 1 /* MIC1_DET_EINT */
4375
#define WM8994_MIC1_DET_EINT_WIDTH 1 /* MIC1_DET_EINT */
4376
#define WM8994_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */
4377
#define WM8994_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */
4378
#define WM8994_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */
4379
#define WM8994_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */
4382
* R1842 (0x732) - Interrupt Raw Status 2
4384
#define WM8994_TEMP_WARN_STS 0x8000 /* TEMP_WARN_STS */
4385
#define WM8994_TEMP_WARN_STS_MASK 0x8000 /* TEMP_WARN_STS */
4386
#define WM8994_TEMP_WARN_STS_SHIFT 15 /* TEMP_WARN_STS */
4387
#define WM8994_TEMP_WARN_STS_WIDTH 1 /* TEMP_WARN_STS */
4388
#define WM8994_DCS_DONE_STS 0x4000 /* DCS_DONE_STS */
4389
#define WM8994_DCS_DONE_STS_MASK 0x4000 /* DCS_DONE_STS */
4390
#define WM8994_DCS_DONE_STS_SHIFT 14 /* DCS_DONE_STS */
4391
#define WM8994_DCS_DONE_STS_WIDTH 1 /* DCS_DONE_STS */
4392
#define WM8994_WSEQ_DONE_STS 0x2000 /* WSEQ_DONE_STS */
4393
#define WM8994_WSEQ_DONE_STS_MASK 0x2000 /* WSEQ_DONE_STS */
4394
#define WM8994_WSEQ_DONE_STS_SHIFT 13 /* WSEQ_DONE_STS */
4395
#define WM8994_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
4396
#define WM8994_FIFOS_ERR_STS 0x1000 /* FIFOS_ERR_STS */
4397
#define WM8994_FIFOS_ERR_STS_MASK 0x1000 /* FIFOS_ERR_STS */
4398
#define WM8994_FIFOS_ERR_STS_SHIFT 12 /* FIFOS_ERR_STS */
4399
#define WM8994_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
4400
#define WM8994_AIF2DRC_SIG_DET_STS 0x0800 /* AIF2DRC_SIG_DET_STS */
4401
#define WM8994_AIF2DRC_SIG_DET_STS_MASK 0x0800 /* AIF2DRC_SIG_DET_STS */
4402
#define WM8994_AIF2DRC_SIG_DET_STS_SHIFT 11 /* AIF2DRC_SIG_DET_STS */
4403
#define WM8994_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */
4404
#define WM8994_AIF1DRC2_SIG_DET_STS 0x0400 /* AIF1DRC2_SIG_DET_STS */
4405
#define WM8994_AIF1DRC2_SIG_DET_STS_MASK 0x0400 /* AIF1DRC2_SIG_DET_STS */
4406
#define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT 10 /* AIF1DRC2_SIG_DET_STS */
4407
#define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */
4408
#define WM8994_AIF1DRC1_SIG_DET_STS 0x0200 /* AIF1DRC1_SIG_DET_STS */
4409
#define WM8994_AIF1DRC1_SIG_DET_STS_MASK 0x0200 /* AIF1DRC1_SIG_DET_STS */
4410
#define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT 9 /* AIF1DRC1_SIG_DET_STS */
4411
#define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */
4412
#define WM8994_SRC2_LOCK_STS 0x0100 /* SRC2_LOCK_STS */
4413
#define WM8994_SRC2_LOCK_STS_MASK 0x0100 /* SRC2_LOCK_STS */
4414
#define WM8994_SRC2_LOCK_STS_SHIFT 8 /* SRC2_LOCK_STS */
4415
#define WM8994_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */
4416
#define WM8994_SRC1_LOCK_STS 0x0080 /* SRC1_LOCK_STS */
4417
#define WM8994_SRC1_LOCK_STS_MASK 0x0080 /* SRC1_LOCK_STS */
4418
#define WM8994_SRC1_LOCK_STS_SHIFT 7 /* SRC1_LOCK_STS */
4419
#define WM8994_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */
4420
#define WM8994_FLL2_LOCK_STS 0x0040 /* FLL2_LOCK_STS */
4421
#define WM8994_FLL2_LOCK_STS_MASK 0x0040 /* FLL2_LOCK_STS */
4422
#define WM8994_FLL2_LOCK_STS_SHIFT 6 /* FLL2_LOCK_STS */
4423
#define WM8994_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
4424
#define WM8994_FLL1_LOCK_STS 0x0020 /* FLL1_LOCK_STS */
4425
#define WM8994_FLL1_LOCK_STS_MASK 0x0020 /* FLL1_LOCK_STS */
4426
#define WM8994_FLL1_LOCK_STS_SHIFT 5 /* FLL1_LOCK_STS */
4427
#define WM8994_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
4428
#define WM8994_MIC2_SHRT_STS 0x0010 /* MIC2_SHRT_STS */
4429
#define WM8994_MIC2_SHRT_STS_MASK 0x0010 /* MIC2_SHRT_STS */
4430
#define WM8994_MIC2_SHRT_STS_SHIFT 4 /* MIC2_SHRT_STS */
4431
#define WM8994_MIC2_SHRT_STS_WIDTH 1 /* MIC2_SHRT_STS */
4432
#define WM8994_MIC2_DET_STS 0x0008 /* MIC2_DET_STS */
4433
#define WM8994_MIC2_DET_STS_MASK 0x0008 /* MIC2_DET_STS */
4434
#define WM8994_MIC2_DET_STS_SHIFT 3 /* MIC2_DET_STS */
4435
#define WM8994_MIC2_DET_STS_WIDTH 1 /* MIC2_DET_STS */
4436
#define WM8994_MIC1_SHRT_STS 0x0004 /* MIC1_SHRT_STS */
4437
#define WM8994_MIC1_SHRT_STS_MASK 0x0004 /* MIC1_SHRT_STS */
4438
#define WM8994_MIC1_SHRT_STS_SHIFT 2 /* MIC1_SHRT_STS */
4439
#define WM8994_MIC1_SHRT_STS_WIDTH 1 /* MIC1_SHRT_STS */
4440
#define WM8994_MIC1_DET_STS 0x0002 /* MIC1_DET_STS */
4441
#define WM8994_MIC1_DET_STS_MASK 0x0002 /* MIC1_DET_STS */
4442
#define WM8994_MIC1_DET_STS_SHIFT 1 /* MIC1_DET_STS */
4443
#define WM8994_MIC1_DET_STS_WIDTH 1 /* MIC1_DET_STS */
4444
#define WM8994_TEMP_SHUT_STS 0x0001 /* TEMP_SHUT_STS */
4445
#define WM8994_TEMP_SHUT_STS_MASK 0x0001 /* TEMP_SHUT_STS */
4446
#define WM8994_TEMP_SHUT_STS_SHIFT 0 /* TEMP_SHUT_STS */
4447
#define WM8994_TEMP_SHUT_STS_WIDTH 1 /* TEMP_SHUT_STS */
4450
* R1848 (0x738) - Interrupt Status 1 Mask
4452
#define WM8994_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
4453
#define WM8994_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
4454
#define WM8994_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
4455
#define WM8994_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
4456
#define WM8994_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
4457
#define WM8994_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
4458
#define WM8994_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
4459
#define WM8994_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
4460
#define WM8994_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
4461
#define WM8994_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
4462
#define WM8994_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
4463
#define WM8994_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
4464
#define WM8994_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
4465
#define WM8994_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
4466
#define WM8994_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
4467
#define WM8994_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
4468
#define WM8994_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
4469
#define WM8994_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
4470
#define WM8994_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
4471
#define WM8994_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
4472
#define WM8994_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
4473
#define WM8994_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
4474
#define WM8994_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
4475
#define WM8994_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
4476
#define WM8994_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
4477
#define WM8994_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
4478
#define WM8994_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
4479
#define WM8994_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
4480
#define WM8994_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
4481
#define WM8994_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
4482
#define WM8994_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
4483
#define WM8994_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
4484
#define WM8994_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
4485
#define WM8994_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
4486
#define WM8994_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
4487
#define WM8994_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
4488
#define WM8994_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
4489
#define WM8994_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
4490
#define WM8994_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
4491
#define WM8994_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
4492
#define WM8994_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
4493
#define WM8994_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
4494
#define WM8994_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
4495
#define WM8994_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
4498
* R1849 (0x739) - Interrupt Status 2 Mask
4500
#define WM8994_IM_TEMP_WARN_EINT 0x8000 /* IM_TEMP_WARN_EINT */
4501
#define WM8994_IM_TEMP_WARN_EINT_MASK 0x8000 /* IM_TEMP_WARN_EINT */
4502
#define WM8994_IM_TEMP_WARN_EINT_SHIFT 15 /* IM_TEMP_WARN_EINT */
4503
#define WM8994_IM_TEMP_WARN_EINT_WIDTH 1 /* IM_TEMP_WARN_EINT */
4504
#define WM8994_IM_DCS_DONE_EINT 0x4000 /* IM_DCS_DONE_EINT */
4505
#define WM8994_IM_DCS_DONE_EINT_MASK 0x4000 /* IM_DCS_DONE_EINT */
4506
#define WM8994_IM_DCS_DONE_EINT_SHIFT 14 /* IM_DCS_DONE_EINT */
4507
#define WM8994_IM_DCS_DONE_EINT_WIDTH 1 /* IM_DCS_DONE_EINT */
4508
#define WM8994_IM_WSEQ_DONE_EINT 0x2000 /* IM_WSEQ_DONE_EINT */
4509
#define WM8994_IM_WSEQ_DONE_EINT_MASK 0x2000 /* IM_WSEQ_DONE_EINT */
4510
#define WM8994_IM_WSEQ_DONE_EINT_SHIFT 13 /* IM_WSEQ_DONE_EINT */
4511
#define WM8994_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
4512
#define WM8994_IM_FIFOS_ERR_EINT 0x1000 /* IM_FIFOS_ERR_EINT */
4513
#define WM8994_IM_FIFOS_ERR_EINT_MASK 0x1000 /* IM_FIFOS_ERR_EINT */
4514
#define WM8994_IM_FIFOS_ERR_EINT_SHIFT 12 /* IM_FIFOS_ERR_EINT */
4515
#define WM8994_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
4516
#define WM8994_IM_AIF2DRC_SIG_DET_EINT 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */
4517
#define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */
4518
#define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* IM_AIF2DRC_SIG_DET_EINT */
4519
#define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */
4520
#define WM8994_IM_AIF1DRC2_SIG_DET_EINT 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */
4521
#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */
4522
#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* IM_AIF1DRC2_SIG_DET_EINT */
4523
#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */
4524
#define WM8994_IM_AIF1DRC1_SIG_DET_EINT 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */
4525
#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */
4526
#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* IM_AIF1DRC1_SIG_DET_EINT */
4527
#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */
4528
#define WM8994_IM_SRC2_LOCK_EINT 0x0100 /* IM_SRC2_LOCK_EINT */
4529
#define WM8994_IM_SRC2_LOCK_EINT_MASK 0x0100 /* IM_SRC2_LOCK_EINT */
4530
#define WM8994_IM_SRC2_LOCK_EINT_SHIFT 8 /* IM_SRC2_LOCK_EINT */
4531
#define WM8994_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */
4532
#define WM8994_IM_SRC1_LOCK_EINT 0x0080 /* IM_SRC1_LOCK_EINT */
4533
#define WM8994_IM_SRC1_LOCK_EINT_MASK 0x0080 /* IM_SRC1_LOCK_EINT */
4534
#define WM8994_IM_SRC1_LOCK_EINT_SHIFT 7 /* IM_SRC1_LOCK_EINT */
4535
#define WM8994_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */
4536
#define WM8994_IM_FLL2_LOCK_EINT 0x0040 /* IM_FLL2_LOCK_EINT */
4537
#define WM8994_IM_FLL2_LOCK_EINT_MASK 0x0040 /* IM_FLL2_LOCK_EINT */
4538
#define WM8994_IM_FLL2_LOCK_EINT_SHIFT 6 /* IM_FLL2_LOCK_EINT */
4539
#define WM8994_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
4540
#define WM8994_IM_FLL1_LOCK_EINT 0x0020 /* IM_FLL1_LOCK_EINT */
4541
#define WM8994_IM_FLL1_LOCK_EINT_MASK 0x0020 /* IM_FLL1_LOCK_EINT */
4542
#define WM8994_IM_FLL1_LOCK_EINT_SHIFT 5 /* IM_FLL1_LOCK_EINT */
4543
#define WM8994_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
4544
#define WM8994_IM_MIC2_SHRT_EINT 0x0010 /* IM_MIC2_SHRT_EINT */
4545
#define WM8994_IM_MIC2_SHRT_EINT_MASK 0x0010 /* IM_MIC2_SHRT_EINT */
4546
#define WM8994_IM_MIC2_SHRT_EINT_SHIFT 4 /* IM_MIC2_SHRT_EINT */
4547
#define WM8994_IM_MIC2_SHRT_EINT_WIDTH 1 /* IM_MIC2_SHRT_EINT */
4548
#define WM8994_IM_MIC2_DET_EINT 0x0008 /* IM_MIC2_DET_EINT */
4549
#define WM8994_IM_MIC2_DET_EINT_MASK 0x0008 /* IM_MIC2_DET_EINT */
4550
#define WM8994_IM_MIC2_DET_EINT_SHIFT 3 /* IM_MIC2_DET_EINT */
4551
#define WM8994_IM_MIC2_DET_EINT_WIDTH 1 /* IM_MIC2_DET_EINT */
4552
#define WM8994_IM_MIC1_SHRT_EINT 0x0004 /* IM_MIC1_SHRT_EINT */
4553
#define WM8994_IM_MIC1_SHRT_EINT_MASK 0x0004 /* IM_MIC1_SHRT_EINT */
4554
#define WM8994_IM_MIC1_SHRT_EINT_SHIFT 2 /* IM_MIC1_SHRT_EINT */
4555
#define WM8994_IM_MIC1_SHRT_EINT_WIDTH 1 /* IM_MIC1_SHRT_EINT */
4556
#define WM8994_IM_MIC1_DET_EINT 0x0002 /* IM_MIC1_DET_EINT */
4557
#define WM8994_IM_MIC1_DET_EINT_MASK 0x0002 /* IM_MIC1_DET_EINT */
4558
#define WM8994_IM_MIC1_DET_EINT_SHIFT 1 /* IM_MIC1_DET_EINT */
4559
#define WM8994_IM_MIC1_DET_EINT_WIDTH 1 /* IM_MIC1_DET_EINT */
4560
#define WM8994_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */
4561
#define WM8994_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */
4562
#define WM8994_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */
4563
#define WM8994_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */
4566
* R1856 (0x740) - Interrupt Control
4568
#define WM8994_IM_IRQ 0x0001 /* IM_IRQ */
4569
#define WM8994_IM_IRQ_MASK 0x0001 /* IM_IRQ */
4570
#define WM8994_IM_IRQ_SHIFT 0 /* IM_IRQ */
4571
#define WM8994_IM_IRQ_WIDTH 1 /* IM_IRQ */
4574
* R1864 (0x748) - IRQ Debounce
4576
#define WM8994_TEMP_WARN_DB 0x0020 /* TEMP_WARN_DB */
4577
#define WM8994_TEMP_WARN_DB_MASK 0x0020 /* TEMP_WARN_DB */
4578
#define WM8994_TEMP_WARN_DB_SHIFT 5 /* TEMP_WARN_DB */
4579
#define WM8994_TEMP_WARN_DB_WIDTH 1 /* TEMP_WARN_DB */
4580
#define WM8994_MIC2_SHRT_DB 0x0010 /* MIC2_SHRT_DB */
4581
#define WM8994_MIC2_SHRT_DB_MASK 0x0010 /* MIC2_SHRT_DB */
4582
#define WM8994_MIC2_SHRT_DB_SHIFT 4 /* MIC2_SHRT_DB */
4583
#define WM8994_MIC2_SHRT_DB_WIDTH 1 /* MIC2_SHRT_DB */
4584
#define WM8994_MIC2_DET_DB 0x0008 /* MIC2_DET_DB */
4585
#define WM8994_MIC2_DET_DB_MASK 0x0008 /* MIC2_DET_DB */
4586
#define WM8994_MIC2_DET_DB_SHIFT 3 /* MIC2_DET_DB */
4587
#define WM8994_MIC2_DET_DB_WIDTH 1 /* MIC2_DET_DB */
4588
#define WM8994_MIC1_SHRT_DB 0x0004 /* MIC1_SHRT_DB */
4589
#define WM8994_MIC1_SHRT_DB_MASK 0x0004 /* MIC1_SHRT_DB */
4590
#define WM8994_MIC1_SHRT_DB_SHIFT 2 /* MIC1_SHRT_DB */
4591
#define WM8994_MIC1_SHRT_DB_WIDTH 1 /* MIC1_SHRT_DB */
4592
#define WM8994_MIC1_DET_DB 0x0002 /* MIC1_DET_DB */
4593
#define WM8994_MIC1_DET_DB_MASK 0x0002 /* MIC1_DET_DB */
4594
#define WM8994_MIC1_DET_DB_SHIFT 1 /* MIC1_DET_DB */
4595
#define WM8994_MIC1_DET_DB_WIDTH 1 /* MIC1_DET_DB */
4596
#define WM8994_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */
4597
#define WM8994_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */
4598
#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */
4599
#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */
4602
* R2304 (0x900) - DSP2_Program
4604
#define WM8958_DSP2_ENA 0x0001 /* DSP2_ENA */
4605
#define WM8958_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */
4606
#define WM8958_DSP2_ENA_SHIFT 0 /* DSP2_ENA */
4607
#define WM8958_DSP2_ENA_WIDTH 1 /* DSP2_ENA */
4610
* R2305 (0x901) - DSP2_Config
4612
#define WM8958_MBC_SEL_MASK 0x0030 /* MBC_SEL - [5:4] */
4613
#define WM8958_MBC_SEL_SHIFT 4 /* MBC_SEL - [5:4] */
4614
#define WM8958_MBC_SEL_WIDTH 2 /* MBC_SEL - [5:4] */
4615
#define WM8958_MBC_ENA 0x0001 /* MBC_ENA */
4616
#define WM8958_MBC_ENA_MASK 0x0001 /* MBC_ENA */
4617
#define WM8958_MBC_ENA_SHIFT 0 /* MBC_ENA */
4618
#define WM8958_MBC_ENA_WIDTH 1 /* MBC_ENA */
4621
* R2560 (0xA00) - DSP2_MagicNum
4623
#define WM8958_DSP2_MAGIC_NUM_MASK 0xFFFF /* DSP2_MAGIC_NUM - [15:0] */
4624
#define WM8958_DSP2_MAGIC_NUM_SHIFT 0 /* DSP2_MAGIC_NUM - [15:0] */
4625
#define WM8958_DSP2_MAGIC_NUM_WIDTH 16 /* DSP2_MAGIC_NUM - [15:0] */
4628
* R2561 (0xA01) - DSP2_ReleaseYear
4630
#define WM8958_DSP2_RELEASE_YEAR_MASK 0xFFFF /* DSP2_RELEASE_YEAR - [15:0] */
4631
#define WM8958_DSP2_RELEASE_YEAR_SHIFT 0 /* DSP2_RELEASE_YEAR - [15:0] */
4632
#define WM8958_DSP2_RELEASE_YEAR_WIDTH 16 /* DSP2_RELEASE_YEAR - [15:0] */
4635
* R2562 (0xA02) - DSP2_ReleaseMonthDay
4637
#define WM8958_DSP2_RELEASE_MONTH_MASK 0xFF00 /* DSP2_RELEASE_MONTH - [15:8] */
4638
#define WM8958_DSP2_RELEASE_MONTH_SHIFT 8 /* DSP2_RELEASE_MONTH - [15:8] */
4639
#define WM8958_DSP2_RELEASE_MONTH_WIDTH 8 /* DSP2_RELEASE_MONTH - [15:8] */
4640
#define WM8958_DSP2_RELEASE_DAY_MASK 0x00FF /* DSP2_RELEASE_DAY - [7:0] */
4641
#define WM8958_DSP2_RELEASE_DAY_SHIFT 0 /* DSP2_RELEASE_DAY - [7:0] */
4642
#define WM8958_DSP2_RELEASE_DAY_WIDTH 8 /* DSP2_RELEASE_DAY - [7:0] */
4645
* R2563 (0xA03) - DSP2_ReleaseTime
4647
#define WM8958_DSP2_RELEASE_HOURS_MASK 0xFF00 /* DSP2_RELEASE_HOURS - [15:8] */
4648
#define WM8958_DSP2_RELEASE_HOURS_SHIFT 8 /* DSP2_RELEASE_HOURS - [15:8] */
4649
#define WM8958_DSP2_RELEASE_HOURS_WIDTH 8 /* DSP2_RELEASE_HOURS - [15:8] */
4650
#define WM8958_DSP2_RELEASE_MINS_MASK 0x00FF /* DSP2_RELEASE_MINS - [7:0] */
4651
#define WM8958_DSP2_RELEASE_MINS_SHIFT 0 /* DSP2_RELEASE_MINS - [7:0] */
4652
#define WM8958_DSP2_RELEASE_MINS_WIDTH 8 /* DSP2_RELEASE_MINS - [7:0] */
4655
* R2564 (0xA04) - DSP2_VerMajMin
4657
#define WM8958_DSP2_MAJOR_VER_MASK 0xFF00 /* DSP2_MAJOR_VER - [15:8] */
4658
#define WM8958_DSP2_MAJOR_VER_SHIFT 8 /* DSP2_MAJOR_VER - [15:8] */
4659
#define WM8958_DSP2_MAJOR_VER_WIDTH 8 /* DSP2_MAJOR_VER - [15:8] */
4660
#define WM8958_DSP2_MINOR_VER_MASK 0x00FF /* DSP2_MINOR_VER - [7:0] */
4661
#define WM8958_DSP2_MINOR_VER_SHIFT 0 /* DSP2_MINOR_VER - [7:0] */
4662
#define WM8958_DSP2_MINOR_VER_WIDTH 8 /* DSP2_MINOR_VER - [7:0] */
4665
* R2565 (0xA05) - DSP2_VerBuild
4667
#define WM8958_DSP2_BUILD_VER_MASK 0xFFFF /* DSP2_BUILD_VER - [15:0] */
4668
#define WM8958_DSP2_BUILD_VER_SHIFT 0 /* DSP2_BUILD_VER - [15:0] */
4669
#define WM8958_DSP2_BUILD_VER_WIDTH 16 /* DSP2_BUILD_VER - [15:0] */
4672
* R2573 (0xA0D) - DSP2_ExecControl
4674
#define WM8958_DSP2_STOPC 0x0020 /* DSP2_STOPC */
4675
#define WM8958_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */
4676
#define WM8958_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */
4677
#define WM8958_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */
4678
#define WM8958_DSP2_STOPS 0x0010 /* DSP2_STOPS */
4679
#define WM8958_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */
4680
#define WM8958_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */
4681
#define WM8958_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */
4682
#define WM8958_DSP2_STOPI 0x0008 /* DSP2_STOPI */
4683
#define WM8958_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */
4684
#define WM8958_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */
4685
#define WM8958_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */
4686
#define WM8958_DSP2_STOP 0x0004 /* DSP2_STOP */
4687
#define WM8958_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */
4688
#define WM8958_DSP2_STOP_SHIFT 2 /* DSP2_STOP */
4689
#define WM8958_DSP2_STOP_WIDTH 1 /* DSP2_STOP */
4690
#define WM8958_DSP2_RUNR 0x0002 /* DSP2_RUNR */
4691
#define WM8958_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */
4692
#define WM8958_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */
4693
#define WM8958_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */
4694
#define WM8958_DSP2_RUN 0x0001 /* DSP2_RUN */
4695
#define WM8958_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */
4696
#define WM8958_DSP2_RUN_SHIFT 0 /* DSP2_RUN */
4697
#define WM8958_DSP2_RUN_WIDTH 1 /* DSP2_RUN */
added
removed
include/linux/mfd/wm8994/registers.h
