2
* arch/ia64/kvm/vmm_ivt.S
4
* Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5
* Stephane Eranian <eranian@hpl.hp.com>
6
* David Mosberger <davidm@hpl.hp.com>
7
* Copyright (C) 2000, 2002-2003 Intel Co
8
* Asit Mallick <asit.k.mallick@intel.com>
9
* Suresh Siddha <suresh.b.siddha@intel.com>
10
* Kenneth Chen <kenneth.w.chen@intel.com>
11
* Fenghua Yu <fenghua.yu@intel.com>
14
* 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling
16
* 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB
17
* handler now uses virtual PT.
19
* 07/6/20 Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
20
* Supporting Intel virtualization architecture
25
* This file defines the interruption vector table used by the CPU.
26
* It does not include one entry per possible cause of interruption.
28
* The first 20 entries of the table contain 64 bundles each while the
29
* remaining 48 entries contain only 16 bundles each.
31
* The 64 bundles are used to allow inlining the whole handler for
33
* interruptions like TLB misses.
35
* For each entry, the comment is as follows:
37
* // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss
39
* entry offset ----/ / / /
41
* entry number ---------/ / /
43
* size of the entry -------------/ /
45
* vector name -------------------------------------/
47
* interruptions triggering this vector
48
* ----------------------/
50
* The table is 32KB in size and must be aligned on 32KB
52
* (The CPU ignores the 15 lower bits of the address)
54
* Table is based upon EAS2.6 (Oct 1999)
58
#include <asm/asmmacro.h>
59
#include <asm/cache.h>
60
#include <asm/pgtable.h>
62
#include "asm-offsets.h"
64
#include "kvm_minstate.h"
68
# define PSR_DEFAULT_BITS psr.ac
70
# define PSR_DEFAULT_BITS 0
73
#define KVM_FAULT(n) \
76
br.sptk.many kvm_vmm_panic; \
79
#define KVM_REFLECT(n) \
81
mov r19=n; /* prepare to save predicates */ \
84
tbit.z p6,p7=r29,IA64_PSR_VM_BIT; \
85
(p7) br.sptk.many kvm_dispatch_reflection; \
86
br.sptk.many kvm_vmm_panic; \
88
GLOBAL_ENTRY(kvm_vmm_panic)
89
KVM_SAVE_MIN_WITH_COVER_R19
90
alloc r14=ar.pfs,0,0,1,0
92
adds r3=8,r2 // set up second base pointer
96
srlz.i // guarantee that interruption collection is on
98
(p15) ssm psr.i // restore psr.
99
addl r14=@gprel(ia64_leave_hypervisor),gp
104
br.call.sptk.many b6=vmm_panic_handler;
107
.section .text..ivt,"ax"
109
.align 32768 // align on 32KB boundary
112
///////////////////////////////////////////////////////////////
113
// 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
118
.org kvm_ia64_ivt+0x400
119
////////////////////////////////////////////////////////////////
120
// 0x0400 Entry 1 (size 64 bundles) ITLB (21)
125
tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
126
(p6) br.sptk kvm_alt_itlb_miss
128
br.sptk kvm_itlb_miss_dispatch
132
.org kvm_ia64_ivt+0x0800
133
//////////////////////////////////////////////////////////////////
134
// 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
139
tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
140
(p6) br.sptk kvm_alt_dtlb_miss
141
br.sptk kvm_dtlb_miss_dispatch
144
.org kvm_ia64_ivt+0x0c00
145
////////////////////////////////////////////////////////////////////
146
// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
147
ENTRY(kvm_alt_itlb_miss)
148
mov r16=cr.ifa // get address that caused the TLB miss
152
movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
154
and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
156
or r19=r17,r19 // insert PTE control bits into r19
158
movl r20=IA64_GRANULE_SHIFT<<2
162
itc.i r19 // insert the TLB entry
165
END(kvm_alt_itlb_miss)
167
.org kvm_ia64_ivt+0x1000
168
/////////////////////////////////////////////////////////////////////
169
// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
170
ENTRY(kvm_alt_dtlb_miss)
171
mov r16=cr.ifa // get address that caused the TLB miss
174
movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
177
and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
179
or r19=r19,r17 // insert PTE control bits into r19
181
movl r20=IA64_GRANULE_SHIFT<<2
185
itc.d r19 // insert the TLB entry
188
END(kvm_alt_dtlb_miss)
190
.org kvm_ia64_ivt+0x1400
191
//////////////////////////////////////////////////////////////////////
192
// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
193
ENTRY(kvm_nested_dtlb_miss)
195
END(kvm_nested_dtlb_miss)
197
.org kvm_ia64_ivt+0x1800
198
/////////////////////////////////////////////////////////////////////
199
// 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
204
.org kvm_ia64_ivt+0x1c00
205
/////////////////////////////////////////////////////////////////////
206
// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
211
.org kvm_ia64_ivt+0x2000
212
////////////////////////////////////////////////////////////////////
213
// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
218
.org kvm_ia64_ivt+0x2400
219
////////////////////////////////////////////////////////////////////
220
// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
221
ENTRY(kvm_iaccess_bit)
225
.org kvm_ia64_ivt+0x2800
226
///////////////////////////////////////////////////////////////////
227
// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
228
ENTRY(kvm_daccess_bit)
232
.org kvm_ia64_ivt+0x2c00
233
/////////////////////////////////////////////////////////////////
234
// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
235
ENTRY(kvm_break_fault)
240
KVM_SAVE_MIN_WITH_COVER_R19
242
alloc r14=ar.pfs,0,0,4,0 //(must be first in insn group!)
244
mov out2=cr.isr // FIXME: pity to make this slow access twice
245
mov out3=cr.iim // FIXME: pity to make this slow access twice
246
adds r3=8,r2 // set up second base pointer
250
srlz.i // guarantee that interruption collection is on
252
(p15)ssm psr.i // restore psr.i
253
addl r14=@gprel(ia64_leave_hypervisor),gp
259
br.call.sptk.many b6=kvm_ia64_handle_break
263
.org kvm_ia64_ivt+0x3000
264
/////////////////////////////////////////////////////////////////
265
// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
267
mov r31=pr // prepare to save predicates
271
tbit.z p6,p7=r29,IA64_PSR_VM_BIT
272
tbit.z p0,p15=r29,IA64_PSR_I_BIT
274
(p7) br.sptk kvm_dispatch_interrupt
276
mov r27=ar.rsc /* M */
278
mov r25=ar.unat /* M */
279
mov r26=ar.pfs /* I */
280
mov r28=cr.iip /* M */
281
cover /* B (or nothing) */
288
addl r1=-VMM_PT_REGS_SIZE,r1
290
adds r17=2*L1_CACHE_BYTES,r1 /* really: biggest cache-line size */
291
adds r16=PT(CR_IPSR),r1
293
lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES
294
st8 [r16]=r29 /* save cr.ipsr */
296
lfetch.fault.excl.nt1 [r17]
299
adds r16=PT(R8),r1 /* initialize first base pointer */
300
adds r17=PT(R9),r1 /* initialize second base pointer */
301
mov r18=r0 /* make sure r18 isn't NaT */
303
.mem.offset 0,0; st8.spill [r16]=r8,16
304
.mem.offset 8,0; st8.spill [r17]=r9,16
306
.mem.offset 0,0; st8.spill [r16]=r10,24
307
.mem.offset 8,0; st8.spill [r17]=r11,24
309
st8 [r16]=r28,16 /* save cr.iip */
310
st8 [r17]=r30,16 /* save cr.ifs */
311
mov r8=ar.fpsr /* M */
314
movl r11=FPSR_DEFAULT /* L-unit */
316
st8 [r16]=r25,16 /* save ar.unat */
317
st8 [r17]=r26,16 /* save ar.pfs */
318
shl r18=r18,16 /* compute ar.rsc to be used for "loadrs" */
320
st8 [r16]=r27,16 /* save ar.rsc */
321
adds r17=16,r17 /* skip over ar_rnat field */
323
st8 [r17]=r31,16 /* save predicates */
324
adds r16=16,r16 /* skip over ar_bspstore field */
326
st8 [r16]=r29,16 /* save b0 */
327
st8 [r17]=r18,16 /* save ar.rsc value for "loadrs" */
329
.mem.offset 0,0; st8.spill [r16]=r20,16 /* save original r1 */
330
.mem.offset 8,0; st8.spill [r17]=r12,16
332
/* switch to kernel memory stack (with 16 bytes of scratch) */
334
.mem.offset 0,0; st8.spill [r16]=r13,16
335
.mem.offset 8,0; st8.spill [r17]=r8,16 /* save ar.fpsr */
337
.mem.offset 0,0; st8.spill [r16]=r15,16
338
.mem.offset 8,0; st8.spill [r17]=r14,16
341
.mem.offset 0,0; st8.spill [r16]=r2,16
342
.mem.offset 8,0; st8.spill [r17]=r3,16
343
adds r2=VMM_PT_REGS_R16_OFFSET,r1
344
adds r14 = VMM_VCPU_GP_OFFSET,r13
349
mov r1=r14 /* establish kernel global pointer */
353
alloc r14=ar.pfs,0,0,1,0 // must be first in an insn group
361
adds r3=8,r2 // set up second base pointer for SAVE_REST
362
srlz.i // ensure everybody knows psr.ic is back on
364
.mem.offset 0,0; st8.spill [r2]=r16,16
365
.mem.offset 8,0; st8.spill [r3]=r17,16
367
.mem.offset 0,0; st8.spill [r2]=r18,16
368
.mem.offset 8,0; st8.spill [r3]=r19,16
370
.mem.offset 0,0; st8.spill [r2]=r20,16
371
.mem.offset 8,0; st8.spill [r3]=r21,16
374
.mem.offset 0,0; st8.spill [r2]=r22,16
375
.mem.offset 8,0; st8.spill [r3]=r23,16
378
.mem.offset 0,0; st8.spill [r2]=r24,16
379
.mem.offset 8,0; st8.spill [r3]=r25,16
381
.mem.offset 0,0; st8.spill [r2]=r26,16
382
.mem.offset 8,0; st8.spill [r3]=r27,16
384
.mem.offset 0,0; st8.spill [r2]=r28,16
385
.mem.offset 8,0; st8.spill [r3]=r29,16
387
.mem.offset 0,0; st8.spill [r2]=r30,16
388
.mem.offset 8,0; st8.spill [r3]=r31,32
390
mov ar.fpsr=r11 /* M-unit */
391
st8 [r2]=r8,8 /* ar.ccv */
392
adds r24=PT(B6)-PT(F7),r3
402
adds r25=PT(B7)-PT(F11),r3
404
st8 [r24]=r18,16 /* b6 */
405
st8 [r25]=r19,16 /* b7 */
407
st8 [r24]=r9 /* ar.csd */
408
st8 [r25]=r10 /* ar.ssd */
410
srlz.d // make sure we see the effect of cr.ivr
411
addl r14=@gprel(ia64_leave_nested),gp
414
br.call.sptk.many b6=kvm_ia64_handle_irq
418
.global kvm_dispatch_vexirq
419
.org kvm_ia64_ivt+0x3400
420
//////////////////////////////////////////////////////////////////////
421
// 0x3400 Entry 13 (size 64 bundles) Reserved
422
ENTRY(kvm_virtual_exirq)
430
(p6) add r29 = VMM_VCPU_SAVED_GP_OFFSET,r21
434
KVM_SAVE_MIN_WITH_COVER_R19
435
alloc r14=ar.pfs,0,0,1,0
440
srlz.i // guarantee that interruption collection is on
442
(p15) ssm psr.i // restore psr.i
443
adds r3=8,r2 // set up second base pointer
446
addl r14=@gprel(ia64_leave_hypervisor),gp
449
br.call.sptk.many b6=kvm_vexirq
450
END(kvm_virtual_exirq)
452
.org kvm_ia64_ivt+0x3800
453
/////////////////////////////////////////////////////////////////////
454
// 0x3800 Entry 14 (size 64 bundles) Reserved
456
// this code segment is from 2.6.16.13
458
.org kvm_ia64_ivt+0x3c00
459
///////////////////////////////////////////////////////////////////////
460
// 0x3c00 Entry 15 (size 64 bundles) Reserved
463
.org kvm_ia64_ivt+0x4000
464
///////////////////////////////////////////////////////////////////////
465
// 0x4000 Entry 16 (size 64 bundles) Reserved
468
.org kvm_ia64_ivt+0x4400
469
//////////////////////////////////////////////////////////////////////
470
// 0x4400 Entry 17 (size 64 bundles) Reserved
473
.org kvm_ia64_ivt+0x4800
474
//////////////////////////////////////////////////////////////////////
475
// 0x4800 Entry 18 (size 64 bundles) Reserved
478
.org kvm_ia64_ivt+0x4c00
479
//////////////////////////////////////////////////////////////////////
480
// 0x4c00 Entry 19 (size 64 bundles) Reserved
483
.org kvm_ia64_ivt+0x5000
484
//////////////////////////////////////////////////////////////////////
485
// 0x5000 Entry 20 (size 16 bundles) Page Not Present
486
ENTRY(kvm_page_not_present)
488
END(kvm_page_not_present)
490
.org kvm_ia64_ivt+0x5100
491
///////////////////////////////////////////////////////////////////////
492
// 0x5100 Entry 21 (size 16 bundles) Key Permission vector
493
ENTRY(kvm_key_permission)
495
END(kvm_key_permission)
497
.org kvm_ia64_ivt+0x5200
498
//////////////////////////////////////////////////////////////////////
499
// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
500
ENTRY(kvm_iaccess_rights)
502
END(kvm_iaccess_rights)
504
.org kvm_ia64_ivt+0x5300
505
//////////////////////////////////////////////////////////////////////
506
// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
507
ENTRY(kvm_daccess_rights)
509
END(kvm_daccess_rights)
511
.org kvm_ia64_ivt+0x5400
512
/////////////////////////////////////////////////////////////////////
513
// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
514
ENTRY(kvm_general_exception)
517
END(kvm_general_exception)
519
.org kvm_ia64_ivt+0x5500
520
//////////////////////////////////////////////////////////////////////
521
// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
522
ENTRY(kvm_disabled_fp_reg)
524
END(kvm_disabled_fp_reg)
526
.org kvm_ia64_ivt+0x5600
527
////////////////////////////////////////////////////////////////////
528
// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
529
ENTRY(kvm_nat_consumption)
531
END(kvm_nat_consumption)
533
.org kvm_ia64_ivt+0x5700
534
/////////////////////////////////////////////////////////////////////
535
// 0x5700 Entry 27 (size 16 bundles) Speculation (40)
536
ENTRY(kvm_speculation_vector)
538
END(kvm_speculation_vector)
540
.org kvm_ia64_ivt+0x5800
541
/////////////////////////////////////////////////////////////////////
542
// 0x5800 Entry 28 (size 16 bundles) Reserved
545
.org kvm_ia64_ivt+0x5900
546
///////////////////////////////////////////////////////////////////
547
// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
548
ENTRY(kvm_debug_vector)
550
END(kvm_debug_vector)
552
.org kvm_ia64_ivt+0x5a00
553
///////////////////////////////////////////////////////////////
554
// 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
555
ENTRY(kvm_unaligned_access)
557
END(kvm_unaligned_access)
559
.org kvm_ia64_ivt+0x5b00
560
//////////////////////////////////////////////////////////////////////
561
// 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
562
ENTRY(kvm_unsupported_data_reference)
564
END(kvm_unsupported_data_reference)
566
.org kvm_ia64_ivt+0x5c00
567
////////////////////////////////////////////////////////////////////
568
// 0x5c00 Entry 32 (size 16 bundles) Floating Point FAULT (65)
569
ENTRY(kvm_floating_point_fault)
571
END(kvm_floating_point_fault)
573
.org kvm_ia64_ivt+0x5d00
574
/////////////////////////////////////////////////////////////////////
575
// 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
576
ENTRY(kvm_floating_point_trap)
578
END(kvm_floating_point_trap)
580
.org kvm_ia64_ivt+0x5e00
581
//////////////////////////////////////////////////////////////////////
582
// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
583
ENTRY(kvm_lower_privilege_trap)
585
END(kvm_lower_privilege_trap)
587
.org kvm_ia64_ivt+0x5f00
588
//////////////////////////////////////////////////////////////////////
589
// 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
590
ENTRY(kvm_taken_branch_trap)
592
END(kvm_taken_branch_trap)
594
.org kvm_ia64_ivt+0x6000
595
////////////////////////////////////////////////////////////////////
596
// 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
597
ENTRY(kvm_single_step_trap)
599
END(kvm_single_step_trap)
600
.global kvm_virtualization_fault_back
601
.org kvm_ia64_ivt+0x6100
602
/////////////////////////////////////////////////////////////////////
603
// 0x6100 Entry 37 (size 16 bundles) Virtualization Fault
604
ENTRY(kvm_virtualization_fault)
606
adds r16 = VMM_VCPU_SAVED_GP_OFFSET,r21
609
adds r17 = VMM_VCPU_GP_OFFSET, r21
612
cmp.eq p6,p0=EVENT_MOV_FROM_AR,r24
613
cmp.eq p7,p0=EVENT_MOV_FROM_RR,r24
614
cmp.eq p8,p0=EVENT_MOV_TO_RR,r24
615
cmp.eq p9,p0=EVENT_RSM,r24
616
cmp.eq p10,p0=EVENT_SSM,r24
617
cmp.eq p11,p0=EVENT_MOV_TO_PSR,r24
618
cmp.eq p12,p0=EVENT_THASH,r24
619
(p6) br.dptk.many kvm_asm_mov_from_ar
620
(p7) br.dptk.many kvm_asm_mov_from_rr
621
(p8) br.dptk.many kvm_asm_mov_to_rr
622
(p9) br.dptk.many kvm_asm_rsm
623
(p10) br.dptk.many kvm_asm_ssm
624
(p11) br.dptk.many kvm_asm_mov_to_psr
625
(p12) br.dptk.many kvm_asm_thash
627
kvm_virtualization_fault_back:
628
adds r16 = VMM_VCPU_SAVED_GP_OFFSET,r21
633
adds r16 = VMM_VCPU_CAUSE_OFFSET,r21
634
adds r17 = VMM_VCPU_OPCODE_OFFSET,r21
639
cmp.ne p6,p0=EVENT_RFI, r24
640
(p6) br.sptk kvm_dispatch_virtualization_fault
642
adds r18=VMM_VPD_BASE_OFFSET,r21
646
adds r18=VMM_VPD_VIFS_OFFSET,r18
651
(p6) br.sptk kvm_dispatch_virtualization_fault
653
//if vifs.v=1 desert current register frame
654
alloc r18=ar.pfs,0,0,0,0
655
br.sptk kvm_dispatch_virtualization_fault
656
END(kvm_virtualization_fault)
658
.org kvm_ia64_ivt+0x6200
659
//////////////////////////////////////////////////////////////
660
// 0x6200 Entry 38 (size 16 bundles) Reserved
663
.org kvm_ia64_ivt+0x6300
664
/////////////////////////////////////////////////////////////////
665
// 0x6300 Entry 39 (size 16 bundles) Reserved
668
.org kvm_ia64_ivt+0x6400
669
/////////////////////////////////////////////////////////////////
670
// 0x6400 Entry 40 (size 16 bundles) Reserved
673
.org kvm_ia64_ivt+0x6500
674
//////////////////////////////////////////////////////////////////
675
// 0x6500 Entry 41 (size 16 bundles) Reserved
678
.org kvm_ia64_ivt+0x6600
679
//////////////////////////////////////////////////////////////////
680
// 0x6600 Entry 42 (size 16 bundles) Reserved
683
.org kvm_ia64_ivt+0x6700
684
//////////////////////////////////////////////////////////////////
685
// 0x6700 Entry 43 (size 16 bundles) Reserved
688
.org kvm_ia64_ivt+0x6800
689
//////////////////////////////////////////////////////////////////
690
// 0x6800 Entry 44 (size 16 bundles) Reserved
693
.org kvm_ia64_ivt+0x6900
694
///////////////////////////////////////////////////////////////////
695
// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception
696
//(17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
697
ENTRY(kvm_ia32_exception)
699
END(kvm_ia32_exception)
701
.org kvm_ia64_ivt+0x6a00
702
////////////////////////////////////////////////////////////////////
703
// 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
704
ENTRY(kvm_ia32_intercept)
706
END(kvm_ia32_intercept)
708
.org kvm_ia64_ivt+0x6c00
709
/////////////////////////////////////////////////////////////////////
710
// 0x6c00 Entry 48 (size 16 bundles) Reserved
713
.org kvm_ia64_ivt+0x6d00
714
//////////////////////////////////////////////////////////////////////
715
// 0x6d00 Entry 49 (size 16 bundles) Reserved
718
.org kvm_ia64_ivt+0x6e00
719
//////////////////////////////////////////////////////////////////////
720
// 0x6e00 Entry 50 (size 16 bundles) Reserved
723
.org kvm_ia64_ivt+0x6f00
724
/////////////////////////////////////////////////////////////////////
725
// 0x6f00 Entry 51 (size 16 bundles) Reserved
728
.org kvm_ia64_ivt+0x7100
729
////////////////////////////////////////////////////////////////////
730
// 0x7100 Entry 53 (size 16 bundles) Reserved
733
.org kvm_ia64_ivt+0x7200
734
/////////////////////////////////////////////////////////////////////
735
// 0x7200 Entry 54 (size 16 bundles) Reserved
738
.org kvm_ia64_ivt+0x7300
739
////////////////////////////////////////////////////////////////////
740
// 0x7300 Entry 55 (size 16 bundles) Reserved
743
.org kvm_ia64_ivt+0x7400
744
////////////////////////////////////////////////////////////////////
745
// 0x7400 Entry 56 (size 16 bundles) Reserved
748
.org kvm_ia64_ivt+0x7500
749
/////////////////////////////////////////////////////////////////////
750
// 0x7500 Entry 57 (size 16 bundles) Reserved
753
.org kvm_ia64_ivt+0x7600
754
/////////////////////////////////////////////////////////////////////
755
// 0x7600 Entry 58 (size 16 bundles) Reserved
758
.org kvm_ia64_ivt+0x7700
759
////////////////////////////////////////////////////////////////////
760
// 0x7700 Entry 59 (size 16 bundles) Reserved
763
.org kvm_ia64_ivt+0x7800
764
////////////////////////////////////////////////////////////////////
765
// 0x7800 Entry 60 (size 16 bundles) Reserved
768
.org kvm_ia64_ivt+0x7900
769
/////////////////////////////////////////////////////////////////////
770
// 0x7900 Entry 61 (size 16 bundles) Reserved
773
.org kvm_ia64_ivt+0x7a00
774
/////////////////////////////////////////////////////////////////////
775
// 0x7a00 Entry 62 (size 16 bundles) Reserved
778
.org kvm_ia64_ivt+0x7b00
779
/////////////////////////////////////////////////////////////////////
780
// 0x7b00 Entry 63 (size 16 bundles) Reserved
783
.org kvm_ia64_ivt+0x7c00
784
////////////////////////////////////////////////////////////////////
785
// 0x7c00 Entry 64 (size 16 bundles) Reserved
788
.org kvm_ia64_ivt+0x7d00
789
/////////////////////////////////////////////////////////////////////
790
// 0x7d00 Entry 65 (size 16 bundles) Reserved
793
.org kvm_ia64_ivt+0x7e00
794
/////////////////////////////////////////////////////////////////////
795
// 0x7e00 Entry 66 (size 16 bundles) Reserved
798
.org kvm_ia64_ivt+0x7f00
799
////////////////////////////////////////////////////////////////////
800
// 0x7f00 Entry 67 (size 16 bundles) Reserved
803
.org kvm_ia64_ivt+0x8000
804
// There is no particular reason for this code to be here, other than that
805
// there happens to be space here that would go unused otherwise. If this
806
// fault ever gets "unreserved", simply moved the following code to a more
810
ENTRY(kvm_dtlb_miss_dispatch)
812
KVM_SAVE_MIN_WITH_COVER_R19
813
alloc r14=ar.pfs,0,0,3,0
816
adds r3=8,r2 // set up second base pointer
820
srlz.i // guarantee that interruption collection is on
822
(p15) ssm psr.i // restore psr.i
823
addl r14=@gprel(ia64_leave_hypervisor_prepare),gp
830
br.call.sptk.many b6=kvm_page_fault
831
END(kvm_dtlb_miss_dispatch)
833
ENTRY(kvm_itlb_miss_dispatch)
835
KVM_SAVE_MIN_WITH_COVER_R19
836
alloc r14=ar.pfs,0,0,3,0
839
adds r3=8,r2 // set up second base pointer
843
srlz.i // guarantee that interruption collection is on
845
(p15) ssm psr.i // restore psr.i
846
addl r14=@gprel(ia64_leave_hypervisor),gp
852
br.call.sptk.many b6=kvm_page_fault
853
END(kvm_itlb_miss_dispatch)
855
ENTRY(kvm_dispatch_reflection)
859
* r19: intr type (offset into ivt, see ia64_int.h)
860
* r31: contains saved predicates (pr)
862
KVM_SAVE_MIN_WITH_COVER_R19
863
alloc r14=ar.pfs,0,0,5,0
868
adds r3=8,r2 // set up second base pointer
872
srlz.i // guarantee that interruption collection is on
874
(p15) ssm psr.i // restore psr.i
875
addl r14=@gprel(ia64_leave_hypervisor),gp
881
br.call.sptk.many b6=reflect_interruption
882
END(kvm_dispatch_reflection)
884
ENTRY(kvm_dispatch_virtualization_fault)
885
adds r16 = VMM_VCPU_CAUSE_OFFSET,r21
886
adds r17 = VMM_VCPU_OPCODE_OFFSET,r21
891
KVM_SAVE_MIN_WITH_COVER_R19
893
alloc r14=ar.pfs,0,0,2,0 // (must be first in insn group!)
895
adds r3=8,r2 // set up second base pointer
899
srlz.i // guarantee that interruption collection is on
901
(p15) ssm psr.i // restore psr.i
902
addl r14=@gprel(ia64_leave_hypervisor_prepare),gp
908
adds out1=16,sp //regs
909
br.call.sptk.many b6=kvm_emulate
910
END(kvm_dispatch_virtualization_fault)
913
ENTRY(kvm_dispatch_interrupt)
914
KVM_SAVE_MIN_WITH_COVER_R19 // uses r31; defines r2 and r3
916
alloc r14=ar.pfs,0,0,1,0 // must be first in an insn group
917
adds r3=8,r2 // set up second base pointer for SAVE_REST
924
addl r14=@gprel(ia64_leave_hypervisor),gp
929
mov out0=r13 // pass pointer to pt_regs as second arg
930
br.call.sptk.many b6=kvm_ia64_handle_irq
931
END(kvm_dispatch_interrupt)
933
GLOBAL_ENTRY(ia64_leave_nested)
936
adds r21=PT(PR)+16,r12
938
lfetch [r21],PT(CR_IPSR)-PT(PR)
939
adds r2=PT(B6)+16,r12
940
adds r3=PT(R16)+16,r12
943
ld8 r28=[r2],8 // load b6
944
adds r29=PT(R24)+16,r12
947
adds r3=PT(AR_CSD)-PT(R16),r3
948
adds r30=PT(AR_CCV)+16,r12
951
ld8 r15=[r30] // load ar.ccv
953
ld8 r29=[r2],16 // load b7
954
ld8 r30=[r3],16 // load ar.csd
956
ld8 r31=[r2],16 // load ar.ssd
960
ld8.fill r10=[r3],PT(R17)-PT(R10)
962
ld8.fill r11=[r2],PT(R18)-PT(R11)
974
// initiate turning off of interrupt and interruption collection
975
invala // invalidate ALAT
993
ld8.fill r31=[r2],PT(F9)-PT(R31)
994
adds r3=PT(F10)-PT(F6),r3
996
ldf.fill f9=[r2],PT(F6)-PT(F9)
997
ldf.fill f10=[r3],PT(F8)-PT(F10)
999
ldf.fill f6=[r2],PT(F7)-PT(F6)
1001
ldf.fill f7=[r2],PT(F11)-PT(F7)
1004
srlz.i // ensure interruption collection is off
1007
bsw.0 // switch back to bank 0 (no stop bit required beforehand...)
1012
adds r16=PT(CR_IPSR)+16,r12
1013
adds r17=PT(CR_IIP)+16,r12
1015
ld8 r29=[r16],16 // load cr.ipsr
1016
ld8 r28=[r17],16 // load cr.iip
1018
ld8 r30=[r16],16 // load cr.ifs
1019
ld8 r25=[r17],16 // load ar.unat
1021
ld8 r26=[r16],16 // load ar.pfs
1022
ld8 r27=[r17],16 // load ar.rsc
1024
// set p9 to indicate that we should restore cr.ifs
1026
ld8 r24=[r16],16 // load ar.rnat (may be garbage)
1027
ld8 r23=[r17],16// load ar.bspstore (may be garbage)
1029
ld8 r31=[r16],16 // load predicates
1030
ld8 r22=[r17],16 // load b0
1032
ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
1033
ld8.fill r1=[r17],16 // load r1
1035
ld8.fill r12=[r16],16
1036
ld8.fill r13=[r17],16
1038
ld8 r20=[r16],16 // ar.fpsr
1039
ld8.fill r15=[r17],16
1041
ld8.fill r14=[r16],16
1046
mov r16=ar.bsp // get existing backing store pointer
1059
END(ia64_leave_nested)
1061
GLOBAL_ENTRY(ia64_leave_hypervisor_prepare)
1063
* work.need_resched etc. mustn't get changed
1064
*by this CPU before it returns to
1065
* user- or fsys-mode, hence we disable interrupts early on:
1067
adds r2 = PT(R4)+16,r12
1068
adds r3 = PT(R5)+16,r12
1069
adds r8 = PT(EML_UNAT)+16,r12
1075
ld8.fill r4=[r2],16 //load r4
1076
ld8.fill r5=[r3],16 //load r5
1078
ld8.fill r6=[r2] //load r6
1079
ld8.fill r7=[r3] //load r7
1081
END(ia64_leave_hypervisor_prepare)
1083
GLOBAL_ENTRY(ia64_leave_hypervisor)
1086
br.call.sptk.many b0=leave_hypervisor_tail
1088
adds r20=PT(PR)+16,r12
1089
adds r8=PT(EML_UNAT)+16,r12
1095
lfetch [r20],PT(CR_IPSR)-PT(PR)
1096
adds r2 = PT(B6)+16,r12
1097
adds r3 = PT(B7)+16,r12
1101
ld8 r24=[r2],16 /* B6 */
1102
ld8 r25=[r3],16 /* B7 */
1104
ld8 r26=[r2],16 /* ar_csd */
1105
ld8 r27=[r3],16 /* ar_ssd */
1115
ld8.fill r10=[r2],PT(R15)-PT(R10)
1116
ld8.fill r11=[r3],PT(R14)-PT(R11)
1118
ld8.fill r15=[r2],PT(R16)-PT(R15)
1119
ld8.fill r14=[r3],PT(R17)-PT(R14)
1121
ld8.fill r16=[r2],16
1122
ld8.fill r17=[r3],16
1124
ld8.fill r18=[r2],16
1125
ld8.fill r19=[r3],16
1127
ld8.fill r20=[r2],16
1128
ld8.fill r21=[r3],16
1130
ld8.fill r22=[r2],16
1131
ld8.fill r23=[r3],16
1133
ld8.fill r24=[r2],16
1134
ld8.fill r25=[r3],16
1136
ld8.fill r26=[r2],16
1137
ld8.fill r27=[r3],16
1139
ld8.fill r28=[r2],16
1140
ld8.fill r29=[r3],16
1142
ld8.fill r30=[r2],PT(F6)-PT(R30)
1143
ld8.fill r31=[r3],PT(F7)-PT(R31)
1146
// initiate turning off of interrupt and interruption collection
1147
invala // invalidate ALAT
1149
srlz.i // ensure interruption collection is off
1153
adds r16 = PT(CR_IPSR)+16,r12
1154
adds r17 = PT(CR_IIP)+16,r12
1155
mov r21=r13 // get current
1157
ld8 r31=[r16],16 // load cr.ipsr
1158
ld8 r30=[r17],16 // load cr.iip
1160
ld8 r29=[r16],16 // load cr.ifs
1161
ld8 r28=[r17],16 // load ar.unat
1163
ld8 r27=[r16],16 // load ar.pfs
1164
ld8 r26=[r17],16 // load ar.rsc
1166
ld8 r25=[r16],16 // load ar.rnat
1167
ld8 r24=[r17],16 // load ar.bspstore
1169
ld8 r23=[r16],16 // load predicates
1170
ld8 r22=[r17],16 // load b0
1172
ld8 r20=[r16],16 // load ar.rsc value for "loadrs"
1173
ld8.fill r1=[r17],16 //load r1
1175
ld8.fill r12=[r16],16 //load r12
1176
ld8.fill r13=[r17],PT(R2)-PT(R13) //load r13
1178
ld8 r19=[r16],PT(R3)-PT(AR_FPSR) //load ar_fpsr
1179
ld8.fill r2=[r17],PT(AR_CCV)-PT(R2) //load r2
1181
ld8.fill r3=[r16] //load r3
1182
ld8 r18=[r17] //load ar_ccv
1191
kvm_dont_preserve_current_frame:
1193
* To prevent leaking bits between the hypervisor and guest domain,
1194
* we must clear the stacked registers in the "invalid" partition here.
1195
* 5 registers/cycle on McKinley).
1197
# define pRecurse p6
1201
alloc loc0=ar.pfs,2,Nregs-2,2,0
1202
shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
1203
sub r19=r19,r18 // r19 = (physStackedSize + 8) - dirtySize
1205
mov ar.rsc=r20 // load ar.rsc to be used for "loadrs"
1206
shladd in0=loc1,3,r19
1210
kvm_rse_clear_invalid:
1211
alloc loc0=ar.pfs,2,Nregs-2,2,0
1212
cmp.lt pRecurse,p0=Nregs*8,in0
1213
// if more than Nregs regs left to clear, (re)curse
1214
add out0=-Nregs*8,in0
1215
add out1=1,in1 // increment recursion count
1224
(pRecurse) br.call.dptk.few b0=kvm_rse_clear_invalid
1228
cmp.ne pReturn,p0=r0,in1
1229
// if recursion count != 0, we need to do a br.ret
1232
(pReturn) br.ret.dptk.many b0
1237
// loadrs has already been shifted
1238
alloc r16=ar.pfs,0,0,0,0 // drop current register frame
1252
adds r18=VMM_VPD_BASE_OFFSET,r21
1255
adds r17=VMM_VCPU_ISR_OFFSET,r21
1258
adds r19=VMM_VPD_VPSR_OFFSET,r18
1260
ld8 r19=[r19] //vpsr
1262
adds r16= VMM_VCPU_GP_OFFSET,r21
1264
ld8 r16= [r16] // Put gp in r24
1265
movl r24=@gprel(ia64_vmm_entry) // calculate return address
1269
br.sptk.many kvm_vps_sync_write // call the service
1271
END(ia64_leave_hypervisor)
1273
GLOBAL_ENTRY(ia64_vmm_entry)
1285
tbit.nz p1,p2 = r19,IA64_PSR_IC_BIT // p1=vpsr.ic
1286
(p1) br.cond.sptk.few kvm_vps_resume_normal
1287
(p2) br.cond.sptk.many kvm_vps_resume_handler
1292
* extern u64 ia64_call_vsa(u64 proc, u64 arg1, u64 arg2,
1293
* u64 arg3, u64 arg4, u64 arg5,
1294
* u64 arg6, u64 arg7);
1296
* XXX: The currently defined services use only 4 args at the max. The
1297
* rest are not consumed.
1299
GLOBAL_ENTRY(ia64_call_vsa)
1308
alloc pfssave=ar.pfs,4,4,0,0
1310
adds entry=VMM_VCPU_VSA_BASE_OFFSET, r13
1314
mov r25=in1 // copy arguments
1319
tbit.nz p6,p0=psrsave,14 // IA64_PSR_I
1320
tbit.nz p7,p0=psrsave,13 // IA64_PSR_IC
1322
add hostret=2f-1b,hostret // calculate return address
1329
br.cond.sptk b6 // call the service
1331
// Architectural sequence for enabling interrupts if necessary
1347
#define INIT_BSPSTORE ((4<<30)-(12<<20)-0x100)
1349
GLOBAL_ENTRY(vmm_reset_entry)
1350
//set up ipsr, iip, vpd.vpsr, dcr
1351
// For IPSR: it/dt/rt=1, i/ic=1, si=1, vm/bn=1
1352
// For DCR: all bits 0
1356
adds r14=-VMM_PT_REGS_SIZE, r12
1358
movl r6=0x501008826000 // IPSR dt/rt/it:1;i/ic:1, si:1, vm/bn:1
1359
movl r10=0x8000000000000000
1360
adds r16=PT(CR_IIP), r14
1361
adds r20=PT(R1), r14
1376
ld8 r4 = [r16] // Set init iip for first run.
1380
adds r16=VMM_VPD_BASE_OFFSET,r13
1384
adds r19=VMM_VPD_VPSR_OFFSET,r18
1390
br.cond.sptk ia64_vmm_entry
1392
END(vmm_reset_entry)