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* Copyright © 2019 Valve Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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#include "aco_builder.h"
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std::vector<aco_ptr<Instruction>> old_instructions;
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void join(const NOP_ctx_gfx6& other)
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set_vskip_mode_then_vector =
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MAX2(set_vskip_mode_then_vector, other.set_vskip_mode_then_vector);
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valu_wr_vcc_then_vccz = MAX2(valu_wr_vcc_then_vccz, other.valu_wr_vcc_then_vccz);
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valu_wr_exec_then_execz = MAX2(valu_wr_exec_then_execz, other.valu_wr_exec_then_execz);
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valu_wr_vcc_then_div_fmas = MAX2(valu_wr_vcc_then_div_fmas, other.valu_wr_vcc_then_div_fmas);
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salu_wr_m0_then_gds_msg_ttrace =
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MAX2(salu_wr_m0_then_gds_msg_ttrace, other.salu_wr_m0_then_gds_msg_ttrace);
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valu_wr_exec_then_dpp = MAX2(valu_wr_exec_then_dpp, other.valu_wr_exec_then_dpp);
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salu_wr_m0_then_lds = MAX2(salu_wr_m0_then_lds, other.salu_wr_m0_then_lds);
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salu_wr_m0_then_moverel = MAX2(salu_wr_m0_then_moverel, other.salu_wr_m0_then_moverel);
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setreg_then_getsetreg = MAX2(setreg_then_getsetreg, other.setreg_then_getsetreg);
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vmem_store_then_wr_data |= other.vmem_store_then_wr_data;
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smem_clause |= other.smem_clause;
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smem_write |= other.smem_write;
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for (unsigned i = 0; i < BITSET_WORDS(128); i++) {
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smem_clause_read_write[i] |= other.smem_clause_read_write[i];
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smem_clause_write[i] |= other.smem_clause_write[i];
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bool operator==(const NOP_ctx_gfx6& other)
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return set_vskip_mode_then_vector == other.set_vskip_mode_then_vector &&
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valu_wr_vcc_then_vccz == other.valu_wr_vcc_then_vccz &&
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valu_wr_exec_then_execz == other.valu_wr_exec_then_execz &&
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valu_wr_vcc_then_div_fmas == other.valu_wr_vcc_then_div_fmas &&
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vmem_store_then_wr_data == other.vmem_store_then_wr_data &&
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salu_wr_m0_then_gds_msg_ttrace == other.salu_wr_m0_then_gds_msg_ttrace &&
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valu_wr_exec_then_dpp == other.valu_wr_exec_then_dpp &&
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salu_wr_m0_then_lds == other.salu_wr_m0_then_lds &&
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salu_wr_m0_then_moverel == other.salu_wr_m0_then_moverel &&
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setreg_then_getsetreg == other.setreg_then_getsetreg &&
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smem_clause == other.smem_clause && smem_write == other.smem_write &&
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BITSET_EQUAL(smem_clause_read_write, other.smem_clause_read_write) &&
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BITSET_EQUAL(smem_clause_write, other.smem_clause_write);
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void add_wait_states(unsigned amount)
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if ((set_vskip_mode_then_vector -= amount) < 0)
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set_vskip_mode_then_vector = 0;
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if ((valu_wr_vcc_then_vccz -= amount) < 0)
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valu_wr_vcc_then_vccz = 0;
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if ((valu_wr_exec_then_execz -= amount) < 0)
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valu_wr_exec_then_execz = 0;
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if ((valu_wr_vcc_then_div_fmas -= amount) < 0)
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valu_wr_vcc_then_div_fmas = 0;
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if ((salu_wr_m0_then_gds_msg_ttrace -= amount) < 0)
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salu_wr_m0_then_gds_msg_ttrace = 0;
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if ((valu_wr_exec_then_dpp -= amount) < 0)
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valu_wr_exec_then_dpp = 0;
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if ((salu_wr_m0_then_lds -= amount) < 0)
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salu_wr_m0_then_lds = 0;
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if ((salu_wr_m0_then_moverel -= amount) < 0)
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salu_wr_m0_then_moverel = 0;
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if ((setreg_then_getsetreg -= amount) < 0)
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setreg_then_getsetreg = 0;
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vmem_store_then_wr_data.reset();
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/* setting MODE.vskip and then any vector op requires 2 wait states */
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int8_t set_vskip_mode_then_vector = 0;
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/* VALU writing VCC/EXEC and then a VALU reading VCCZ/EXECZ requires 5 wait states */
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int8_t valu_wr_vcc_then_vccz = 0;
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int8_t valu_wr_exec_then_execz = 0;
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/* VALU writing VCC followed by v_div_fmas require 4 wait states */
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int8_t valu_wr_vcc_then_div_fmas = 0;
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/* SALU writing M0 followed by GDS, s_sendmsg or s_ttrace_data requires 1 wait state */
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int8_t salu_wr_m0_then_gds_msg_ttrace = 0;
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/* VALU writing EXEC followed by DPP requires 5 wait states */
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int8_t valu_wr_exec_then_dpp = 0;
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/* SALU writing M0 followed by some LDS instructions requires 1 wait state on GFX10 */
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int8_t salu_wr_m0_then_lds = 0;
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/* SALU writing M0 followed by s_moverel requires 1 wait state on GFX9 */
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int8_t salu_wr_m0_then_moverel = 0;
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/* s_setreg followed by a s_getreg/s_setreg of the same register needs 2 wait states
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* currently we don't look at the actual register */
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int8_t setreg_then_getsetreg = 0;
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/* some memory instructions writing >64bit followed by a instructions
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* writing the VGPRs holding the writedata requires 1 wait state */
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std::bitset<256> vmem_store_then_wr_data;
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/* we break up SMEM clauses that contain stores or overwrite an
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* operand/definition of another instruction in the clause */
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bool smem_clause = false;
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bool smem_write = false;
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BITSET_DECLARE(smem_clause_read_write, 128) = {0};
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BITSET_DECLARE(smem_clause_write, 128) = {0};
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struct NOP_ctx_gfx10 {
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bool has_VOPC = false;
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bool has_nonVALU_exec_read = false;
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bool has_VMEM = false;
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bool has_branch_after_VMEM = false;
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bool has_branch_after_DS = false;
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bool has_NSA_MIMG = false;
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bool has_writelane = false;
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std::bitset<128> sgprs_read_by_VMEM;
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std::bitset<128> sgprs_read_by_SMEM;
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void join(const NOP_ctx_gfx10& other)
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has_VOPC |= other.has_VOPC;
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has_nonVALU_exec_read |= other.has_nonVALU_exec_read;
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has_VMEM |= other.has_VMEM;
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has_branch_after_VMEM |= other.has_branch_after_VMEM;
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has_DS |= other.has_DS;
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has_branch_after_DS |= other.has_branch_after_DS;
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has_NSA_MIMG |= other.has_NSA_MIMG;
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has_writelane |= other.has_writelane;
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sgprs_read_by_VMEM |= other.sgprs_read_by_VMEM;
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sgprs_read_by_SMEM |= other.sgprs_read_by_SMEM;
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bool operator==(const NOP_ctx_gfx10& other)
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return has_VOPC == other.has_VOPC && has_nonVALU_exec_read == other.has_nonVALU_exec_read &&
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has_VMEM == other.has_VMEM && has_branch_after_VMEM == other.has_branch_after_VMEM &&
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has_DS == other.has_DS && has_branch_after_DS == other.has_branch_after_DS &&
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has_NSA_MIMG == other.has_NSA_MIMG && has_writelane == other.has_writelane &&
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sgprs_read_by_VMEM == other.sgprs_read_by_VMEM &&
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sgprs_read_by_SMEM == other.sgprs_read_by_SMEM;
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get_wait_states(aco_ptr<Instruction>& instr)
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if (instr->opcode == aco_opcode::s_nop)
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return instr->sopp().imm + 1;
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else if (instr->opcode == aco_opcode::p_constaddr)
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return 3; /* lowered to 3 instructions in the assembler */
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regs_intersect(PhysReg a_reg, unsigned a_size, PhysReg b_reg, unsigned b_size)
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return a_reg > b_reg ? (a_reg - b_reg < b_size) : (b_reg - a_reg < a_size);
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template <bool Valu, bool Vintrp, bool Salu>
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handle_raw_hazard_instr(aco_ptr<Instruction>& pred, PhysReg reg, int* nops_needed, uint32_t* mask)
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unsigned mask_size = util_last_bit(*mask);
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uint32_t writemask = 0;
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for (Definition& def : pred->definitions) {
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if (regs_intersect(reg, mask_size, def.physReg(), def.size())) {
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unsigned start = def.physReg() > reg ? def.physReg() - reg : 0;
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unsigned end = MIN2(mask_size, start + def.size());
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writemask |= u_bit_consecutive(start, end - start);
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bool is_hazard = writemask != 0 && ((pred->isVALU() && Valu) || (pred->isVINTRP() && Vintrp) ||
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(pred->isSALU() && Salu));
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*nops_needed = MAX2(*nops_needed - get_wait_states(pred), 0);
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return *nops_needed == 0;
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template <bool Valu, bool Vintrp, bool Salu>
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handle_raw_hazard_internal(State& state, Block* block, int nops_needed, PhysReg reg, uint32_t mask,
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if (block == state.block && start_at_end) {
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/* If it's the current block, block->instructions is incomplete. */
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for (int pred_idx = state.old_instructions.size() - 1; pred_idx >= 0; pred_idx--) {
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aco_ptr<Instruction>& instr = state.old_instructions[pred_idx];
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break; /* Instruction has been moved to block->instructions. */
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if (handle_raw_hazard_instr<Valu, Vintrp, Salu>(instr, reg, &nops_needed, &mask))
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for (int pred_idx = block->instructions.size() - 1; pred_idx >= 0; pred_idx--) {
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if (handle_raw_hazard_instr<Valu, Vintrp, Salu>(block->instructions[pred_idx], reg,
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&nops_needed, &mask))
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/* Loops require branch instructions, which count towards the wait
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* states. So even with loops this should finish unless nops_needed is some
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for (unsigned lin_pred : block->linear_preds) {
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std::max(res, handle_raw_hazard_internal<Valu, Vintrp, Salu>(
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state, &state.program->blocks[lin_pred], nops_needed, reg, mask, true));
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template <bool Valu, bool Vintrp, bool Salu>
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handle_raw_hazard(State& state, int* NOPs, int min_states, Operand op)
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if (*NOPs >= min_states)
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int res = handle_raw_hazard_internal<Valu, Vintrp, Salu>(
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state, state.block, min_states, op.physReg(), u_bit_consecutive(0, op.size()), false);
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*NOPs = MAX2(*NOPs, res);
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static auto handle_valu_then_read_hazard = handle_raw_hazard<true, true, false>;
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static auto handle_vintrp_then_read_hazard = handle_raw_hazard<false, true, false>;
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static auto handle_valu_salu_then_read_hazard = handle_raw_hazard<true, true, true>;
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set_bitset_range(BITSET_WORD* words, unsigned start, unsigned size)
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unsigned end = start + size - 1;
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unsigned start_mod = start % BITSET_WORDBITS;
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if (start_mod + size <= BITSET_WORDBITS) {
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BITSET_SET_RANGE_INSIDE_WORD(words, start, end);
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unsigned first_size = BITSET_WORDBITS - start_mod;
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set_bitset_range(words, start, BITSET_WORDBITS - start_mod);
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set_bitset_range(words, start + first_size, size - first_size);
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test_bitset_range(BITSET_WORD* words, unsigned start, unsigned size)
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unsigned end = start + size - 1;
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unsigned start_mod = start % BITSET_WORDBITS;
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if (start_mod + size <= BITSET_WORDBITS) {
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return BITSET_TEST_RANGE(words, start, end);
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unsigned first_size = BITSET_WORDBITS - start_mod;
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return test_bitset_range(words, start, BITSET_WORDBITS - start_mod) ||
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test_bitset_range(words, start + first_size, size - first_size);
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/* A SMEM clause is any group of consecutive SMEM instructions. The
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* instructions in this group may return out of order and/or may be replayed.
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* To fix this potential hazard correctly, we have to make sure that when a
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* clause has more than one instruction, no instruction in the clause writes
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* to a register that is read by another instruction in the clause (including
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* itself). In this case, we have to break the SMEM clause by inserting non
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* SMEM clauses are only present on GFX8+, and only matter when XNACK is set.
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handle_smem_clause_hazards(Program* program, NOP_ctx_gfx6& ctx, aco_ptr<Instruction>& instr,
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/* break off from previous SMEM clause if needed */
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if (!*NOPs & (ctx.smem_clause || ctx.smem_write)) {
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/* Don't allow clauses with store instructions since the clause's
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* instructions may use the same address. */
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if (ctx.smem_write || instr->definitions.empty() ||
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instr_info.is_atomic[(unsigned)instr->opcode]) {
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} else if (program->dev.xnack_enabled) {
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for (Operand op : instr->operands) {
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if (!op.isConstant() &&
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test_bitset_range(ctx.smem_clause_write, op.physReg(), op.size())) {
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Definition def = instr->definitions[0];
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if (!*NOPs && test_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size()))
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/* TODO: we don't handle accessing VCC using the actual SGPR instead of using the alias */
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handle_instruction_gfx6(State& state, NOP_ctx_gfx6& ctx, aco_ptr<Instruction>& instr,
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std::vector<aco_ptr<Instruction>>& new_instructions)
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if (instr->isSMEM()) {
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if (state.program->chip_class == GFX6) {
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/* A read of an SGPR by SMRD instruction requires 4 wait states
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* when the SGPR was written by a VALU instruction. According to LLVM,
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* there is also an undocumented hardware behavior when the buffer
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* descriptor is written by a SALU instruction */
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for (unsigned i = 0; i < instr->operands.size(); i++) {
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Operand op = instr->operands[i];
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bool is_buffer_desc = i == 0 && op.size() > 2;
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handle_valu_salu_then_read_hazard(state, &NOPs, 4, op);
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handle_valu_then_read_hazard(state, &NOPs, 4, op);
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handle_smem_clause_hazards(state.program, ctx, instr, &NOPs);
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} else if (instr->isSALU()) {
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if (instr->opcode == aco_opcode::s_setreg_b32 ||
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instr->opcode == aco_opcode::s_setreg_imm32_b32 ||
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instr->opcode == aco_opcode::s_getreg_b32) {
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NOPs = MAX2(NOPs, ctx.setreg_then_getsetreg);
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if (state.program->chip_class == GFX9) {
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if (instr->opcode == aco_opcode::s_movrels_b32 ||
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instr->opcode == aco_opcode::s_movrels_b64 ||
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instr->opcode == aco_opcode::s_movreld_b32 ||
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instr->opcode == aco_opcode::s_movreld_b64) {
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NOPs = MAX2(NOPs, ctx.salu_wr_m0_then_moverel);
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if (instr->opcode == aco_opcode::s_sendmsg || instr->opcode == aco_opcode::s_ttracedata)
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NOPs = MAX2(NOPs, ctx.salu_wr_m0_then_gds_msg_ttrace);
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} else if (instr->isDS() && instr->ds().gds) {
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NOPs = MAX2(NOPs, ctx.salu_wr_m0_then_gds_msg_ttrace);
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} else if (instr->isVALU() || instr->isVINTRP()) {
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for (Operand op : instr->operands) {
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if (op.physReg() == vccz)
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NOPs = MAX2(NOPs, ctx.valu_wr_vcc_then_vccz);
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if (op.physReg() == execz)
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NOPs = MAX2(NOPs, ctx.valu_wr_exec_then_execz);
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if (instr->isDPP()) {
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NOPs = MAX2(NOPs, ctx.valu_wr_exec_then_dpp);
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handle_valu_then_read_hazard(state, &NOPs, 2, instr->operands[0]);
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for (Definition def : instr->definitions) {
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if (def.regClass().type() != RegType::sgpr) {
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for (unsigned i = 0; i < def.size(); i++)
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NOPs = MAX2(NOPs, ctx.vmem_store_then_wr_data[(def.physReg() & 0xff) + i]);
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if ((instr->opcode == aco_opcode::v_readlane_b32 ||
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instr->opcode == aco_opcode::v_readlane_b32_e64 ||
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instr->opcode == aco_opcode::v_writelane_b32 ||
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instr->opcode == aco_opcode::v_writelane_b32_e64) &&
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!instr->operands[1].isConstant()) {
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handle_valu_then_read_hazard(state, &NOPs, 4, instr->operands[1]);
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/* It's required to insert 1 wait state if the dst VGPR of any v_interp_*
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* is followed by a read with v_readfirstlane or v_readlane to fix GPU
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* hangs on GFX6. Note that v_writelane_* is apparently not affected.
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* This hazard isn't documented anywhere but AMD confirmed that hazard.
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if (state.program->chip_class == GFX6 &&
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(instr->opcode == aco_opcode::v_readlane_b32 || /* GFX6 doesn't have v_readlane_b32_e64 */
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instr->opcode == aco_opcode::v_readfirstlane_b32)) {
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handle_vintrp_then_read_hazard(state, &NOPs, 1, instr->operands[0]);
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if (instr->opcode == aco_opcode::v_div_fmas_f32 ||
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instr->opcode == aco_opcode::v_div_fmas_f64)
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NOPs = MAX2(NOPs, ctx.valu_wr_vcc_then_div_fmas);
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} else if (instr->isVMEM() || instr->isFlatLike()) {
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/* If the VALU writes the SGPR that is used by a VMEM, the user must add five wait states. */
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for (Operand op : instr->operands) {
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if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr)
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handle_valu_then_read_hazard(state, &NOPs, 5, op);
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if (!instr->isSALU() && instr->format != Format::SMEM)
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NOPs = MAX2(NOPs, ctx.set_vskip_mode_then_vector);
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if (state.program->chip_class == GFX9) {
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bool lds_scratch_global = (instr->isScratch() || instr->isGlobal()) && instr->flatlike().lds;
453
if (instr->isVINTRP() || lds_scratch_global ||
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instr->opcode == aco_opcode::ds_read_addtid_b32 ||
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instr->opcode == aco_opcode::ds_write_addtid_b32 ||
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instr->opcode == aco_opcode::buffer_store_lds_dword) {
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NOPs = MAX2(NOPs, ctx.salu_wr_m0_then_lds);
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ctx.add_wait_states(NOPs + get_wait_states(instr));
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// TODO: try to schedule the NOP-causing instruction up to reduce the number of stall cycles
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aco_ptr<SOPP_instruction> nop{
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create_instruction<SOPP_instruction>(aco_opcode::s_nop, Format::SOPP, 0, 0)};
470
new_instructions.emplace_back(std::move(nop));
473
/* update information to check for later hazards */
474
if ((ctx.smem_clause || ctx.smem_write) && (NOPs || instr->format != Format::SMEM)) {
475
ctx.smem_clause = false;
476
ctx.smem_write = false;
478
if (state.program->dev.xnack_enabled) {
479
BITSET_ZERO(ctx.smem_clause_read_write);
480
BITSET_ZERO(ctx.smem_clause_write);
484
if (instr->isSMEM()) {
485
if (instr->definitions.empty() || instr_info.is_atomic[(unsigned)instr->opcode]) {
486
ctx.smem_write = true;
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ctx.smem_clause = true;
490
if (state.program->dev.xnack_enabled) {
491
for (Operand op : instr->operands) {
492
if (!op.isConstant()) {
493
set_bitset_range(ctx.smem_clause_read_write, op.physReg(), op.size());
497
Definition def = instr->definitions[0];
498
set_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size());
499
set_bitset_range(ctx.smem_clause_write, def.physReg(), def.size());
502
} else if (instr->isVALU()) {
503
for (Definition def : instr->definitions) {
504
if (def.regClass().type() == RegType::sgpr) {
505
if (def.physReg() == vcc || def.physReg() == vcc_hi) {
506
ctx.valu_wr_vcc_then_vccz = 5;
507
ctx.valu_wr_vcc_then_div_fmas = 4;
509
if (def.physReg() == exec || def.physReg() == exec_hi) {
510
ctx.valu_wr_exec_then_execz = 5;
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ctx.valu_wr_exec_then_dpp = 5;
515
} else if (instr->isSALU() && !instr->definitions.empty()) {
516
if (!instr->definitions.empty()) {
517
/* all other definitions should be SCC */
518
Definition def = instr->definitions[0];
519
if (def.physReg() == m0) {
520
ctx.salu_wr_m0_then_gds_msg_ttrace = 1;
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ctx.salu_wr_m0_then_lds = 1;
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ctx.salu_wr_m0_then_moverel = 1;
524
} else if (instr->opcode == aco_opcode::s_setreg_b32 ||
525
instr->opcode == aco_opcode::s_setreg_imm32_b32) {
526
SOPK_instruction& sopk = instr->sopk();
527
unsigned offset = (sopk.imm >> 6) & 0x1f;
528
unsigned size = ((sopk.imm >> 11) & 0x1f) + 1;
529
unsigned reg = sopk.imm & 0x3f;
530
ctx.setreg_then_getsetreg = 2;
532
if (reg == 1 && offset >= 28 && size > (28 - offset))
533
ctx.set_vskip_mode_then_vector = 2;
535
} else if (instr->isVMEM() || instr->isFlatLike()) {
536
/* >64-bit MUBUF/MTBUF store with a constant in SOFFSET */
537
bool consider_buf = (instr->isMUBUF() || instr->isMTBUF()) && instr->operands.size() == 4 &&
538
instr->operands[3].size() > 2 && instr->operands[2].physReg() >= 128;
539
/* MIMG store with a 128-bit T# with more than two bits set in dmask (making it a >64-bit
541
bool consider_mimg = instr->isMIMG() &&
542
instr->operands[1].regClass().type() == RegType::vgpr &&
543
instr->operands[1].size() > 2 && instr->operands[0].size() == 4;
544
/* FLAT/GLOBAL/SCRATCH store with >64-bit data */
546
instr->isFlatLike() && instr->operands.size() == 3 && instr->operands[2].size() > 2;
547
if (consider_buf || consider_mimg || consider_flat) {
548
PhysReg wrdata = instr->operands[consider_flat ? 2 : 3].physReg();
549
unsigned size = instr->operands[consider_flat ? 2 : 3].size();
550
for (unsigned i = 0; i < size; i++)
551
ctx.vmem_store_then_wr_data[(wrdata & 0xff) + i] = 1;
556
template <std::size_t N>
558
check_written_regs(const aco_ptr<Instruction>& instr, const std::bitset<N>& check_regs)
560
return std::any_of(instr->definitions.begin(), instr->definitions.end(),
561
[&check_regs](const Definition& def) -> bool
563
bool writes_any = false;
564
for (unsigned i = 0; i < def.size(); i++) {
565
unsigned def_reg = def.physReg() + i;
566
writes_any |= def_reg < check_regs.size() && check_regs[def_reg];
572
template <std::size_t N>
574
mark_read_regs(const aco_ptr<Instruction>& instr, std::bitset<N>& reg_reads)
576
for (const Operand& op : instr->operands) {
577
for (unsigned i = 0; i < op.size(); i++) {
578
unsigned reg = op.physReg() + i;
579
if (reg < reg_reads.size())
586
VALU_writes_sgpr(aco_ptr<Instruction>& instr)
590
if (instr->isVOP3() && instr->definitions.size() == 2)
592
if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
593
instr->opcode == aco_opcode::v_readlane_b32 ||
594
instr->opcode == aco_opcode::v_readlane_b32_e64)
600
instr_writes_exec(const aco_ptr<Instruction>& instr)
602
return std::any_of(instr->definitions.begin(), instr->definitions.end(),
603
[](const Definition& def) -> bool
604
{ return def.physReg() == exec_lo || def.physReg() == exec_hi; });
608
instr_writes_sgpr(const aco_ptr<Instruction>& instr)
610
return std::any_of(instr->definitions.begin(), instr->definitions.end(),
611
[](const Definition& def) -> bool
612
{ return def.getTemp().type() == RegType::sgpr; });
616
instr_is_branch(const aco_ptr<Instruction>& instr)
618
return instr->opcode == aco_opcode::s_branch || instr->opcode == aco_opcode::s_cbranch_scc0 ||
619
instr->opcode == aco_opcode::s_cbranch_scc1 ||
620
instr->opcode == aco_opcode::s_cbranch_vccz ||
621
instr->opcode == aco_opcode::s_cbranch_vccnz ||
622
instr->opcode == aco_opcode::s_cbranch_execz ||
623
instr->opcode == aco_opcode::s_cbranch_execnz ||
624
instr->opcode == aco_opcode::s_cbranch_cdbgsys ||
625
instr->opcode == aco_opcode::s_cbranch_cdbguser ||
626
instr->opcode == aco_opcode::s_cbranch_cdbgsys_or_user ||
627
instr->opcode == aco_opcode::s_cbranch_cdbgsys_and_user ||
628
instr->opcode == aco_opcode::s_subvector_loop_begin ||
629
instr->opcode == aco_opcode::s_subvector_loop_end ||
630
instr->opcode == aco_opcode::s_setpc_b64 || instr->opcode == aco_opcode::s_swappc_b64 ||
631
instr->opcode == aco_opcode::s_getpc_b64 || instr->opcode == aco_opcode::s_call_b64;
635
handle_instruction_gfx10(State& state, NOP_ctx_gfx10& ctx, aco_ptr<Instruction>& instr,
636
std::vector<aco_ptr<Instruction>>& new_instructions)
638
// TODO: s_dcache_inv needs to be in it's own group on GFX10
640
/* VMEMtoScalarWriteHazard
641
* Handle EXEC/M0/SGPR write following a VMEM instruction without a VALU or "waitcnt vmcnt(0)"
644
if (instr->isVMEM() || instr->isFlatLike() || instr->isDS()) {
645
/* Remember all SGPRs that are read by the VMEM instruction */
646
mark_read_regs(instr, ctx.sgprs_read_by_VMEM);
647
ctx.sgprs_read_by_VMEM.set(exec);
648
if (state.program->wave_size == 64)
649
ctx.sgprs_read_by_VMEM.set(exec_hi);
650
} else if (instr->isSALU() || instr->isSMEM()) {
651
if (instr->opcode == aco_opcode::s_waitcnt) {
652
/* Hazard is mitigated by "s_waitcnt vmcnt(0)" */
653
uint16_t imm = instr->sopp().imm;
654
unsigned vmcnt = (imm & 0xF) | ((imm & (0x3 << 14)) >> 10);
656
ctx.sgprs_read_by_VMEM.reset();
657
} else if (instr->opcode == aco_opcode::s_waitcnt_depctr) {
658
/* Hazard is mitigated by a s_waitcnt_depctr with a magic imm */
659
if (instr->sopp().imm == 0xffe3)
660
ctx.sgprs_read_by_VMEM.reset();
663
/* Check if SALU writes an SGPR that was previously read by the VALU */
664
if (check_written_regs(instr, ctx.sgprs_read_by_VMEM)) {
665
ctx.sgprs_read_by_VMEM.reset();
667
/* Insert s_waitcnt_depctr instruction with magic imm to mitigate the problem */
668
aco_ptr<SOPP_instruction> depctr{
669
create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 0)};
670
depctr->imm = 0xffe3;
672
new_instructions.emplace_back(std::move(depctr));
674
} else if (instr->isVALU()) {
675
/* Hazard is mitigated by any VALU instruction */
676
ctx.sgprs_read_by_VMEM.reset();
679
/* VcmpxPermlaneHazard
680
* Handle any permlane following a VOPC instruction, insert v_mov between them.
682
if (instr->isVOPC()) {
684
} else if (ctx.has_VOPC && (instr->opcode == aco_opcode::v_permlane16_b32 ||
685
instr->opcode == aco_opcode::v_permlanex16_b32)) {
686
ctx.has_VOPC = false;
688
/* v_nop would be discarded by SQ, so use v_mov with the first operand of the permlane */
689
aco_ptr<VOP1_instruction> v_mov{
690
create_instruction<VOP1_instruction>(aco_opcode::v_mov_b32, Format::VOP1, 1, 1)};
691
v_mov->definitions[0] = Definition(instr->operands[0].physReg(), v1);
692
v_mov->operands[0] = Operand(instr->operands[0].physReg(), v1);
693
new_instructions.emplace_back(std::move(v_mov));
694
} else if (instr->isVALU() && instr->opcode != aco_opcode::v_nop) {
695
ctx.has_VOPC = false;
698
/* VcmpxExecWARHazard
699
* Handle any VALU instruction writing the exec mask after it was read by a non-VALU instruction.
701
if (!instr->isVALU() && instr->reads_exec()) {
702
ctx.has_nonVALU_exec_read = true;
703
} else if (instr->isVALU()) {
704
if (instr_writes_exec(instr)) {
705
ctx.has_nonVALU_exec_read = false;
707
/* Insert s_waitcnt_depctr instruction with magic imm to mitigate the problem */
708
aco_ptr<SOPP_instruction> depctr{
709
create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 0)};
710
depctr->imm = 0xfffe;
712
new_instructions.emplace_back(std::move(depctr));
713
} else if (instr_writes_sgpr(instr)) {
714
/* Any VALU instruction that writes an SGPR mitigates the problem */
715
ctx.has_nonVALU_exec_read = false;
717
} else if (instr->opcode == aco_opcode::s_waitcnt_depctr) {
718
/* s_waitcnt_depctr can mitigate the problem if it has a magic imm */
719
if ((instr->sopp().imm & 0xfffe) == 0xfffe)
720
ctx.has_nonVALU_exec_read = false;
723
/* SMEMtoVectorWriteHazard
724
* Handle any VALU instruction writing an SGPR after an SMEM reads it.
726
if (instr->isSMEM()) {
727
/* Remember all SGPRs that are read by the SMEM instruction */
728
mark_read_regs(instr, ctx.sgprs_read_by_SMEM);
729
} else if (VALU_writes_sgpr(instr)) {
730
/* Check if VALU writes an SGPR that was previously read by SMEM */
731
if (check_written_regs(instr, ctx.sgprs_read_by_SMEM)) {
732
ctx.sgprs_read_by_SMEM.reset();
734
/* Insert s_mov to mitigate the problem */
735
aco_ptr<SOP1_instruction> s_mov{
736
create_instruction<SOP1_instruction>(aco_opcode::s_mov_b32, Format::SOP1, 1, 1)};
737
s_mov->definitions[0] = Definition(sgpr_null, s1);
738
s_mov->operands[0] = Operand::zero();
739
new_instructions.emplace_back(std::move(s_mov));
741
} else if (instr->isSALU()) {
742
if (instr->format != Format::SOPP) {
743
/* SALU can mitigate the hazard */
744
ctx.sgprs_read_by_SMEM.reset();
746
/* Reducing lgkmcnt count to 0 always mitigates the hazard. */
747
const SOPP_instruction& sopp = instr->sopp();
748
if (sopp.opcode == aco_opcode::s_waitcnt_lgkmcnt) {
749
if (sopp.imm == 0 && sopp.definitions[0].physReg() == sgpr_null)
750
ctx.sgprs_read_by_SMEM.reset();
751
} else if (sopp.opcode == aco_opcode::s_waitcnt) {
752
unsigned lgkm = (sopp.imm >> 8) & 0x3f;
754
ctx.sgprs_read_by_SMEM.reset();
759
/* LdsBranchVmemWARHazard
760
* Handle VMEM/GLOBAL/SCRATCH->branch->DS and DS->branch->VMEM/GLOBAL/SCRATCH patterns.
762
if (instr->isVMEM() || instr->isGlobal() || instr->isScratch()) {
764
ctx.has_branch_after_VMEM = false;
765
/* Mitigation for DS is needed only if there was already a branch after */
766
ctx.has_DS = ctx.has_branch_after_DS;
767
} else if (instr->isDS()) {
769
ctx.has_branch_after_DS = false;
770
/* Mitigation for VMEM is needed only if there was already a branch after */
771
ctx.has_VMEM = ctx.has_branch_after_VMEM;
772
} else if (instr_is_branch(instr)) {
773
ctx.has_branch_after_VMEM = ctx.has_VMEM;
774
ctx.has_branch_after_DS = ctx.has_DS;
775
} else if (instr->opcode == aco_opcode::s_waitcnt_vscnt) {
776
/* Only s_waitcnt_vscnt can mitigate the hazard */
777
const SOPK_instruction& sopk = instr->sopk();
778
if (sopk.definitions[0].physReg() == sgpr_null && sopk.imm == 0)
779
ctx.has_VMEM = ctx.has_branch_after_VMEM = ctx.has_DS = ctx.has_branch_after_DS = false;
781
if ((ctx.has_VMEM && ctx.has_branch_after_DS) || (ctx.has_DS && ctx.has_branch_after_VMEM)) {
782
ctx.has_VMEM = ctx.has_branch_after_VMEM = ctx.has_DS = ctx.has_branch_after_DS = false;
784
/* Insert s_waitcnt_vscnt to mitigate the problem */
785
aco_ptr<SOPK_instruction> wait{
786
create_instruction<SOPK_instruction>(aco_opcode::s_waitcnt_vscnt, Format::SOPK, 0, 1)};
787
wait->definitions[0] = Definition(sgpr_null, s1);
789
new_instructions.emplace_back(std::move(wait));
793
* Handles NSA MIMG (4 or more dwords) immediately followed by MUBUF/MTBUF (with offset[2:1] !=
796
if (instr->isMIMG() && get_mimg_nsa_dwords(instr.get()) > 1) {
797
ctx.has_NSA_MIMG = true;
798
} else if (ctx.has_NSA_MIMG) {
799
ctx.has_NSA_MIMG = false;
801
if (instr->isMUBUF() || instr->isMTBUF()) {
802
uint32_t offset = instr->isMUBUF() ? instr->mubuf().offset : instr->mtbuf().offset;
804
Builder(state.program, &new_instructions).sopp(aco_opcode::s_nop, -1, 0);
808
/* waNsaCannotFollowWritelane
809
* Handles NSA MIMG immediately following a v_writelane_b32.
811
if (instr->opcode == aco_opcode::v_writelane_b32_e64) {
812
ctx.has_writelane = true;
813
} else if (ctx.has_writelane) {
814
ctx.has_writelane = false;
815
if (instr->isMIMG() && get_mimg_nsa_dwords(instr.get()) > 0)
816
Builder(state.program, &new_instructions).sopp(aco_opcode::s_nop, -1, 0);
820
template <typename Ctx>
821
using HandleInstr = void (*)(State& state, Ctx&, aco_ptr<Instruction>&,
822
std::vector<aco_ptr<Instruction>>&);
824
template <typename Ctx, HandleInstr<Ctx> Handle>
826
handle_block(Program* program, Ctx& ctx, Block& block)
828
if (block.instructions.empty())
832
state.program = program;
833
state.block = █
834
state.old_instructions = std::move(block.instructions);
836
block.instructions.clear(); // Silence clang-analyzer-cplusplus.Move warning
837
block.instructions.reserve(state.old_instructions.size());
839
for (aco_ptr<Instruction>& instr : state.old_instructions) {
840
Handle(state, ctx, instr, block.instructions);
841
block.instructions.emplace_back(std::move(instr));
845
template <typename Ctx, HandleInstr<Ctx> Handle>
847
mitigate_hazards(Program* program)
849
std::vector<Ctx> all_ctx(program->blocks.size());
850
std::stack<unsigned, std::vector<unsigned>> loop_header_indices;
852
for (unsigned i = 0; i < program->blocks.size(); i++) {
853
Block& block = program->blocks[i];
854
Ctx& ctx = all_ctx[i];
856
if (block.kind & block_kind_loop_header) {
857
loop_header_indices.push(i);
858
} else if (block.kind & block_kind_loop_exit) {
859
/* Go through the whole loop again */
860
for (unsigned idx = loop_header_indices.top(); idx < i; idx++) {
862
for (unsigned b : program->blocks[idx].linear_preds)
863
loop_block_ctx.join(all_ctx[b]);
865
handle_block<Ctx, Handle>(program, loop_block_ctx, program->blocks[idx]);
867
/* We only need to continue if the loop header context changed */
868
if (idx == loop_header_indices.top() && loop_block_ctx == all_ctx[idx])
871
all_ctx[idx] = loop_block_ctx;
874
loop_header_indices.pop();
877
for (unsigned b : block.linear_preds)
878
ctx.join(all_ctx[b]);
880
handle_block<Ctx, Handle>(program, ctx, block);
884
} /* end namespace */
887
insert_NOPs(Program* program)
889
if (program->chip_class >= GFX10_3)
890
; /* no hazards/bugs to mitigate */
891
else if (program->chip_class >= GFX10)
892
mitigate_hazards<NOP_ctx_gfx10, handle_instruction_gfx10>(program);
894
mitigate_hazards<NOP_ctx_gfx6, handle_instruction_gfx6>(program);
added
removed
src/amd/compiler/aco_insert_NOPs.cpp
