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* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
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* Copyright 2018 Advanced Micro Devices, Inc.
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "driver_ddebug/dd_util.h"
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#include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
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#include "gallium/winsys/radeon/drm/radeon_drm_public.h"
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#include "radeon/radeon_uvd.h"
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#include "si_compute.h"
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#include "si_public.h"
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#include "si_shader_internal.h"
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#include "ac_shadowed_regs.h"
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#include "compiler/nir/nir.h"
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#include "util/disk_cache.h"
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#include "util/u_cpu_detect.h"
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#include "util/u_log.h"
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#include "util/u_memory.h"
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#include "util/u_suballoc.h"
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#include "util/u_tests.h"
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#include "util/u_upload_mgr.h"
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#include "util/xmlconfig.h"
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#include "vl/vl_decoder.h"
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static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags);
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static const struct debug_named_value radeonsi_debug_options[] = {
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/* Shader logging options: */
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{"vs", DBG(VS), "Print vertex shaders"},
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{"ps", DBG(PS), "Print pixel shaders"},
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{"gs", DBG(GS), "Print geometry shaders"},
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{"tcs", DBG(TCS), "Print tessellation control shaders"},
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{"tes", DBG(TES), "Print tessellation evaluation shaders"},
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{"cs", DBG(CS), "Print compute shaders"},
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{"noir", DBG(NO_IR), "Don't print the LLVM IR"},
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{"nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
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{"noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
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{"preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations"},
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/* Shader compiler options the shader cache should be aware of: */
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{"w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders."},
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{"w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders."},
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{"w32psdiscard", DBG(W32_PS_DISCARD), "Use Wave32 for pixel shaders even if they contain discard and LLVM is buggy."},
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{"w32cs", DBG(W32_CS), "Use Wave32 for computes shaders."},
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{"w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders."},
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{"w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders."},
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{"w64cs", DBG(W64_CS), "Use Wave64 for computes shaders."},
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/* Shader compiler options (with no effect on the shader cache): */
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{"checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR"},
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{"mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand"},
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{"nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants."},
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/* Information logging options: */
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{"info", DBG(INFO), "Print driver information"},
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{"tex", DBG(TEX), "Print texture info"},
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{"compute", DBG(COMPUTE), "Print compute info"},
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{"vm", DBG(VM), "Print virtual addresses when creating resources"},
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{"cache_stats", DBG(CACHE_STATS), "Print shader cache statistics."},
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{"ib", DBG(IB), "Print command buffers."},
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{"nowc", DBG(NO_WC), "Disable GTT write combining"},
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{"check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info."},
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{"reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context."},
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{"shadowregs", DBG(SHADOW_REGS), "Enable CP register shadowing."},
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{"nofastdlist", DBG(NO_FAST_DISPLAY_LIST), "Disable fast display lists"},
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/* Multimedia options: */
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{ "noefc", DBG(NO_EFC), "Disable hardware based encoder colour format conversion."},
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/* 3D engine options: */
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{"nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used."},
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{"nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline."},
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{"nggc", DBG(ALWAYS_NGG_CULLING_ALL), "Always use NGG culling even when it can hurt."},
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{"nonggc", DBG(NO_NGG_CULLING), "Disable NGG culling."},
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{"switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet."},
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{"nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization"},
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{"nodpbb", DBG(NO_DPBB), "Disable DPBB."},
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{"dpbb", DBG(DPBB), "Enable DPBB."},
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{"nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z"},
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{"no2d", DBG(NO_2D_TILING), "Disable 2D tiling"},
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{"notiling", DBG(NO_TILING), "Disable tiling"},
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{"nodisplaytiling", DBG(NO_DISPLAY_TILING), "Disable display tiling"},
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{"nodisplaydcc", DBG(NO_DISPLAY_DCC), "Disable display DCC"},
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{"noexporteddcc", DBG(NO_EXPORTED_DCC), "Disable DCC for all exported buffers (via DMABUF, etc.)"},
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{"nodcc", DBG(NO_DCC), "Disable DCC."},
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{"nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear."},
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{"nodccstore", DBG(NO_DCC_STORE), "Disable DCC stores"},
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{"dccstore", DBG(DCC_STORE), "Enable DCC stores"},
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{"nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA"},
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{"nofmask", DBG(NO_FMASK), "Disable MSAA compression"},
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{"nodma", DBG(NO_DMA), "Disable SDMA-copy for DRI_PRIME"},
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{"tmz", DBG(TMZ), "Force allocation of scanout/depth/stencil buffer as encrypted"},
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{"sqtt", DBG(SQTT), "Enable SQTT"},
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DEBUG_NAMED_VALUE_END /* must be last */
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static const struct debug_named_value test_options[] = {
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{"blit", DBG(TEST_BLIT), "Invoke blit tests and exit."},
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{"testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit."},
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{"testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit."},
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{"testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance"},
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{"testgds", DBG(TEST_GDS), "Test GDS."},
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{"testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management."},
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{"testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management."},
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DEBUG_NAMED_VALUE_END /* must be last */
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void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
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/* Only create the less-optimizing version of the compiler on APUs
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* predating Ryzen (Raven). */
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bool create_low_opt_compiler =
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!sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8;
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enum ac_target_machine_options tm_options =
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(sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
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(create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
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ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
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compiler->passes = ac_create_llvm_passes(compiler->tm);
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if (compiler->low_opt_tm)
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compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
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void si_init_aux_async_compute_ctx(struct si_screen *sscreen)
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assert(!sscreen->async_compute_context);
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sscreen->async_compute_context = si_create_context(
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SI_CONTEXT_FLAG_AUX |
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(sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
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PIPE_CONTEXT_COMPUTE_ONLY);
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/* Limit the numbers of waves allocated for this context. */
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if (sscreen->async_compute_context)
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((struct si_context*)sscreen->async_compute_context)->cs_max_waves_per_sh = 2;
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static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
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ac_destroy_llvm_compiler(compiler);
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static void decref_implicit_resource(struct hash_entry *entry)
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pipe_resource_reference((struct pipe_resource**)&entry->data, NULL);
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static void si_destroy_context(struct pipe_context *context)
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struct si_context *sctx = (struct si_context *)context;
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/* Unreference the framebuffer normally to disable related logic
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struct pipe_framebuffer_state fb = {};
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if (context->set_framebuffer_state)
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context->set_framebuffer_state(context, &fb);
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si_release_all_descriptors(sctx);
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if (sctx->chip_class >= GFX10 && sctx->has_graphics)
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gfx10_destroy_query(sctx);
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if (sctx->thread_trace)
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si_destroy_thread_trace(sctx);
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pipe_resource_reference(&sctx->esgs_ring, NULL);
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pipe_resource_reference(&sctx->gsvs_ring, NULL);
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pipe_resource_reference(&sctx->tess_rings, NULL);
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pipe_resource_reference(&sctx->tess_rings_tmz, NULL);
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pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
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pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
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si_resource_reference(&sctx->border_color_buffer, NULL);
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free(sctx->border_color_table);
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si_resource_reference(&sctx->scratch_buffer, NULL);
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si_resource_reference(&sctx->compute_scratch_buffer, NULL);
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si_resource_reference(&sctx->wait_mem_scratch, NULL);
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si_resource_reference(&sctx->wait_mem_scratch_tmz, NULL);
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si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
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if (sctx->cs_preamble_state)
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si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0);
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if (sctx->cs_preamble_tess_rings)
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si_pm4_free_state(sctx, sctx->cs_preamble_tess_rings, ~0);
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if (sctx->cs_preamble_tess_rings_tmz)
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si_pm4_free_state(sctx, sctx->cs_preamble_tess_rings_tmz, ~0);
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if (sctx->cs_preamble_gs_rings)
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si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
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for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
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si_pm4_free_state(sctx, sctx->vgt_shader_config[i], SI_STATE_IDX(vgt_shader_config));
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if (sctx->fixed_func_tcs_shader.cso)
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sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
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if (sctx->custom_dsa_flush)
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sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
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if (sctx->custom_blend_resolve)
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sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
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if (sctx->custom_blend_fmask_decompress)
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sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
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if (sctx->custom_blend_eliminate_fastclear)
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sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
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if (sctx->custom_blend_dcc_decompress)
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sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
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if (sctx->vs_blit_pos)
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sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
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if (sctx->vs_blit_pos_layered)
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sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
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if (sctx->vs_blit_color)
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sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
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if (sctx->vs_blit_color_layered)
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sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
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if (sctx->vs_blit_texcoord)
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sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
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if (sctx->cs_clear_buffer)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
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if (sctx->cs_clear_buffer_rmw)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer_rmw);
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if (sctx->cs_copy_buffer)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
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if (sctx->cs_copy_image_1D)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1D);
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if (sctx->cs_copy_image_2D)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_2D);
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if (sctx->cs_clear_render_target)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
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if (sctx->cs_clear_render_target_1d_array)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
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if (sctx->cs_clear_12bytes_buffer)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
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if (sctx->cs_dcc_decompress)
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_decompress);
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for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_dcc_retile); i++) {
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if (sctx->cs_dcc_retile[i])
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile[i]);
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if (sctx->no_velems_state)
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sctx->b.delete_vertex_elements_state(&sctx->b, sctx->no_velems_state);
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for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
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for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
280
if (sctx->cs_fmask_expand[i][j]) {
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_fmask_expand[i][j]);
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for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_clear_dcc_msaa); i++) {
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for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i]); j++) {
288
for (unsigned k = 0; k < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j]); k++) {
289
for (unsigned l = 0; l < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j][k]); l++) {
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for (unsigned m = 0; m < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j][k][l]); m++) {
291
if (sctx->cs_clear_dcc_msaa[i][j][k][l][m])
292
sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_dcc_msaa[i][j][k][l][m]);
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util_blitter_destroy(sctx->blitter);
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if (sctx->query_result_shader)
303
sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
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if (sctx->sh_query_result_shader)
305
sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
307
sctx->ws->cs_destroy(&sctx->gfx_cs);
309
sctx->ws->ctx_destroy(sctx->ctx);
311
sctx->ws->cs_destroy(sctx->sdma_cs);
315
if (sctx->dirty_implicit_resources)
316
_mesa_hash_table_destroy(sctx->dirty_implicit_resources,
317
decref_implicit_resource);
319
if (sctx->b.stream_uploader)
320
u_upload_destroy(sctx->b.stream_uploader);
321
if (sctx->b.const_uploader && sctx->b.const_uploader != sctx->b.stream_uploader)
322
u_upload_destroy(sctx->b.const_uploader);
323
if (sctx->cached_gtt_allocator)
324
u_upload_destroy(sctx->cached_gtt_allocator);
326
slab_destroy_child(&sctx->pool_transfers);
327
slab_destroy_child(&sctx->pool_transfers_unsync);
329
u_suballocator_destroy(&sctx->allocator_zeroed_memory);
331
sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
332
si_resource_reference(&sctx->eop_bug_scratch, NULL);
333
si_resource_reference(&sctx->eop_bug_scratch_tmz, NULL);
334
si_resource_reference(&sctx->shadowed_regs, NULL);
335
radeon_bo_reference(sctx->screen->ws, &sctx->gds, NULL);
336
radeon_bo_reference(sctx->screen->ws, &sctx->gds_oa, NULL);
338
si_destroy_compiler(&sctx->compiler);
340
si_saved_cs_reference(&sctx->current_saved_cs, NULL);
342
_mesa_hash_table_destroy(sctx->tex_handles, NULL);
343
_mesa_hash_table_destroy(sctx->img_handles, NULL);
345
util_dynarray_fini(&sctx->resident_tex_handles);
346
util_dynarray_fini(&sctx->resident_img_handles);
347
util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
348
util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
349
util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
351
if (!(sctx->context_flags & SI_CONTEXT_FLAG_AUX))
352
p_atomic_dec(&context->screen->num_contexts);
357
static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
359
struct si_context *sctx = (struct si_context *)ctx;
360
if (sctx->context_flags & SI_CONTEXT_FLAG_AUX)
361
return PIPE_NO_RESET;
364
enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx, false, &needs_reset);
366
if (status != PIPE_NO_RESET && needs_reset && !(sctx->context_flags & SI_CONTEXT_FLAG_AUX)) {
367
/* Call the gallium frontend to set a no-op API dispatch. */
368
if (sctx->device_reset_callback.reset) {
369
sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
375
static void si_set_device_reset_callback(struct pipe_context *ctx,
376
const struct pipe_device_reset_callback *cb)
378
struct si_context *sctx = (struct si_context *)ctx;
381
sctx->device_reset_callback = *cb;
383
memset(&sctx->device_reset_callback, 0, sizeof(sctx->device_reset_callback));
386
/* Apitrace profiling:
387
* 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
388
* 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
389
* and remember its number.
390
* 3) In Mesa, enable queries and performance counters around that draw
391
* call and print the results.
392
* 4) glretrace --benchmark --markers ..
394
static void si_emit_string_marker(struct pipe_context *ctx, const char *string, int len)
396
struct si_context *sctx = (struct si_context *)ctx;
398
dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
400
if (sctx->thread_trace_enabled)
401
si_write_user_event(sctx, &sctx->gfx_cs, UserEventTrigger, string, len);
404
u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
407
static void si_set_debug_callback(struct pipe_context *ctx, const struct util_debug_callback *cb)
409
struct si_context *sctx = (struct si_context *)ctx;
410
struct si_screen *screen = sctx->screen;
412
util_queue_finish(&screen->shader_compiler_queue);
413
util_queue_finish(&screen->shader_compiler_queue_low_priority);
418
memset(&sctx->debug, 0, sizeof(sctx->debug));
421
static void si_set_log_context(struct pipe_context *ctx, struct u_log_context *log)
423
struct si_context *sctx = (struct si_context *)ctx;
427
u_log_add_auto_logger(log, si_auto_log_cs, sctx);
430
static void si_set_context_param(struct pipe_context *ctx, enum pipe_context_param param,
433
struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
436
case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
437
ws->pin_threads_to_L3_cache(ws, value);
443
static void si_set_frontend_noop(struct pipe_context *ctx, bool enable)
445
struct si_context *sctx = (struct si_context *)ctx;
447
ctx->flush(ctx, NULL, PIPE_FLUSH_ASYNC);
448
sctx->is_noop = enable;
451
static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags)
453
struct si_screen *sscreen = (struct si_screen *)screen;
454
STATIC_ASSERT(DBG_COUNT <= 64);
456
/* Don't create a context if it's not compute-only and hw is compute-only. */
457
if (!sscreen->info.has_graphics && !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
460
struct si_context *sctx = CALLOC_STRUCT(si_context);
461
struct radeon_winsys *ws = sscreen->ws;
463
bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
468
sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
470
if (flags & PIPE_CONTEXT_DEBUG)
471
sscreen->record_llvm_ir = true; /* racy but not critical */
473
sctx->b.screen = screen; /* this must be set first */
475
sctx->b.destroy = si_destroy_context;
476
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
477
sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
478
sctx->context_flags = flags;
480
slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
481
slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
483
sctx->ws = sscreen->ws;
484
sctx->family = sscreen->info.family;
485
sctx->chip_class = sscreen->info.chip_class;
487
if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) {
488
sctx->eop_bug_scratch = si_aligned_buffer_create(
489
&sscreen->b, SI_RESOURCE_FLAG_DRIVER_INTERNAL,
490
PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256);
491
if (!sctx->eop_bug_scratch)
495
/* Initialize the context handle and the command stream. */
496
sctx->ctx = sctx->ws->ctx_create(sctx->ws);
500
ws->cs_create(&sctx->gfx_cs, sctx->ctx, sctx->has_graphics ? RING_GFX : RING_COMPUTE,
501
(void *)si_flush_gfx_cs, sctx, stop_exec_on_failure);
503
/* Initialize private allocators. */
504
u_suballocator_init(&sctx->allocator_zeroed_memory, &sctx->b, 128 * 1024, 0,
506
SI_RESOURCE_FLAG_CLEAR | SI_RESOURCE_FLAG_32BIT, false);
508
sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024, 0, PIPE_USAGE_STAGING, 0);
509
if (!sctx->cached_gtt_allocator)
512
/* Initialize public allocators. */
513
/* Unify uploaders as follows:
514
* - dGPUs with Smart Access Memory: there is only one uploader instance writing to VRAM.
515
* - APUs: There is only one uploader instance writing to RAM. VRAM has the same perf on APUs.
516
* - Other chips: The const uploader writes to VRAM and the stream uploader writes to RAM.
518
bool smart_access_memory = sscreen->info.smart_access_memory;
519
bool is_apu = !sscreen->info.has_dedicated_vram;
520
sctx->b.stream_uploader =
521
u_upload_create(&sctx->b, 1024 * 1024, 0,
522
smart_access_memory && !is_apu ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STREAM,
523
SI_RESOURCE_FLAG_32BIT); /* same flags as const_uploader */
524
if (!sctx->b.stream_uploader)
527
if (smart_access_memory || is_apu) {
528
sctx->b.const_uploader = sctx->b.stream_uploader;
530
sctx->b.const_uploader =
531
u_upload_create(&sctx->b, 256 * 1024, 0, PIPE_USAGE_DEFAULT,
532
SI_RESOURCE_FLAG_32BIT);
533
if (!sctx->b.const_uploader)
538
if (sscreen->info.has_3d_cube_border_color_mipmap) {
539
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table));
540
if (!sctx->border_color_table)
543
sctx->border_color_buffer = si_resource(pipe_buffer_create(
544
screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)));
545
if (!sctx->border_color_buffer)
548
sctx->border_color_map =
549
ws->buffer_map(ws, sctx->border_color_buffer->buf, NULL, PIPE_MAP_WRITE);
550
if (!sctx->border_color_map)
554
sctx->ngg = sscreen->use_ngg;
555
si_shader_change_notify(sctx);
557
/* Initialize context functions used by graphics and compute. */
558
if (sctx->chip_class >= GFX10)
559
sctx->emit_cache_flush = gfx10_emit_cache_flush;
561
sctx->emit_cache_flush = si_emit_cache_flush;
563
sctx->b.emit_string_marker = si_emit_string_marker;
564
sctx->b.set_debug_callback = si_set_debug_callback;
565
sctx->b.set_log_context = si_set_log_context;
566
sctx->b.set_context_param = si_set_context_param;
567
sctx->b.get_device_reset_status = si_get_reset_status;
568
sctx->b.set_device_reset_callback = si_set_device_reset_callback;
569
sctx->b.set_frontend_noop = si_set_frontend_noop;
571
si_init_all_descriptors(sctx);
572
si_init_buffer_functions(sctx);
573
si_init_clear_functions(sctx);
574
si_init_blit_functions(sctx);
575
si_init_compute_functions(sctx);
576
si_init_compute_blit_functions(sctx);
577
si_init_debug_functions(sctx);
578
si_init_fence_functions(sctx);
579
si_init_query_functions(sctx);
580
si_init_state_compute_functions(sctx);
581
si_init_context_texture_functions(sctx);
583
/* Initialize graphics-only context functions. */
584
if (sctx->has_graphics) {
585
if (sctx->chip_class >= GFX10)
586
gfx10_init_query(sctx);
587
si_init_msaa_functions(sctx);
588
si_init_shader_functions(sctx);
589
si_init_state_functions(sctx);
590
si_init_streamout_functions(sctx);
591
si_init_viewport_functions(sctx);
592
si_init_spi_map_functions(sctx);
594
sctx->blitter = util_blitter_create(&sctx->b);
595
if (sctx->blitter == NULL)
597
sctx->blitter->skip_viewport_restore = true;
599
/* Some states are expected to be always non-NULL. */
600
sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
601
sctx->queued.named.blend = sctx->noop_blend;
603
sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
604
sctx->queued.named.dsa = sctx->noop_dsa;
606
sctx->no_velems_state = sctx->b.create_vertex_elements_state(&sctx->b, 0, NULL);
607
sctx->vertex_elements = sctx->no_velems_state;
609
sctx->discard_rasterizer_state = util_blitter_get_discard_rasterizer_state(sctx->blitter);
610
sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
612
switch (sctx->chip_class) {
614
si_init_draw_functions_GFX6(sctx);
617
si_init_draw_functions_GFX7(sctx);
620
si_init_draw_functions_GFX8(sctx);
623
si_init_draw_functions_GFX9(sctx);
626
si_init_draw_functions_GFX10(sctx);
629
si_init_draw_functions_GFX10_3(sctx);
632
unreachable("unhandled chip class");
636
sctx->sample_mask = 0xffff;
638
/* Initialize multimedia functions. */
639
if (sscreen->info.has_video_hw.uvd_decode || sscreen->info.has_video_hw.vcn_decode ||
640
sscreen->info.has_video_hw.jpeg_decode || sscreen->info.has_video_hw.vce_encode ||
641
sscreen->info.has_video_hw.uvd_encode || sscreen->info.has_video_hw.vcn_encode) {
642
sctx->b.create_video_codec = si_uvd_create_decoder;
643
sctx->b.create_video_buffer = si_video_buffer_create;
644
if (screen->resource_create_with_modifiers)
645
sctx->b.create_video_buffer_with_modifiers = si_video_buffer_create_with_modifiers;
647
sctx->b.create_video_codec = vl_create_decoder;
648
sctx->b.create_video_buffer = vl_video_buffer_create;
651
if (sctx->chip_class >= GFX9) {
652
sctx->wait_mem_scratch =
653
si_aligned_buffer_create(screen,
654
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
655
PIPE_USAGE_DEFAULT, 8,
656
sscreen->info.tcc_cache_line_size);
657
if (!sctx->wait_mem_scratch)
661
/* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
662
* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
663
if (sctx->chip_class == GFX7) {
664
sctx->null_const_buf.buffer =
665
pipe_aligned_buffer_create(screen,
666
SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
667
PIPE_USAGE_DEFAULT, 16,
668
sctx->screen->info.tcc_cache_line_size);
669
if (!sctx->null_const_buf.buffer)
671
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
673
unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
674
for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
675
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
676
sctx->b.set_constant_buffer(&sctx->b, shader, i, false, &sctx->null_const_buf);
680
si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &sctx->null_const_buf);
681
si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &sctx->null_const_buf);
682
si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &sctx->null_const_buf);
683
si_set_internal_const_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &sctx->null_const_buf);
684
si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf);
687
uint64_t max_threads_per_block;
688
screen->get_compute_param(screen, PIPE_SHADER_IR_NIR, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
689
&max_threads_per_block);
691
/* The maximum number of scratch waves. Scratch space isn't divided
692
* evenly between CUs. The number is only a function of the number of CUs.
693
* We can decrease the constant to decrease the scratch buffer size.
695
* sctx->scratch_waves must be >= the maximum possible size of
696
* 1 threadgroup, so that the hw doesn't hang from being unable
699
sctx->scratch_waves =
700
MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64);
702
/* Bindless handles. */
703
sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
704
sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
706
util_dynarray_init(&sctx->resident_tex_handles, NULL);
707
util_dynarray_init(&sctx->resident_img_handles, NULL);
708
util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
709
util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
710
util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
712
sctx->dirty_implicit_resources = _mesa_pointer_hash_table_create(NULL);
713
if (!sctx->dirty_implicit_resources)
716
/* The remainder of this function initializes the gfx CS and must be last. */
717
assert(sctx->gfx_cs.current.cdw == 0);
719
if (sctx->has_graphics) {
720
si_init_cp_reg_shadowing(sctx);
723
/* Set immutable fields of shader keys. */
724
if (sctx->chip_class >= GFX9) {
725
/* The LS output / HS input layout can be communicated
726
* directly instead of via user SGPRs for merged LS-HS.
727
* This also enables jumping over the VS prolog for HS-only waves.
729
* When the LS VGPR fix is needed, monolithic shaders can:
730
* - avoid initializing EXEC in both the LS prolog
731
* and the LS main part when !vs_needs_prolog
732
* - remove the fixup for unused input VGPRs
734
sctx->shader.tcs.key.ge.opt.prefer_mono = 1;
736
/* This enables jumping over the VS prolog for GS-only waves. */
737
sctx->shader.gs.key.ge.opt.prefer_mono = 1;
740
si_begin_new_gfx_cs(sctx, true);
741
assert(sctx->gfx_cs.current.cdw == sctx->initial_gfx_cs_size);
743
/* Initialize per-context buffers. */
744
if (sctx->wait_mem_scratch)
745
si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME,
746
&sctx->wait_mem_number);
747
if (sctx->wait_mem_scratch_tmz)
748
si_cp_write_data(sctx, sctx->wait_mem_scratch_tmz, 0, 4, V_370_MEM, V_370_ME,
749
&sctx->wait_mem_number);
751
if (sctx->chip_class == GFX7) {
752
/* Clear the NULL constant buffer, because loads should return zeros.
753
* Note that this forces CP DMA to be used, because clover deadlocks
754
* for some reason when the compute codepath is used.
756
uint32_t clear_value = 0;
757
si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0,
758
&clear_value, 4, SI_OP_SYNC_AFTER, SI_COHERENCY_SHADER,
759
SI_CP_DMA_CLEAR_METHOD);
762
if (!(flags & SI_CONTEXT_FLAG_AUX)) {
763
p_atomic_inc(&screen->num_contexts);
765
/* Check if the aux_context needs to be recreated */
766
struct si_context *saux = (struct si_context *)sscreen->aux_context;
768
simple_mtx_lock(&sscreen->aux_context_lock);
769
enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(
770
saux->ctx, true, NULL);
771
if (status != PIPE_NO_RESET) {
772
/* We lost the aux_context, create a new one */
773
struct u_log_context *aux_log = (saux)->log;
774
sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
775
sscreen->aux_context->destroy(sscreen->aux_context);
777
sscreen->aux_context = si_create_context(
778
&sscreen->b, SI_CONTEXT_FLAG_AUX |
779
(sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
780
(sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
781
sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
783
simple_mtx_unlock(&sscreen->aux_context_lock);
785
simple_mtx_lock(&sscreen->async_compute_context_lock);
786
if (status != PIPE_NO_RESET && sscreen->async_compute_context) {
787
sscreen->async_compute_context->destroy(sscreen->async_compute_context);
788
sscreen->async_compute_context = NULL;
790
simple_mtx_unlock(&sscreen->async_compute_context_lock);
793
sctx->initial_gfx_cs_size = sctx->gfx_cs.current.cdw;
796
fprintf(stderr, "radeonsi: Failed to create a context.\n");
797
si_destroy_context(&sctx->b);
801
static bool si_is_resource_busy(struct pipe_screen *screen, struct pipe_resource *resource,
804
struct radeon_winsys *ws = ((struct si_screen *)screen)->ws;
806
return !ws->buffer_wait(ws, si_resource(resource)->buf, 0,
807
/* If mapping for write, we need to wait for all reads and writes.
808
* If mapping for read, we only need to wait for writes.
810
usage & PIPE_MAP_WRITE ? RADEON_USAGE_READWRITE : RADEON_USAGE_WRITE);
813
static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, void *priv,
816
struct si_screen *sscreen = (struct si_screen *)screen;
817
struct pipe_context *ctx;
819
if (sscreen->debug_flags & DBG(CHECK_VM))
820
flags |= PIPE_CONTEXT_DEBUG;
822
ctx = si_create_context(screen, flags);
824
if (ctx && sscreen->info.chip_class >= GFX9 && sscreen->debug_flags & DBG(SQTT)) {
825
if (!si_init_thread_trace((struct si_context *)ctx)) {
831
if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
834
/* Clover (compute-only) is unsupported. */
835
if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
838
/* When shaders are logged to stderr, asynchronous compilation is
840
if (sscreen->debug_flags & DBG_ALL_SHADERS)
843
/* Use asynchronous flushes only on amdgpu, since the radeon
844
* implementation for fence_server_sync is incomplete. */
845
struct pipe_context *tc =
846
threaded_context_create(ctx, &sscreen->pool_transfers,
847
si_replace_buffer_storage,
848
&(struct threaded_context_options){
849
.create_fence = sscreen->info.is_amdgpu ?
850
si_create_fence : NULL,
851
.is_resource_busy = si_is_resource_busy,
852
.driver_calls_flush_notify = true,
854
&((struct si_context *)ctx)->tc);
857
threaded_context_init_bytes_mapped_limit((struct threaded_context *)tc, 4);
865
static void si_destroy_screen(struct pipe_screen *pscreen)
867
struct si_screen *sscreen = (struct si_screen *)pscreen;
868
struct si_shader_part *parts[] = {sscreen->vs_prologs, sscreen->tcs_epilogs,
869
sscreen->ps_prologs, sscreen->ps_epilogs};
872
if (!sscreen->ws->unref(sscreen->ws))
875
if (sscreen->debug_flags & DBG(CACHE_STATS)) {
876
printf("live shader cache: hits = %u, misses = %u\n", sscreen->live_shader_cache.hits,
877
sscreen->live_shader_cache.misses);
878
printf("memory shader cache: hits = %u, misses = %u\n", sscreen->num_memory_shader_cache_hits,
879
sscreen->num_memory_shader_cache_misses);
880
printf("disk shader cache: hits = %u, misses = %u\n", sscreen->num_disk_shader_cache_hits,
881
sscreen->num_disk_shader_cache_misses);
884
simple_mtx_destroy(&sscreen->aux_context_lock);
886
if (sscreen->aux_context) {
887
struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
889
sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
890
u_log_context_destroy(aux_log);
894
sscreen->aux_context->destroy(sscreen->aux_context);
897
simple_mtx_destroy(&sscreen->async_compute_context_lock);
898
if (sscreen->async_compute_context) {
899
sscreen->async_compute_context->destroy(sscreen->async_compute_context);
902
util_queue_destroy(&sscreen->shader_compiler_queue);
903
util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
905
/* Release the reference on glsl types of the compiler threads. */
906
glsl_type_singleton_decref();
908
for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
909
si_destroy_compiler(&sscreen->compiler[i]);
911
for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
912
si_destroy_compiler(&sscreen->compiler_lowp[i]);
914
/* Free shader parts. */
915
for (i = 0; i < ARRAY_SIZE(parts); i++) {
917
struct si_shader_part *part = parts[i];
919
parts[i] = part->next;
920
si_shader_binary_clean(&part->binary);
924
simple_mtx_destroy(&sscreen->shader_parts_mutex);
925
si_destroy_shader_cache(sscreen);
927
si_destroy_perfcounters(sscreen);
928
si_gpu_load_kill_thread(sscreen);
930
simple_mtx_destroy(&sscreen->gpu_load_mutex);
932
slab_destroy_parent(&sscreen->pool_transfers);
934
disk_cache_destroy(sscreen->disk_shader_cache);
935
util_live_shader_cache_deinit(&sscreen->live_shader_cache);
936
util_idalloc_mt_fini(&sscreen->buffer_ids);
937
util_vertex_state_cache_deinit(&sscreen->vertex_state_cache);
939
sscreen->ws->destroy(sscreen->ws);
943
static void si_init_gs_info(struct si_screen *sscreen)
945
sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, sscreen->info.family);
948
static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
950
struct pipe_context *ctx = sscreen->aux_context;
951
struct si_context *sctx = (struct si_context *)ctx;
952
struct pipe_resource *buf = pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
955
puts("Buffer allocation failed.");
959
si_resource(buf)->gpu_address = 0; /* cause a VM fault */
961
if (test_flags & DBG(TEST_VMFAULT_CP)) {
962
si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, SI_OP_SYNC_BEFORE_AFTER,
963
SI_COHERENCY_NONE, L2_BYPASS);
964
ctx->flush(ctx, NULL, 0);
965
puts("VM fault test: CP - done.");
967
if (test_flags & DBG(TEST_VMFAULT_SHADER)) {
968
util_test_constant_buffer(ctx, buf);
969
puts("VM fault test: Shader - done.");
974
static void si_test_gds_memory_management(struct si_context *sctx, unsigned alloc_size,
975
unsigned alignment, enum radeon_bo_domain domain)
977
struct radeon_winsys *ws = sctx->ws;
978
struct radeon_cmdbuf cs[8];
979
struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
981
for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
982
ws->cs_create(&cs[i], sctx->ctx, RING_COMPUTE, NULL, NULL, false);
983
gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
987
for (unsigned iterations = 0; iterations < 20000; iterations++) {
988
for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
989
/* This clears GDS with CP DMA.
991
* We don't care if GDS is present. Just add some packet
992
* to make the GPU busy for a moment.
994
si_cp_dma_clear_buffer(
995
sctx, &cs[i], NULL, 0, alloc_size, 0,
996
SI_OP_CPDMA_SKIP_CHECK_CS_SPACE, 0,
999
ws->cs_add_buffer(&cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain);
1000
ws->cs_flush(&cs[i], PIPE_FLUSH_ASYNC, NULL);
1006
static void si_disk_cache_create(struct si_screen *sscreen)
1008
/* Don't use the cache if shader dumping is enabled. */
1009
if (sscreen->debug_flags & DBG_ALL_SHADERS)
1012
struct mesa_sha1 ctx;
1013
unsigned char sha1[20];
1014
char cache_id[20 * 2 + 1];
1016
_mesa_sha1_init(&ctx);
1018
if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
1019
!disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
1022
_mesa_sha1_final(&ctx, sha1);
1023
disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
1025
sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id,
1026
sscreen->info.address32_hi);
1029
static void si_set_max_shader_compiler_threads(struct pipe_screen *screen, unsigned max_threads)
1031
struct si_screen *sscreen = (struct si_screen *)screen;
1033
/* This function doesn't allow a greater number of threads than
1034
* the queue had at its creation. */
1035
util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, max_threads);
1036
/* Don't change the number of threads on the low priority queue. */
1039
static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen, void *shader,
1040
enum pipe_shader_type shader_type)
1042
struct si_shader_selector *sel = (struct si_shader_selector *)shader;
1044
return util_queue_fence_is_signalled(&sel->ready);
1047
static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
1048
const struct pipe_screen_config *config)
1050
struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
1051
unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
1052
uint64_t test_flags;
1059
#define OPT_BOOL(name, dflt, description) \
1060
sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name);
1061
#define OPT_INT(name, dflt, description) \
1062
sscreen->options.name = driQueryOptioni(config->options, "radeonsi_" #name);
1063
#include "si_debug_options.h"
1067
ws->query_info(ws, &sscreen->info,
1068
sscreen->options.enable_sam,
1069
sscreen->options.disable_sam);
1071
if (sscreen->info.chip_class >= GFX9) {
1072
sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
1074
ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config,
1075
&sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat);
1078
sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", radeonsi_debug_options, 0);
1079
sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", radeonsi_debug_options, 0);
1080
test_flags = debug_get_flags_option("AMD_TEST", test_options, 0);
1082
if (sscreen->debug_flags & DBG(NO_GFX))
1083
sscreen->info.has_graphics = false;
1085
if ((sscreen->debug_flags & DBG(TMZ)) &&
1086
!sscreen->info.has_tmz_support) {
1087
fprintf(stderr, "radeonsi: requesting TMZ features but TMZ is not supported\n");
1092
util_idalloc_mt_init_tc(&sscreen->buffer_ids);
1094
/* Set functions first. */
1095
sscreen->b.context_create = si_pipe_create_context;
1096
sscreen->b.destroy = si_destroy_screen;
1097
sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads;
1098
sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished;
1099
sscreen->b.finalize_nir = si_finalize_nir;
1101
si_init_screen_get_functions(sscreen);
1102
si_init_screen_buffer_functions(sscreen);
1103
si_init_screen_fence_functions(sscreen);
1104
si_init_screen_state_functions(sscreen);
1105
si_init_screen_texture_functions(sscreen);
1106
si_init_screen_query_functions(sscreen);
1107
si_init_screen_live_shader_cache(sscreen);
1109
/* Set these flags in debug_flags early, so that the shader cache takes
1110
* them into account.
1112
* Enable FS_CORRECT_DERIVS_AFTER_KILL by default if LLVM is >= 13. This makes
1113
* nir_opt_move_discards_to_top more effective.
1115
if (driQueryOptionb(config->options, "glsl_correct_derivatives_after_discard") ||
1116
LLVM_VERSION_MAJOR >= 13)
1117
sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1119
if (sscreen->debug_flags & DBG(INFO))
1120
ac_print_gpu_info(&sscreen->info, stdout);
1122
slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64);
1124
sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1125
if (sscreen->force_aniso == -1) {
1126
sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1129
if (sscreen->force_aniso >= 0) {
1130
printf("radeonsi: Forcing anisotropy filter to %ix\n",
1131
/* round down to a power of two */
1132
1 << util_logbase2(sscreen->force_aniso));
1135
(void)simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1136
(void)simple_mtx_init(&sscreen->async_compute_context_lock, mtx_plain);
1137
(void)simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1139
si_init_gs_info(sscreen);
1140
if (!si_init_shader_cache(sscreen)) {
1145
if (sscreen->info.chip_class < GFX10_3)
1146
sscreen->options.vrs2x2 = false;
1148
si_disk_cache_create(sscreen);
1150
/* Determine the number of shader compiler threads. */
1151
const struct util_cpu_caps_t *caps = util_get_cpu_caps();
1152
hw_threads = caps->nr_cpus;
1154
if (hw_threads >= 12) {
1155
num_comp_hi_threads = hw_threads * 3 / 4;
1156
num_comp_lo_threads = hw_threads / 3;
1157
} else if (hw_threads >= 6) {
1158
num_comp_hi_threads = hw_threads - 2;
1159
num_comp_lo_threads = hw_threads / 2;
1160
} else if (hw_threads >= 2) {
1161
num_comp_hi_threads = hw_threads - 1;
1162
num_comp_lo_threads = hw_threads / 2;
1164
num_comp_hi_threads = 1;
1165
num_comp_lo_threads = 1;
1169
nir_process_debug_variable();
1171
/* Use a single compilation thread if NIR printing is enabled to avoid
1172
* multiple shaders being printed at the same time.
1174
if (NIR_DEBUG(PRINT)) {
1175
num_comp_hi_threads = 1;
1176
num_comp_lo_threads = 1;
1180
num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler));
1181
num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp));
1183
/* Take a reference on the glsl types for the compiler threads. */
1184
glsl_type_singleton_init_or_ref();
1186
if (!util_queue_init(
1187
&sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads,
1188
UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY, NULL)) {
1189
si_destroy_shader_cache(sscreen);
1191
glsl_type_singleton_decref();
1195
if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", 64,
1196
num_comp_lo_threads,
1197
UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1198
UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY, NULL)) {
1199
si_destroy_shader_cache(sscreen);
1201
glsl_type_singleton_decref();
1205
if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1206
si_init_perfcounters(sscreen);
1208
sscreen->max_memory_usage_kb = sscreen->info.vram_size_kb + sscreen->info.gart_size_kb / 4 * 3;
1210
/* Determine tessellation ring info. */
1211
bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1212
sscreen->info.family != CHIP_CARRIZO &&
1213
sscreen->info.family != CHIP_STONEY;
1214
/* This must be one less than the maximum number due to a hw limitation.
1215
* Various hardware bugs need this.
1217
unsigned max_offchip_buffers_per_se;
1219
if (sscreen->info.chip_class >= GFX10)
1220
max_offchip_buffers_per_se = 128;
1221
/* Only certain chips can use the maximum value. */
1222
else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20)
1223
max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1225
max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1227
unsigned max_offchip_buffers = max_offchip_buffers_per_se * sscreen->info.max_se;
1228
unsigned offchip_granularity;
1230
/* Hawaii has a bug with offchip buffers > 256 that can be worked
1231
* around by setting 4K granularity.
1233
if (sscreen->info.family == CHIP_HAWAII) {
1234
sscreen->tess_offchip_block_dw_size = 4096;
1235
offchip_granularity = V_03093C_X_4K_DWORDS;
1237
sscreen->tess_offchip_block_dw_size = 8192;
1238
offchip_granularity = V_03093C_X_8K_DWORDS;
1241
sscreen->tess_factor_ring_size = 48 * 1024 * sscreen->info.max_se;
1242
sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4;
1244
if (sscreen->info.chip_class >= GFX10_3) {
1245
sscreen->vgt_hs_offchip_param =
1246
S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
1247
S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
1248
} else if (sscreen->info.chip_class >= GFX7) {
1249
if (sscreen->info.chip_class >= GFX8)
1250
--max_offchip_buffers;
1251
sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) |
1252
S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity);
1254
assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1255
sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1258
sscreen->has_draw_indirect_multi =
1259
(sscreen->info.family >= CHIP_POLARIS10) ||
1260
(sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 &&
1261
sscreen->info.me_fw_version >= 87) ||
1262
(sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 &&
1263
sscreen->info.me_fw_version >= 173) ||
1264
(sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 &&
1265
sscreen->info.me_fw_version >= 142);
1267
sscreen->has_out_of_order_rast =
1268
sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1269
sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights") ||
1270
driQueryOptionb(config->options, "allow_draw_out_of_order");
1271
sscreen->commutative_blend_add =
1272
driQueryOptionb(config->options, "radeonsi_commutative_blend_add") ||
1273
driQueryOptionb(config->options, "allow_draw_out_of_order");
1274
sscreen->allow_draw_out_of_order = driQueryOptionb(config->options, "allow_draw_out_of_order");
1276
sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) &&
1277
sscreen->info.chip_class >= GFX10 &&
1278
(sscreen->info.family != CHIP_NAVI14 ||
1279
sscreen->info.is_pro_graphics);
1280
sscreen->use_ngg_culling = sscreen->use_ngg &&
1281
sscreen->info.max_render_backends >= 2 &&
1282
!((sscreen->debug_flags & DBG(NO_NGG_CULLING)) ||
1283
LLVM_VERSION_MAJOR <= 11 /* hangs on 11, see #4874 */);
1284
sscreen->use_ngg_streamout = false;
1286
/* Only set this for the cases that are known to work, which are:
1287
* - GFX9 if bpp >= 4 (in bytes)
1289
if (sscreen->info.chip_class >= GFX10) {
1290
memset(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp, true,
1291
sizeof(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp));
1292
} else if (sscreen->info.chip_class == GFX9) {
1293
for (unsigned bpp_log2 = util_logbase2(1); bpp_log2 <= util_logbase2(16); bpp_log2++)
1294
sscreen->allow_dcc_msaa_clear_to_reg_for_bpp[bpp_log2] = true;
1297
/* DCC stores have 50% performance of uncompressed stores and sometimes
1298
* even less than that. It's risky to enable on dGPUs.
1300
sscreen->always_allow_dcc_stores = !(sscreen->debug_flags & DBG(NO_DCC_STORE)) &&
1301
((sscreen->info.chip_class >= GFX10_3 &&
1302
!sscreen->info.has_dedicated_vram) ||
1303
sscreen->debug_flags & DBG(DCC_STORE));
1305
sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) &&
1306
(sscreen->info.chip_class >= GFX10 ||
1307
/* Only enable primitive binning on gfx9 APUs by default. */
1308
(sscreen->info.chip_class == GFX9 && !sscreen->info.has_dedicated_vram) ||
1309
sscreen->debug_flags & DBG(DPBB));
1311
if (sscreen->dpbb_allowed) {
1312
if (sscreen->info.has_dedicated_vram) {
1313
if (sscreen->info.max_render_backends > 4) {
1314
sscreen->pbb_context_states_per_bin = 1;
1315
sscreen->pbb_persistent_states_per_bin = 1;
1317
sscreen->pbb_context_states_per_bin = 3;
1318
sscreen->pbb_persistent_states_per_bin = 8;
1321
/* This is a workaround for:
1322
* https://bugs.freedesktop.org/show_bug.cgi?id=110214
1323
* (an alternative is to insert manual BATCH_BREAK event when
1324
* a context_roll is detected). */
1325
sscreen->pbb_context_states_per_bin = sscreen->info.has_gfx9_scissor_bug ? 1 : 6;
1326
/* Using 32 here can cause GPU hangs on RAVEN1 */
1327
sscreen->pbb_persistent_states_per_bin = 16;
1330
assert(sscreen->pbb_context_states_per_bin >= 1 &&
1331
sscreen->pbb_context_states_per_bin <= 6);
1332
assert(sscreen->pbb_persistent_states_per_bin >= 1 &&
1333
sscreen->pbb_persistent_states_per_bin <= 32);
1336
(void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1337
sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1339
sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
1340
if (sscreen->info.chip_class <= GFX8) {
1341
sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1342
sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1345
if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1346
sscreen->debug_flags |= DBG_ALL_SHADERS;
1353
* That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1355
* s >= z >= c (ignoring this only wastes memory)
1360
* Only MSAA color and depth buffers are overriden.
1362
if (sscreen->info.has_eqaa_surface_allocator) {
1363
const char *eqaa = debug_get_option("EQAA", NULL);
1366
if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1367
sscreen->eqaa_force_coverage_samples = s;
1368
sscreen->eqaa_force_z_samples = z;
1369
sscreen->eqaa_force_color_samples = f;
1373
sscreen->ngg_subgroup_size = 128;
1375
/* Create the auxiliary context. This must be done last. */
1376
sscreen->aux_context = si_create_context(
1378
SI_CONTEXT_FLAG_AUX |
1379
(sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1380
(sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1382
if (sscreen->options.aux_debug) {
1383
struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1384
u_log_context_init(log);
1385
sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1388
if (test_flags & DBG(TEST_BLIT))
1389
si_test_blit(sscreen);
1391
if (test_flags & DBG(TEST_DMA_PERF)) {
1392
si_test_dma_perf(sscreen);
1395
if (test_flags & (DBG(TEST_VMFAULT_CP) | DBG(TEST_VMFAULT_SHADER)))
1396
si_test_vmfault(sscreen, test_flags);
1398
if (test_flags & DBG(TEST_GDS))
1399
si_test_gds((struct si_context *)sscreen->aux_context);
1401
if (test_flags & DBG(TEST_GDS_MM)) {
1402
si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 32 * 1024, 4,
1405
if (test_flags & DBG(TEST_GDS_OA_MM)) {
1406
si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 4, 1,
1410
ac_print_shadowed_regs(&sscreen->info);
1412
STATIC_ASSERT(sizeof(union si_vgt_stages_key) == 1);
1416
struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1418
drmVersionPtr version = drmGetVersion(fd);
1419
struct radeon_winsys *rw = NULL;
1421
driParseConfigFiles(config->options, config->options_info, 0, "radeonsi",
1422
NULL, NULL, NULL, 0, NULL, 0);
1424
switch (version->version_major) {
1426
rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1429
rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1433
drmFreeVersion(version);
1434
return rw ? rw->screen : NULL;
1437
struct si_context* si_get_aux_context(struct si_screen *sscreen)
1439
simple_mtx_lock(&sscreen->aux_context_lock);
1440
return (struct si_context*)sscreen->aux_context;
1443
void si_put_aux_context_flush(struct si_screen *sscreen)
1445
struct pipe_context *c = &((struct si_context*)sscreen->aux_context)->b;
1446
c->flush(c, NULL, 0);
1447
simple_mtx_unlock(&sscreen->aux_context_lock);
added
removed
src/gallium/drivers/radeonsi/si_pipe.c
